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Merge branch 'master' of git://git.denx.de/u-boot-arm
[platform/kernel/u-boot.git]
/
board
/
freescale
/
mpc8610hpcd
/
mpc8610hpcd.c
diff --git
a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index
0bf21d5
..
2ac169b
100644
(file)
--- a/
board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/
board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@
-25,28
+25,26
@@
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
-#include <asm/immap_fsl_pci.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
#include <i2c.h>
#include <asm/io.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <spd_sdram.h>
#include <i2c.h>
#include <asm/io.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <spd_sdram.h>
+#include <netdev.h>
#include "../common/pixis.h"
#include "../common/pixis.h"
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
void sdram_init(void);
void sdram_init(void);
-
long in
t fixed_sdram(void);
+
phys_size_
t fixed_sdram(void);
void mpc8610hpcd_diu_init(void);
/* called before any console output */
int board_early_init_f(void)
{
void mpc8610hpcd_diu_init(void);
/* called before any console output */
int board_early_init_f(void)
{
- volatile immap_t *immap = (immap_t *)C
FG
_IMMR;
+ volatile immap_t *immap = (immap_t *)C
ONFIG_SYS
_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
volatile ccsr_gur_t *gur = &immap->im_gur;
gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
@@
-57,16
+55,17
@@
int board_early_init_f(void)
int misc_init_r(void)
{
u8 tmp_val, version;
int misc_init_r(void)
{
u8 tmp_val, version;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
/*Do not use 8259PIC*/
/*Do not use 8259PIC*/
- tmp_val = in
8(PIXIS_BASE
+ PIXIS_BRDCFG0);
- out
8(PIXIS_BASE
+ PIXIS_BRDCFG0, tmp_val | 0x80);
+ tmp_val = in
_8(pixis_base
+ PIXIS_BRDCFG0);
+ out
_8(pixis_base
+ PIXIS_BRDCFG0, tmp_val | 0x80);
/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
- version = in
8(PIXIS_BASE
+ PIXIS_PVER);
+ version = in
_8(pixis_base
+ PIXIS_PVER);
if(version >= 0x07) {
if(version >= 0x07) {
- tmp_val = in
8(PIXIS_BASE
+ PIXIS_BRDCFG0);
- out
8(PIXIS_BASE
+ PIXIS_BRDCFG0, tmp_val & 0xbf);
+ tmp_val = in
_8(pixis_base
+ PIXIS_BRDCFG0);
+ out
_8(pixis_base
+ PIXIS_BRDCFG0, tmp_val & 0xbf);
}
/* Using this for DIU init before the driver in linux takes over
}
/* Using this for DIU init before the driver in linux takes over
@@
-96,13
+95,14
@@
int misc_init_r(void)
int checkboard(void)
{
int checkboard(void)
{
- volatile immap_t *immap = (immap_t *)C
FG
_IMMR;
+ volatile immap_t *immap = (immap_t *)C
ONFIG_SYS
_IMMR;
volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- printf ("Board: MPC8610HPCD, System ID: 0x%02
l
x, "
- "System Version: 0x%02
lx, FPGA Version: 0x%02l
x\n",
- in
8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE
+ PIXIS_VER),
- in
8(PIXIS_BASE
+ PIXIS_PVER));
+ printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
+ "System Version: 0x%02
x, FPGA Version: 0x%02
x\n",
+ in
_8(pixis_base + PIXIS_ID), in_8(pixis_base
+ PIXIS_VER),
+ in
_8(pixis_base
+ PIXIS_PVER));
mcm->abcr |= 0x00010000; /* 0 */
mcm->hpmr3 = 0x80000008; /* 4c */
mcm->abcr |= 0x00010000; /* 0 */
mcm->hpmr3 = 0x80000008; /* 4c */
@@
-119,26
+119,19
@@
int checkboard(void)
phys_size_t
initdram(int board_type)
{
phys_size_t
initdram(int board_type)
{
-
long
dram_size = 0;
+
phys_size_t
dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
#if defined(CONFIG_SPD_EEPROM)
- dram_size =
spd
_sdram();
+ dram_size =
fsl_ddr
_sdram();
#else
dram_size = fixed_sdram();
#endif
#else
dram_size = fixed_sdram();
#endif
-#if defined(C
FG
_RAMBOOT)
+#if defined(C
ONFIG_SYS
_RAMBOOT)
puts(" DDR: ");
return dram_size;
#endif
puts(" DDR: ");
return dram_size;
#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
-
puts(" DDR: ");
return dram_size;
}
puts(" DDR: ");
return dram_size;
}
@@
-149,10
+142,10
@@
initdram(int board_type)
* Fixed sdram init -- doesn't use serial presence detect.
*/
* Fixed sdram init -- doesn't use serial presence detect.
*/
-
long in
t fixed_sdram(void)
+
phys_size_
t fixed_sdram(void)
{
{
-#if !defined(C
FG
_RAMBOOT)
- volatile immap_t *immap = (immap_t *)C
FG
_IMMR;
+#if !defined(C
ONFIG_SYS
_RAMBOOT)
+ volatile immap_t *immap = (immap_t *)C
ONFIG_SYS
_IMMR;
volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
uint d_init;
volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
uint d_init;
@@
-163,7
+156,7
@@
long int fixed_sdram(void)
ddr->timing_cfg_0 = 0x00260802;
ddr->timing_cfg_1 = 0x3935d322;
ddr->timing_cfg_2 = 0x14904cc8;
ddr->timing_cfg_0 = 0x00260802;
ddr->timing_cfg_1 = 0x3935d322;
ddr->timing_cfg_2 = 0x14904cc8;
- ddr->sdram_mode
_1
= 0x00480432;
+ ddr->sdram_mode = 0x00480432;
ddr->sdram_mode_2 = 0x00000000;
ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
ddr->sdram_data_init = 0xDEADBEEF;
ddr->sdram_mode_2 = 0x00000000;
ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
ddr->sdram_data_init = 0xDEADBEEF;
@@
-179,7
+172,7
@@
long int fixed_sdram(void)
udelay(500);
udelay(500);
- ddr->sdram_cfg
_1
= 0xc3000000; /* 0xe3008000;*/
+ ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
@@
-199,7
+192,7
@@
long int fixed_sdram(void)
return 512 * 1024 * 1024;
#endif
return 512 * 1024 * 1024;
#endif
- return C
FG
_SDRAM_SIZE * 1024 * 1024;
+ return C
ONFIG_SYS
_SDRAM_SIZE * 1024 * 1024;
}
#endif
}
#endif
@@
-240,7
+233,7
@@
int first_free_busno = 0;
void pci_init_board(void)
{
void pci_init_board(void)
{
- volatile immap_t *immap = (immap_t *) C
FG
_CCSRBAR;
+ volatile immap_t *immap = (immap_t *) C
ONFIG_SYS
_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL)
volatile ccsr_gur_t *gur = &immap->im_gur;
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL)
@@
-253,12
+246,12
@@
void pci_init_board(void)
#ifdef CONFIG_PCIE1
{
#ifdef CONFIG_PCIE1
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
struct pci_controller *hose = &pcie1_hose;
int pcie_configured = (io_sel == 1) || (io_sel == 4);
int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
(host_agent == 5);
struct pci_controller *hose = &pcie1_hose;
int pcie_configured = (io_sel == 1) || (io_sel == 4);
int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
(host_agent == 5);
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
@@
-268,27
+261,23
@@
void pci_init_board(void)
pci->pme_msg_det = 0xffffffff;
/* inbound */
pci->pme_msg_det = 0xffffffff;
/* inbound */
- pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
/* outbound memory */
- pci_set_region(
hose->regions + 1
,
- C
FG_PCIE1_MEM_BASE
,
- C
FG
_PCIE1_MEM_PHYS,
- C
FG
_PCIE1_MEM_SIZE,
+ pci_set_region(
r++
,
+ C
ONFIG_SYS_PCIE1_MEM_BUS
,
+ C
ONFIG_SYS
_PCIE1_MEM_PHYS,
+ C
ONFIG_SYS
_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(
hose->regions + 2
,
- C
FG_PCIE1_IO_BASE
,
- C
FG
_PCIE1_IO_PHYS,
- C
FG
_PCIE1_IO_SIZE,
+ pci_set_region(
r++
,
+ C
ONFIG_SYS_PCIE1_IO_BUS
,
+ C
ONFIG_SYS
_PCIE1_IO_PHYS,
+ C
ONFIG_SYS
_PCIE1_IO_SIZE,
PCI_REGION_IO);
PCI_REGION_IO);
- hose->region_count =
3
;
+ hose->region_count =
r - hose->regions
;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
@@
-310,9
+299,9
@@
void pci_init_board(void)
#ifdef CONFIG_PCIE2
{
#ifdef CONFIG_PCIE2
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
struct pci_controller *hose = &pcie2_hose;
struct pci_controller *hose = &pcie2_hose;
+ struct pci_region *r = hose->regions;
int pcie_configured = (io_sel == 0) || (io_sel == 4);
int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
int pcie_configured = (io_sel == 0) || (io_sel == 4);
int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
@@
-327,27
+316,23
@@
void pci_init_board(void)
pci->pme_msg_det = 0xffffffff;
/* inbound */
pci->pme_msg_det = 0xffffffff;
/* inbound */
- pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
/* outbound memory */
- pci_set_region(
hose->regions + 1
,
- C
FG_PCIE2_MEM_BASE
,
- C
FG
_PCIE2_MEM_PHYS,
- C
FG
_PCIE2_MEM_SIZE,
+ pci_set_region(
r++
,
+ C
ONFIG_SYS_PCIE2_MEM_BUS
,
+ C
ONFIG_SYS
_PCIE2_MEM_PHYS,
+ C
ONFIG_SYS
_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(
hose->regions + 2
,
- C
FG_PCIE2_IO_BASE
,
- C
FG
_PCIE2_IO_PHYS,
- C
FG
_PCIE2_IO_SIZE,
+ pci_set_region(
r++
,
+ C
ONFIG_SYS_PCIE2_IO_BUS
,
+ C
ONFIG_SYS
_PCIE2_IO_PHYS,
+ C
ONFIG_SYS
_PCIE2_IO_SIZE,
PCI_REGION_IO);
PCI_REGION_IO);
- hose->region_count =
3
;
+ hose->region_count =
r - hose->regions
;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
@@
-368,10
+353,10
@@
void pci_init_board(void)
#ifdef CONFIG_PCI1
{
#ifdef CONFIG_PCI1
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
struct pci_controller *hose = &pci1_hose;
int pci_agent = (host_agent >= 4) && (host_agent <= 6);
struct pci_controller *hose = &pci1_hose;
int pci_agent = (host_agent >= 4) && (host_agent <= 6);
+ struct pci_region *r = hose->regions;
if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
printf(" PCI connected to PCI slots as %s" \
if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
printf(" PCI connected to PCI slots as %s" \
@@
-380,27
+365,23
@@
void pci_init_board(void)
(uint)pci);
/* inbound */
(uint)pci);
/* inbound */
- pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
/* outbound memory */
- pci_set_region(
hose->regions + 1
,
- C
FG_PCI1_MEM_BASE
,
- C
FG
_PCI1_MEM_PHYS,
- C
FG
_PCI1_MEM_SIZE,
+ pci_set_region(
r++
,
+ C
ONFIG_SYS_PCI1_MEM_BUS
,
+ C
ONFIG_SYS
_PCI1_MEM_PHYS,
+ C
ONFIG_SYS
_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(
hose->regions + 2
,
- C
FG_PCI1_IO_BASE
,
- C
FG
_PCI1_IO_PHYS,
- C
FG
_PCI1_IO_SIZE,
+ pci_set_region(
r++
,
+ C
ONFIG_SYS_PCI1_IO_BUS
,
+ C
ONFIG_SYS
_PCI1_IO_PHYS,
+ C
ONFIG_SYS
_PCI1_IO_SIZE,
PCI_REGION_IO);
PCI_REGION_IO);
- hose->region_count =
3
;
+ hose->region_count =
r - hose->regions
;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr,
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr,
@@
-423,9
+404,6
@@
void pci_init_board(void)
void
ft_board_setup(void *blob, bd_t *bd)
{
void
ft_board_setup(void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
-
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", bd->bi_busfreq / 4, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", bd->bi_busfreq / 4, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
@@
-440,36
+418,15
@@
ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
-
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
-
#ifdef CONFIG_PCI1
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
-
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
#endif
#ifdef CONFIG_PCIE1
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno
- - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
#ifdef CONFIG_PCIE2
#endif
#ifdef CONFIG_PCIE2
- path = fdt_getprop(blob, node, "pci2", NULL);
- if (path) {
- tmp[1] = pcie2_hose.last_busno
- - pcie2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
#endif
#endif
- }
}
#endif
}
#endif
@@
-483,10
+440,9
@@
get_board_sys_clk(ulong dummy)
{
u8 i;
ulong val = 0;
{
u8 i;
ulong val = 0;
- u
long a
;
+ u
8 *pixis_base = (u8 *)PIXIS_BASE
;
- a = PIXIS_BASE + PIXIS_SPD;
- i = in8(a);
+ i = in_8(pixis_base + PIXIS_SPD);
i &= 0x07;
switch (i) {
i &= 0x07;
switch (i) {
@@
-518,3
+474,18
@@
get_board_sys_clk(ulong dummy)
return val;
}
return val;
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+void board_reset(void)
+{
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+ out_8(pixis_base + PIXIS_RST, 0);
+
+ while (1)
+ ;
+}