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85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards
[platform/kernel/u-boot.git]
/
board
/
freescale
/
mpc8540ads
/
tlb.c
diff --git
a/board/freescale/mpc8540ads/tlb.c
b/board/freescale/mpc8540ads/tlb.c
index
4fe2862
..
a9925d5
100644
(file)
--- a/
board/freescale/mpc8540ads/tlb.c
+++ b/
board/freescale/mpc8540ads/tlb.c
@@
-28,16
+28,16
@@
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, C
FG_INIT_RAM_ADDR, CFG
_INIT_RAM_ADDR,
+ SET_TLB_ENTRY(0, C
ONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS
_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, C
FG_INIT_RAM_ADDR + 4 * 1024 , CFG
_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY(0, C
ONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS
_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, C
FG_INIT_RAM_ADDR + 8 * 1024 , CFG
_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY(0, C
ONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS
_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, C
FG_INIT_RAM_ADDR + 12 * 1024 , CFG
_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY(0, C
ONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS
_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
@@
-46,7
+46,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* 0xff000000 16M FLASH
* Out of reset this entry is only 4K.
*/
* 0xff000000 16M FLASH
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, C
FG_FLASH_BASE, CFG
_FLASH_BASE,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_FLASH_BASE, CONFIG_SYS
_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
@@
-54,7
+54,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- SET_TLB_ENTRY(1, C
FG_PCI1_MEM_PHYS, CFG
_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS
_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
@@
-62,7
+62,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- SET_TLB_ENTRY(1, C
FG_PCI1_MEM_PHYS + 0x10000000, CFG
_PCI1_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS
_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
@@
-70,7
+70,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 3: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
* TLB 3: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
- SET_TLB_ENTRY(1, C
FG_RIO_MEM_BASE, CFG_RIO_MEM_BASE
,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS
,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
@@
-78,7
+78,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 4: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
* TLB 4: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
- SET_TLB_ENTRY(1, C
FG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE
+ 0x10000000,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS
+ 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
@@
-87,7
+87,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
- SET_TLB_ENTRY(1, C
FG_CCSRBAR, CFG
_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_CCSRBAR, CONFIG_SYS
_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64M, 1),
@@
-95,7
+95,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- SET_TLB_ENTRY(1, C
FG_LBC_SDRAM_BASE, CFG
_LBC_SDRAM_BASE,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS
_LBC_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 6, BOOKE_PAGESZ_64M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 6, BOOKE_PAGESZ_64M, 1),
@@
-103,7
+103,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 7: 16K Non-cacheable, guarded
* 0xf8000000 16K BCSR registers
*/
* TLB 7: 16K Non-cacheable, guarded
* 0xf8000000 16K BCSR registers
*/
- SET_TLB_ENTRY(1, C
FG_BCSR, CFG
_BCSR,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_BCSR, CONFIG_SYS
_BCSR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_16K, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_16K, 1),
@@
-117,11
+117,11
@@
struct fsl_e_tlb_entry tlb_table[] = {
* Likely it needs to be increased by two for these entries.
*/
#error("Update the number of table entries in tlb1_entry")
* Likely it needs to be increased by two for these entries.
*/
#error("Update the number of table entries in tlb1_entry")
- SET_TLB_ENTRY(1, C
FG_DDR_SDRAM_BASE, CFG
_DDR_SDRAM_BASE,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS
_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_64M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_64M, 1),
- SET_TLB_ENTRY(1, C
FG_DDR_SDRAM_BASE + 0x4000000, CFG
_DDR_SDRAM_BASE + 0x4000000,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS
_DDR_SDRAM_BASE + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_64M, 1),
#endif
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_64M, 1),
#endif