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rename CFG_ macros to CONFIG_SYS
[platform/kernel/u-boot.git]
/
board
/
freescale
/
mpc8266ads
/
mpc8266ads.c
diff --git
a/board/freescale/mpc8266ads/mpc8266ads.c
b/board/freescale/mpc8266ads/mpc8266ads.c
index
090a534
..
66acc41
100644
(file)
--- a/
board/freescale/mpc8266ads/mpc8266ads.c
+++ b/
board/freescale/mpc8266ads/mpc8266ads.c
@@
-224,7
+224,7
@@
typedef struct pci_ic_s {
void reset_phy(void)
{
void reset_phy(void)
{
- volatile bcsr_t *bcsr = (bcsr_t *)C
FG
_BCSR;
+ volatile bcsr_t *bcsr = (bcsr_t *)C
ONFIG_SYS
_BCSR;
/* reset the FEC port */
bcsr->bcsr1 &= ~FETH_RST;
/* reset the FEC port */
bcsr->bcsr1 &= ~FETH_RST;
@@
-234,8
+234,8
@@
void reset_phy(void)
int board_early_init_f (void)
{
int board_early_init_f (void)
{
- volatile bcsr_t *bcsr = (bcsr_t *)C
FG
_BCSR;
- volatile pci_ic_t *pci_ic = (pci_ic_t *) C
FG
_PCI_INT;
+ volatile bcsr_t *bcsr = (bcsr_t *)C
ONFIG_SYS
_BCSR;
+ volatile pci_ic_t *pci_ic = (pci_ic_t *) C
ONFIG_SYS
_PCI_INT;
bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2;
bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2;
@@
-254,17
+254,17
@@
int checkboard(void)
phys_size_t initdram(int board_type)
{
/* Autoinit part stolen from board/sacsng/sacsng.c */
phys_size_t initdram(int board_type)
{
/* Autoinit part stolen from board/sacsng/sacsng.c */
- volatile immap_t *immap = (immap_t *)C
FG
_IMMR;
+ volatile immap_t *immap = (immap_t *)C
ONFIG_SYS
_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar c = 0xff;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar c = 0xff;
- volatile uchar *ramaddr = (uchar *)(C
FG
_SDRAM_BASE + 0x8);
- uint psdmr = C
FG
_PSDMR;
+ volatile uchar *ramaddr = (uchar *)(C
ONFIG_SYS
_SDRAM_BASE + 0x8);
+ uint psdmr = C
ONFIG_SYS
_PSDMR;
int i;
uint psrt = 0x21; /* for no SPD */
uint chipselects = 1; /* for no SPD */
int i;
uint psrt = 0x21; /* for no SPD */
uint chipselects = 1; /* for no SPD */
- uint sdram_size = C
FG_SDRAM_SIZE * 1024 * 1024;
/* for no SPD */
- uint or = C
FG_OR2_PRELIM;
/* for no SPD */
+ uint sdram_size = C
ONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
/* for no SPD */
+ uint or = C
ONFIG_SYS_OR2_PRELIM;
/* for no SPD */
uint data_width;
uint rows;
uint banks;
uint data_width;
uint rows;
uint banks;
@@
-286,7
+286,7
@@
phys_size_t initdram(int board_type)
/*
* Read the SDRAM SPD EEPROM via I2C.
*/
/*
* Read the SDRAM SPD EEPROM via I2C.
*/
- i2c_init (C
FG_I2C_SPEED, CFG
_I2C_SLAVE);
+ i2c_init (C
ONFIG_SYS_I2C_SPEED, CONFIG_SYS
_I2C_SLAVE);
i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
spd_size = data;
i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
spd_size = data;
@@
-506,13
+506,13
@@
phys_size_t initdram(int board_type)
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address C
FG
_SDRAM_BASE.
+ * get here. The SDRAM can be accessed at the address C
ONFIG_SYS
_SDRAM_BASE.
*/
*/
- memctl->memc_mptpr = C
FG
_MPTPR;
+ memctl->memc_mptpr = C
ONFIG_SYS
_MPTPR;
memctl->memc_psrt = psrt;
memctl->memc_psrt = psrt;
- memctl->memc_br2 = C
FG
_BR2_PRELIM;
+ memctl->memc_br2 = C
ONFIG_SYS
_BR2_PRELIM;
memctl->memc_or2 = or;
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
memctl->memc_or2 = or;
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
@@
-536,7
+536,7
@@
phys_size_t initdram(int board_type)
{
ramaddr += sdram_size;
{
ramaddr += sdram_size;
- memctl->memc_br3 = C
FG
_BR3_PRELIM + sdram_size;
+ memctl->memc_br3 = C
ONFIG_SYS
_BR3_PRELIM + sdram_size;
memctl->memc_or3 = or;
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
memctl->memc_or3 = or;
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;