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Merge tag 'u-boot-rockchip-20200501' of https://gitlab.denx.de/u-boot/custodians...
[platform/kernel/u-boot.git]
/
board
/
freescale
/
ls1046aqds
/
ls1046aqds.c
diff --git
a/board/freescale/ls1046aqds/ls1046aqds.c
b/board/freescale/ls1046aqds/ls1046aqds.c
index
b71c174
..
e6648e9
100644
(file)
--- a/
board/freescale/ls1046aqds/ls1046aqds.c
+++ b/
board/freescale/ls1046aqds/ls1046aqds.c
@@
-1,6
+1,7
@@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
*/
#include <common.h>
*/
#include <common.h>
@@
-269,11
+270,23
@@
u32 get_lpuart_clk(void)
}
#endif
}
#endif
-int select_i2c_ch_pca9547(u8 ch)
+int select_i2c_ch_pca9547(u8 ch
, int bus_num
)
{
int ret;
{
int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+ ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+ 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find udev for a bus %d\n", __func__,
+ bus_num);
+ return ret;
+ }
+ ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@@
-288,8
+301,10
@@
int dram_init(void)
* When resuming from deep sleep, the I2C channel may not be
* in the default channel. So, switch to the default channel
* before accessing DDR SPD.
* When resuming from deep sleep, the I2C channel may not be
* in the default channel. So, switch to the default channel
* before accessing DDR SPD.
+ *
+ * PCA9547 mount on I2C1 bus
*/
*/
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT
, 0
);
fsl_initdram();
#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
defined(CONFIG_SPL_BUILD)
fsl_initdram();
#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
defined(CONFIG_SPL_BUILD)
@@
-302,7
+317,7
@@
int dram_init(void)
int i2c_multiplexer_select_vid_channel(u8 channel)
{
int i2c_multiplexer_select_vid_channel(u8 channel)
{
- return select_i2c_ch_pca9547(channel);
+ return select_i2c_ch_pca9547(channel
, 0
);
}
int board_early_init_f(void)
}
int board_early_init_f(void)
@@
-315,9
+330,11
@@
int board_early_init_f(void)
u8 uart;
#endif
u8 uart;
#endif
+#ifdef CONFIG_SYS_I2C
#ifdef CONFIG_SYS_I2C_EARLY_INIT
i2c_early_init_f();
#endif
#ifdef CONFIG_SYS_I2C_EARLY_INIT
i2c_early_init_f();
#endif
+#endif
fsl_lsch2_early_init_f();
#ifdef CONFIG_HAS_FSL_XHCI_USB
fsl_lsch2_early_init_f();
#ifdef CONFIG_HAS_FSL_XHCI_USB
@@
-394,7
+411,7
@@
int misc_init_r(void)
int board_init(void)
{
int board_init(void)
{
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT
, 0
);
#ifdef CONFIG_SYS_FSL_SERDES
config_serdes_mux();
#ifdef CONFIG_SYS_FSL_SERDES
config_serdes_mux();
@@
-407,7
+424,7
@@
int board_init(void)
ppa_init();
#endif
ppa_init();
#endif
-#ifdef CONFIG_
SECURE_BOOT
+#ifdef CONFIG_
NXP_ESBC
/*
* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
/*
* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@
-445,7
+462,9
@@
int ft_board_setup(void *blob, bd_t *bd)
ft_cpu_setup(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
ft_cpu_setup(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
fdt_fixup_fman_ethernet(blob);
+#endif
fdt_fixup_board_enet(blob);
#endif
fdt_fixup_board_enet(blob);
#endif
@@
-482,7
+501,7
@@
u16 flash_read16(void *addr)
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
-#if
def CONFIG_TFABOOT
+#if
defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
void *env_sf_get_env_addr(void)
{
return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
void *env_sf_get_env_addr(void)
{
return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);