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layerscape: Disable CONFIG_FMAN_ENET on *aqds* platforms
[platform/kernel/u-boot.git]
/
board
/
freescale
/
corenet_ds
/
eth_superhydra.c
diff --git
a/board/freescale/corenet_ds/eth_superhydra.c
b/board/freescale/corenet_ds/eth_superhydra.c
index
ad1bffd
..
55bac0f
100644
(file)
--- a/
board/freescale/corenet_ds/eth_superhydra.c
+++ b/
board/freescale/corenet_ds/eth_superhydra.c
@@
-1,8
+1,7
@@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
* Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
* Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
*/
/*
@@
-49,13
+48,15
@@
*/
#include <common.h>
*/
#include <common.h>
+#include <log.h>
+#include <net.h>
#include <netdev.h>
#include <asm/fsl_serdes.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <malloc.h>
#include <fdt_support.h>
#include <netdev.h>
#include <asm/fsl_serdes.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <malloc.h>
#include <fdt_support.h>
-#include <
asm/
fsl_dtsec.h>
+#include <fsl_dtsec.h>
#include "../common/ngpixis.h"
#include "../common/fman.h"
#include "../common/ngpixis.h"
#include "../common/fman.h"
@@
-175,7
+176,7
@@
static int super_hydra_mdio_init(char *realbusname, char *fakebusname)
bus->read = super_hydra_mdio_read;
bus->write = super_hydra_mdio_write;
bus->reset = super_hydra_mdio_reset;
bus->read = super_hydra_mdio_read;
bus->write = super_hydra_mdio_write;
bus->reset = super_hydra_mdio_reset;
- s
printf
(bus->name, fakebusname);
+ s
trcpy
(bus->name, fakebusname);
hmdio->realbus = miiphy_get_dev_by_name(realbusname);
hmdio->realbus = miiphy_get_dev_by_name(realbusname);
@@
-316,6
+317,9
@@
void fdt_fixup_board_enet(void *fdt)
}
break;
case PHY_INTERFACE_MODE_RGMII:
}
break;
case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
fdt_status_okay_by_alias(fdt, "hydra_rg");
debug("Enabled MDIO node hydra_rg\n");
break;
fdt_status_okay_by_alias(fdt, "hydra_rg");
debug("Enabled MDIO node hydra_rg\n");
break;
@@
-352,6
+356,9
@@
void fdt_fixup_board_enet(void *fdt)
}
break;
case PHY_INTERFACE_MODE_RGMII:
}
break;
case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
fdt_status_okay_by_alias(fdt, "hydra_rg");
debug("Enabled MDIO node hydra_rg\n");
break;
fdt_status_okay_by_alias(fdt, "hydra_rg");
debug("Enabled MDIO node hydra_rg\n");
break;
@@
-414,7
+421,7
@@
void fdt_fixup_board_enet(void *fdt)
* 0x36 | | |
*/
* 0x36 | | |
*/
-int board_eth_init(
bd_t
*bis)
+int board_eth_init(
struct bd_info
*bis)
{
#ifdef CONFIG_FMAN_ENET
struct fsl_pq_mdio_info dtsec_mdio_info;
{
#ifdef CONFIG_FMAN_ENET
struct fsl_pq_mdio_info dtsec_mdio_info;
@@
-556,6
+563,9
@@
int board_eth_init(bd_t *bis)
miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_RGMII:
miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
/*
* FM1 DTSEC5 is routed via EC1 to the first on-board
* RGMII port. FM2 DTSEC5 is routed via EC2 to the
/*
* FM1 DTSEC5 is routed via EC1 to the first on-board
* RGMII port. FM2 DTSEC5 is routed via EC2 to the
@@
-573,7
+583,7
@@
int board_eth_init(bd_t *bis)
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
break;
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
break;
- case PHY_INTERFACE_MODE_N
ONE
:
+ case PHY_INTERFACE_MODE_N
A
:
fm_info_set_phy_address(i, 0);
break;
default:
fm_info_set_phy_address(i, 0);
break;
default:
@@
-703,6
+713,9
@@
int board_eth_init(bd_t *bis)
break;
case PHY_INTERFACE_MODE_RGMII:
break;
case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
/*
* FM1 DTSEC5 is routed via EC1 to the first on-board
* RGMII port. FM2 DTSEC5 is routed via EC2 to the
/*
* FM1 DTSEC5 is routed via EC1 to the first on-board
* RGMII port. FM2 DTSEC5 is routed via EC2 to the
@@
-720,7
+733,7
@@
int board_eth_init(bd_t *bis)
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
break;
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
break;
- case PHY_INTERFACE_MODE_N
ONE
:
+ case PHY_INTERFACE_MODE_N
A
:
fm_info_set_phy_address(i, 0);
break;
default:
fm_info_set_phy_address(i, 0);
break;
default: