*/
out32(GPIO0_OR, 0x40000002);
out32(GPIO0_TCR, 0x4c90011f);
*/
out32(GPIO0_OR, 0x40000002);
out32(GPIO0_TCR, 0x4c90011f);
#ifdef CONFIG_ENV_IS_IN_FLASH
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
#ifdef CONFIG_ENV_IS_IN_FLASH
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
void pci_target_init(struct pci_controller *hose)
{
char *ptmla_str, *ptmms_str;
void pci_target_init(struct pci_controller *hose)
{
char *ptmla_str, *ptmms_str;
*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
- out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
/* and enable region */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
/* and enable region */
/* Program the board's vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
/* Program the board's vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
if (!is_monarch()) {
/* Program the board's subsystem id/classcode */
pci_write_config_word(0, PCI_SUBSYSTEM_ID,
if (!is_monarch()) {
/* Program the board's subsystem id/classcode */
pci_write_config_word(0, PCI_SUBSYSTEM_ID,
/* PCI configuration done: release ERREADY */
out_be32((void*)GPIO1_OR,
/* PCI configuration done: release ERREADY */
out_be32((void*)GPIO1_OR,
} else {
/* Program the board's subsystem id/classcode */
pci_write_config_word(0, PCI_SUBSYSTEM_ID,
} else {
/* Program the board's subsystem id/classcode */
pci_write_config_word(0, PCI_SUBSYSTEM_ID,
int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
uchar *buffer, unsigned cnt)
{
int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
uchar *buffer, unsigned cnt)
{
#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
maxlen = BOOT_EEPROM_PAGE_SIZE -
#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
maxlen = BOOT_EEPROM_PAGE_SIZE -