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rename CFG_ macros to CONFIG_SYS
[platform/kernel/u-boot.git]
/
board
/
esd
/
du440
/
du440.c
diff --git
a/board/esd/du440/du440.c
b/board/esd/du440/du440.c
index
6dca35d
..
2f97a12
100644
(file)
--- a/
board/esd/du440/du440.c
+++ b/
board/esd/du440/du440.c
@@
-29,7
+29,7
@@
DECLARE_GLOBAL_DATA_PTR;
DECLARE_GLOBAL_DATA_PTR;
-extern flash_info_t flash_info[C
FG
_MAX_FLASH_BANKS];
+extern flash_info_t flash_info[C
ONFIG_SYS
_MAX_FLASH_BANKS];
extern ulong flash_get_size (ulong base, int banknum);
int usbhub_init(void);
extern ulong flash_get_size (ulong base, int banknum);
int usbhub_init(void);
@@
-51,8
+51,8
@@
int board_early_init_f(void)
/*
* Setup the GPIO pins
*/
/*
* Setup the GPIO pins
*/
- out_be32((void*)GPIO0_OR, 0x00000000 | C
FG
_GPIO0_EP_EEP);
- out_be32((void*)GPIO0_TCR, 0x0000001f | C
FG
_GPIO0_EP_EEP);
+ out_be32((void*)GPIO0_OR, 0x00000000 | C
ONFIG_SYS
_GPIO0_EP_EEP);
+ out_be32((void*)GPIO0_TCR, 0x0000001f | C
ONFIG_SYS
_GPIO0_EP_EEP);
out_be32((void*)GPIO0_OSRL, 0x50055400);
out_be32((void*)GPIO0_OSRH, 0x55005000);
out_be32((void*)GPIO0_TSRL, 0x50055400);
out_be32((void*)GPIO0_OSRL, 0x50055400);
out_be32((void*)GPIO0_OSRH, 0x55005000);
out_be32((void*)GPIO0_TSRL, 0x50055400);
@@
-66,13
+66,13
@@
int board_early_init_f(void)
out_be32((void*)GPIO1_OR, 0x00000000);
out_be32((void*)GPIO1_TCR, 0xc2000000 |
out_be32((void*)GPIO1_OR, 0x00000000);
out_be32((void*)GPIO1_TCR, 0xc2000000 |
- C
FG
_GPIO1_IORSTN |
- C
FG
_GPIO1_IORST2N |
- C
FG
_GPIO1_LEDUSR1 |
- C
FG
_GPIO1_LEDUSR2 |
- C
FG
_GPIO1_LEDPOST |
- C
FG
_GPIO1_LEDDU);
- out_be32((void*)GPIO1_ODR, C
FG
_GPIO1_LEDDU);
+ C
ONFIG_SYS
_GPIO1_IORSTN |
+ C
ONFIG_SYS
_GPIO1_IORST2N |
+ C
ONFIG_SYS
_GPIO1_LEDUSR1 |
+ C
ONFIG_SYS
_GPIO1_LEDUSR2 |
+ C
ONFIG_SYS
_GPIO1_LEDPOST |
+ C
ONFIG_SYS
_GPIO1_LEDDU);
+ out_be32((void*)GPIO1_ODR, C
ONFIG_SYS
_GPIO1_LEDDU);
out_be32((void*)GPIO1_OSRL, 0x0c280000);
out_be32((void*)GPIO1_OSRH, 0x00000000);
out_be32((void*)GPIO1_TSRL, 0xcc000000);
out_be32((void*)GPIO1_OSRL, 0x0c280000);
out_be32((void*)GPIO1_OSRH, 0x00000000);
out_be32((void*)GPIO1_TSRL, 0xcc000000);
@@
-154,8
+154,8
@@
int board_early_init_f(void)
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
- (0x80000000 >> (28 + C
FG
_NAND0_CS)) |
- (0x80000000 >> (28 + C
FG
_NAND1_CS));
+ (0x80000000 >> (28 + C
ONFIG_SYS
_NAND0_CS)) |
+ (0x80000000 >> (28 + C
ONFIG_SYS
_NAND1_CS));
mtsdr(SDR0_CUST0, sdr0_cust0);
return 0;
mtsdr(SDR0_CUST0, sdr0_cust0);
return 0;
@@
-273,7
+273,7
@@
int misc_init_r(void)
* We have to wait at least 560ms until we may call usbhub_init
*/
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
* We have to wait at least 560ms until we may call usbhub_init
*/
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
- C
FG_GPIO1_IORSTN | CFG
_GPIO1_IORST2N);
+ C
ONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS
_GPIO1_IORST2N);
/*
* flash USR1/2 LEDs (600ms)
/*
* flash USR1/2 LEDs (600ms)
@@
-282,22
+282,22
@@
int misc_init_r(void)
*/
for (j = 0; j < 3; j++) {
out_be32((void*)GPIO1_OR,
*/
for (j = 0; j < 3; j++) {
out_be32((void*)GPIO1_OR,
- (in_be32((void*)GPIO1_OR) & ~C
FG
_GPIO1_LEDUSR2) |
- C
FG
_GPIO1_LEDUSR1);
+ (in_be32((void*)GPIO1_OR) & ~C
ONFIG_SYS
_GPIO1_LEDUSR2) |
+ C
ONFIG_SYS
_GPIO1_LEDUSR1);
for (i = 0; i < 100; i++)
udelay(1000);
out_be32((void*)GPIO1_OR,
for (i = 0; i < 100; i++)
udelay(1000);
out_be32((void*)GPIO1_OR,
- (in_be32((void*)GPIO1_OR) & ~C
FG
_GPIO1_LEDUSR1) |
- C
FG
_GPIO1_LEDUSR2);
+ (in_be32((void*)GPIO1_OR) & ~C
ONFIG_SYS
_GPIO1_LEDUSR1) |
+ C
ONFIG_SYS
_GPIO1_LEDUSR2);
for (i = 0; i < 100; i++)
udelay(1000);
}
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
for (i = 0; i < 100; i++)
udelay(1000);
}
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
- ~(C
FG_GPIO1_LEDUSR1 | CFG
_GPIO1_LEDUSR2));
+ ~(C
ONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS
_GPIO1_LEDUSR2));
if (usbhub_init())
du440_post_errors++;
if (usbhub_init())
du440_post_errors++;
@@
-310,14
+310,14
@@
int misc_init_r(void)
int pld_revision(void)
{
int pld_revision(void)
{
- out8(C
FG
_CPLD_BASE, 0x00);
- return (int)(in8(C
FG
_CPLD_BASE) & CPLD_VERSION_MASK);
+ out8(C
ONFIG_SYS
_CPLD_BASE, 0x00);
+ return (int)(in8(C
ONFIG_SYS
_CPLD_BASE) & CPLD_VERSION_MASK);
}
int board_revision(void)
{
}
int board_revision(void)
{
- int rpins = (int)((in_be32((void*)GPIO1_IR) & C
FG
_GPIO1_HWVER_MASK)
- >> C
FG
_GPIO1_HWVER_SHIFT);
+ int rpins = (int)((in_be32((void*)GPIO1_IR) & C
ONFIG_SYS
_GPIO1_HWVER_MASK)
+ >> C
ONFIG_SYS
_GPIO1_HWVER_SHIFT);
return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
((rpins & 4) >> 1) | ((rpins & 8) >> 3);
return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
((rpins & 4) >> 1) | ((rpins & 8) >> 3);
@@
-328,7
+328,7
@@
void board_show_activity (ulong timestamp)
{
if ((timestamp % 100) == 0)
out_be32((void*)GPIO1_OR,
{
if ((timestamp % 100) == 0)
out_be32((void*)GPIO1_OR,
- in_be32((void*)GPIO1_OR) ^ C
FG
_GPIO1_LEDUSR1);
+ in_be32((void*)GPIO1_OR) ^ C
ONFIG_SYS
_GPIO1_LEDUSR1);
}
void show_activity(int arg)
}
void show_activity(int arg)
@@
-421,7
+421,7
@@
int pci_pre_init(struct pci_controller *hose)
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
-#if defined(CONFIG_PCI) && defined(C
FG
_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(C
ONFIG_SYS
_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*
void pci_target_init(struct pci_controller *hose)
{
/*
@@
-437,16
+437,16
@@
void pci_target_init(struct pci_controller *hose)
*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
- out32r(PCIX0_PMM0LA, C
FG_PCI_MEMBASE);
/* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, C
FG
_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0LA, C
ONFIG_SYS_PCI_MEMBASE);
/* PMM0 Local Address */
+ out32r(PCIX0_PMM0PCILA, C
ONFIG_SYS
_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
- out32r(PCIX0_PMM1LA, C
FG
_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIX0_PMM1PCILA, C
FG
_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM1LA, C
ONFIG_SYS
_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIX0_PMM1PCILA, C
ONFIG_SYS
_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
@@
-479,9
+479,9
@@
void pci_target_init(struct pci_controller *hose)
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
-#endif /* defined(CONFIG_PCI) && defined(C
FG
_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(C
ONFIG_SYS
_PCI_TARGET_INIT) */
-#if defined(CONFIG_PCI) && defined(C
FG
_PCI_MASTER_INIT)
+#if defined(CONFIG_PCI) && defined(C
ONFIG_SYS
_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
@@
-496,7
+496,7
@@
void pci_master_init(struct pci_controller *hose)
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
-#endif /* defined(CONFIG_PCI) && defined(C
FG
_PCI_MASTER_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(C
ONFIG_SYS
_PCI_MASTER_INIT) */
/*
* is_pci_host
/*
* is_pci_host
@@
-524,18
+524,18
@@
int last_stage_init(void)
int e, i;
/* everyting is ok: turn on POST-LED */
int e, i;
/* everyting is ok: turn on POST-LED */
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | C
FG
_GPIO1_LEDPOST);
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | C
ONFIG_SYS
_GPIO1_LEDPOST);
/* slowly blink on errors and finally keep LED off */
for (e = 0; e < du440_post_errors; e++) {
out_be32((void*)GPIO1_OR,
/* slowly blink on errors and finally keep LED off */
for (e = 0; e < du440_post_errors; e++) {
out_be32((void*)GPIO1_OR,
- in_be32((void*)GPIO1_OR) | C
FG
_GPIO1_LEDPOST);
+ in_be32((void*)GPIO1_OR) | C
ONFIG_SYS
_GPIO1_LEDPOST);
for (i = 0; i < 500; i++)
udelay(1000);
out_be32((void*)GPIO1_OR,
for (i = 0; i < 500; i++)
udelay(1000);
out_be32((void*)GPIO1_OR,
- in_be32((void*)GPIO1_OR) & ~C
FG
_GPIO1_LEDPOST);
+ in_be32((void*)GPIO1_OR) & ~C
ONFIG_SYS
_GPIO1_LEDPOST);
for (i = 0; i < 500; i++)
udelay(1000);
for (i = 0; i < 500; i++)
udelay(1000);
@@
-583,9
+583,9
@@
int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf("ERROR - no signal\n");
t1 = t2 = 0;
printf("ERROR - no signal\n");
t1 = t2 = 0;
- pinold = in_be32((void*)GPIO1_IR) & C
FG
_GPIO1_DCF77;
+ pinold = in_be32((void*)GPIO1_IR) & C
ONFIG_SYS
_GPIO1_DCF77;
while (!ctrlc()) {
while (!ctrlc()) {
- pin = in_be32((void*)GPIO1_IR) & C
FG
_GPIO1_DCF77;
+ pin = in_be32((void*)GPIO1_IR) & C
ONFIG_SYS
_GPIO1_DCF77;
if (pin && !pinold) { /* bit start */
t1 = get_ticks();
if (t2 && ((unsigned int)(t1 - t2) /
if (pin && !pinold) { /* bit start */
t1 = get_ticks();
if (t2 && ((unsigned int)(t1 - t2) /
@@
-661,7
+661,7
@@
U_BOOT_CMD(
);
#endif /* CONFIG_I2C_MULTI_BUS */
);
#endif /* CONFIG_I2C_MULTI_BUS */
-#define C
FG
_BOOT_EEPROM_PAGE_WRITE_BITS 3
+#define C
ONFIG_SYS
_BOOT_EEPROM_PAGE_WRITE_BITS 3
int boot_eeprom_write (unsigned dev_addr,
unsigned offset,
uchar *buffer,
int boot_eeprom_write (unsigned dev_addr,
unsigned offset,
uchar *buffer,
@@
-671,7
+671,7
@@
int boot_eeprom_write (unsigned dev_addr,
unsigned blk_off;
int rcode = 0;
unsigned blk_off;
int rcode = 0;
-#if defined(C
FG
_EEPROM_WREN)
+#if defined(C
ONFIG_SYS
_EEPROM_WREN)
eeprom_write_enable(dev_addr, 1);
#endif
/*
eeprom_write_enable(dev_addr, 1);
#endif
/*
@@
-700,9
+700,9
@@
int boot_eeprom_write (unsigned dev_addr,
* bytes that can be ccessed with the single read or write
* operation.
*/
* bytes that can be ccessed with the single read or write
* operation.
*/
-#if defined(C
FG
_BOOT_EEPROM_PAGE_WRITE_BITS)
+#if defined(C
ONFIG_SYS
_BOOT_EEPROM_PAGE_WRITE_BITS)
-#define BOOT_EEPROM_PAGE_SIZE (1 << C
FG
_BOOT_EEPROM_PAGE_WRITE_BITS)
+#define BOOT_EEPROM_PAGE_SIZE (1 << C
ONFIG_SYS
_BOOT_EEPROM_PAGE_WRITE_BITS)
#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
maxlen = BOOT_EEPROM_PAGE_SIZE -
#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
maxlen = BOOT_EEPROM_PAGE_SIZE -
@@
-722,11
+722,11
@@
int boot_eeprom_write (unsigned dev_addr,
buffer += len;
offset += len;
buffer += len;
offset += len;
-#if defined(C
FG
_EEPROM_PAGE_WRITE_DELAY_MS)
- udelay(C
FG
_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#if defined(C
ONFIG_SYS
_EEPROM_PAGE_WRITE_DELAY_MS)
+ udelay(C
ONFIG_SYS
_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
}
#endif
}
-#if defined(C
FG
_EEPROM_WREN)
+#if defined(C
ONFIG_SYS
_EEPROM_WREN)
eeprom_write_enable(dev_addr, 0);
#endif
return rcode;
eeprom_write_enable(dev_addr, 0);
#endif
return rcode;
@@
-779,7
+779,7
@@
int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
printf("Writing boot EEPROM ...\n");
}
printf("Writing boot EEPROM ...\n");
- if (boot_eeprom_write(C
FG
_I2C_BOOT_EEPROM_ADDR,
+ if (boot_eeprom_write(C
ONFIG_SYS
_I2C_BOOT_EEPROM_ADDR,
0, (uchar*)sdsdp, 16) != 0)
printf("boot_eeprom_write failed\n");
else
0, (uchar*)sdsdp, 16) != 0)
printf("boot_eeprom_write failed\n");
else
@@
-793,7
+793,7
@@
U_BOOT_CMD(
NULL
);
NULL
);
-#if defined(C
FG
_EEPROM_WREN)
+#if defined(C
ONFIG_SYS
_EEPROM_WREN)
/*
* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
/*
* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
@@
-805,27
+805,27
@@
U_BOOT_CMD(
*/
int eeprom_write_enable (unsigned dev_addr, int state)
{
*/
int eeprom_write_enable (unsigned dev_addr, int state)
{
- if ((C
FG
_I2C_EEPROM_ADDR != dev_addr) &&
- (C
FG
_I2C_BOOT_EEPROM_ADDR != dev_addr))
+ if ((C
ONFIG_SYS
_I2C_EEPROM_ADDR != dev_addr) &&
+ (C
ONFIG_SYS
_I2C_BOOT_EEPROM_ADDR != dev_addr))
return -1;
else {
switch (state) {
case 1:
/* Enable write access, clear bit GPIO_SINT2. */
out_be32((void*)GPIO0_OR,
return -1;
else {
switch (state) {
case 1:
/* Enable write access, clear bit GPIO_SINT2. */
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) & ~C
FG
_GPIO0_EP_EEP);
+ in_be32((void*)GPIO0_OR) & ~C
ONFIG_SYS
_GPIO0_EP_EEP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO_SINT2. */
out_be32((void*)GPIO0_OR,
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO_SINT2. */
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) | C
FG
_GPIO0_EP_EEP);
+ in_be32((void*)GPIO0_OR) | C
ONFIG_SYS
_GPIO0_EP_EEP);
state = 0;
break;
default:
/* Read current status back. */
state = (0 == (in_be32((void*)GPIO0_OR) &
state = 0;
break;
default:
/* Read current status back. */
state = (0 == (in_be32((void*)GPIO0_OR) &
- C
FG
_GPIO0_EP_EEP));
+ C
ONFIG_SYS
_GPIO0_EP_EEP));
break;
}
}
break;
}
}
@@
-839,21
+839,21
@@
int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (query) {
/* Query write access state. */
if (query) {
/* Query write access state. */
- state = eeprom_write_enable(C
FG
_I2C_EEPROM_ADDR, -1);
+ state = eeprom_write_enable(C
ONFIG_SYS
_I2C_EEPROM_ADDR, -1);
if (state < 0)
puts ("Query of write access state failed.\n");
else {
printf ("Write access for device 0x%0x is %sabled.\n",
if (state < 0)
puts ("Query of write access state failed.\n");
else {
printf ("Write access for device 0x%0x is %sabled.\n",
- C
FG
_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ C
ONFIG_SYS
_I2C_EEPROM_ADDR, state ? "en" : "dis");
state = 0;
}
} else {
if ('0' == argv[1][0]) {
/* Disable write access. */
state = 0;
}
} else {
if ('0' == argv[1][0]) {
/* Disable write access. */
- state = eeprom_write_enable(C
FG
_I2C_EEPROM_ADDR, 0);
+ state = eeprom_write_enable(C
ONFIG_SYS
_I2C_EEPROM_ADDR, 0);
} else {
/* Enable write access. */
} else {
/* Enable write access. */
- state = eeprom_write_enable(C
FG
_I2C_EEPROM_ADDR, 1);
+ state = eeprom_write_enable(C
ONFIG_SYS
_I2C_EEPROM_ADDR, 1);
}
if (state < 0)
puts ("Setup of write access state failed.\n");
}
if (state < 0)
puts ("Setup of write access state failed.\n");
@@
-865,19
+865,19
@@
int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
"eepwren - Enable / disable / query EEPROM write access\n",
NULL);
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
"eepwren - Enable / disable / query EEPROM write access\n",
NULL);
-#endif /* #if defined(C
FG
_EEPROM_WREN) */
+#endif /* #if defined(C
ONFIG_SYS
_EEPROM_WREN) */
static int got_pldirq;
static int pld_interrupt(u32 arg)
{
int rc = -1; /* not for us */
static int got_pldirq;
static int pld_interrupt(u32 arg)
{
int rc = -1; /* not for us */
- u8 status = in8(C
FG
_CPLD_BASE);
+ u8 status = in8(C
ONFIG_SYS
_CPLD_BASE);
/* check for PLD interrupt */
if (status & PWR_INT_FLAG) {
/* reset this int */
/* check for PLD interrupt */
if (status & PWR_INT_FLAG) {
/* reset this int */
- out8(C
FG
_CPLD_BASE, 0);
+ out8(C
ONFIG_SYS
_CPLD_BASE, 0);
rc = 0;
got_pldirq = 1; /* trigger backend */
}
rc = 0;
got_pldirq = 1; /* trigger backend */
}
@@
-890,7
+890,7
@@
int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
got_pldirq = 0;
/* clear any pending interrupt */
got_pldirq = 0;
/* clear any pending interrupt */
- out8(C
FG
_CPLD_BASE, 0);
+ out8(C
ONFIG_SYS
_CPLD_BASE, 0);
irq_install_handler(CPLD_IRQ,
(interrupt_handler_t *)pld_interrupt, 0);
irq_install_handler(CPLD_IRQ,
(interrupt_handler_t *)pld_interrupt, 0);
@@
-906,7
+906,7
@@
int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (got_pldirq) {
printf("Got interrupt!\n");
printf("Power %sready!\n",
if (got_pldirq) {
printf("Got interrupt!\n");
printf("Power %sready!\n",
- in8(C
FG
_CPLD_BASE) & PWR_RDY ? "":"NOT ");
+ in8(C
ONFIG_SYS
_CPLD_BASE) & PWR_RDY ? "":"NOT ");
}
irq_free_handler(CPLD_IRQ);
}
irq_free_handler(CPLD_IRQ);
@@
-970,7
+970,7
@@
U_BOOT_CMD(
int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
unsigned long long start, end;
int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
unsigned long long start, end;
- char c, cmd[C
FG
_CBSIZE];
+ char c, cmd[C
ONFIG_SYS
_CBSIZE];
char *p, *d = cmd;
int ret, i;
ulong us;
char *p, *d = cmd;
int ret, i;
ulong us;
@@
-998,7
+998,7
@@
int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return ret;
}
U_BOOT_CMD(
return ret;
}
U_BOOT_CMD(
- time, C
FG_MAXARGS,
1, do_time,
+ time, C
ONFIG_SYS_MAXARGS,
1, do_time,
"time - run command and output execution time\n",
NULL
);
"time - run command and output execution time\n",
NULL
);
@@
-1048,7
+1048,7
@@
int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 0;
}
U_BOOT_CMD(
return 0;
}
U_BOOT_CMD(
- gfxdemo, C
FG_MAXARGS,
1, do_gfxdemo,
+ gfxdemo, C
ONFIG_SYS_MAXARGS,
1, do_gfxdemo,
"gfxdemo - demo\n",
NULL
);
"gfxdemo - demo\n",
NULL
);