- mtebc( pb0ap, 0x03800000 ); /* set chip selects */
- mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
- mtebc( pb1ap, 0x03800000 );
- mtebc( pb1cr, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
- mtebc( pb2ap, 0x03800000 );
- mtebc( pb2cr, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
+ mtebc( PB0AP, 0x03800000 ); /* set chip selects */
+ mtebc( PB0CR, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
+ mtebc( PB1AP, 0x03800000 );
+ mtebc( PB1CR, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
+ mtebc( PB2AP, 0x03800000 );
+ mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */
mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */
mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */
mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */
mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic0sr, 0xffffffff );
mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic0sr, 0xffffffff );
* The luan board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
* The luan board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
* may not be sufficient for a given board.
*
************************************************************************/
* may not be sufficient for a given board.
*
************************************************************************/
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+ out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+ out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
************************************************************************/
static void l2cache_disable(void)
{
************************************************************************/
static void l2cache_disable(void)
{
************************************************************************/
static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
{
************************************************************************/
static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
{
- mtdcr( l2_cache_snp0, 0 ); /* snoop registers */
- mtdcr( l2_cache_snp1, 0 );
+ mtdcr( L2_CACHE_SNP0, 0 ); /* snoop registers */
+ mtdcr( L2_CACHE_SNP1, 0 );
************************************************************************/
static int l2cache_status(void)
{
************************************************************************/
static int l2cache_status(void)
{
U_BOOT_CMD(
l2cache, 2, 1, do_l2cache,
U_BOOT_CMD(
l2cache, 2, 1, do_l2cache,