+ /* if either one are a vector register... */
+ if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
+ opflags_t sok = BITS32 | BITS64;
+ int32_t o = input->offset;
+ int mod, scale, index, base;
+
+ /*
+ * For a vector SIB, one has to be a vector and the other,
+ * if present, a GPR. The vector must be the index operand.
+ */
+ if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
+ if (s == 0)
+ s = 1;
+ else if (s != 1)
+ goto err;
+
+ t = bt, bt = it, it = t;
+ x = bx, bx = ix, ix = x;
+ }
+
+ if (bt != -1) {
+ if (REG_GPR & ~bx)
+ goto err;
+ if (!(REG64 & ~bx) || !(REG32 & ~bx))
+ sok &= bx;
+ else
+ goto err;
+ }
+
+ /*
+ * While we're here, ensure the user didn't specify
+ * WORD or QWORD
+ */
+ if (input->disp_size == 16 || input->disp_size == 64)
+ goto err;
+
+ if (addrbits == 16 ||
+ (addrbits == 32 && !(sok & BITS32)) ||
+ (addrbits == 64 && !(sok & BITS64)))
+ goto err;
+
+ output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
+ : ((ix & YMMREG & ~REG_EA)
+ ? EA_YMMVSIB : EA_XMMVSIB));
+
+ output->rex |= rexflags(it, ix, REX_X);
+ output->rex |= rexflags(bt, bx, REX_B);
+ ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
+
+ index = it & 7; /* it is known to be != -1 */
+
+ switch (s) {
+ case 1:
+ scale = 0;
+ break;
+ case 2:
+ scale = 1;
+ break;
+ case 4:
+ scale = 2;
+ break;
+ case 8:
+ scale = 3;
+ break;
+ default: /* then what the smeg is it? */
+ goto err; /* panic */
+ }
+
+ if (bt == -1) {
+ base = 5;
+ mod = 0;
+ } else {
+ base = (bt & 7);
+ if (base != REG_NUM_EBP && o == 0 &&
+ seg == NO_SEG && !forw_ref &&
+ !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
+ mod = 0;
+ else if (IS_MOD_01())
+ mod = 1;
+ else
+ mod = 2;
+ }
+
+ output->sib_present = true;
+ output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
+ output->modrm = GEN_MODRM(mod, rfield, 4);
+ output->sib = GEN_SIB(scale, index, base);
+ } else if ((ix|bx) & (BITS32|BITS64)) {