+config SMP
+ bool "Symmetric Multi-Processing"
+ depends on SBI_V01 || !RISCV_SMODE
+ help
+ This enables support for systems with more than one CPU. If
+ you say N here, U-Boot will run on single and multiprocessor
+ machines, but will use only one CPU of a multiprocessor
+ machine. If you say Y here, U-Boot will run on many, but not
+ all, single processor machines.
+
+config SPL_SMP
+ bool "Symmetric Multi-Processing in SPL"
+ depends on SPL && SPL_RISCV_MMODE
+ default y
+ help
+ This enables support for systems with more than one CPU in SPL.
+ If you say N here, U-Boot SPL will run on single and multiprocessor
+ machines, but will use only one CPU of a multiprocessor
+ machine. If you say Y here, U-Boot SPL will run on many, but not
+ all, single processor machines.
+
+config NR_CPUS
+ int "Maximum number of CPUs (2-32)"
+ range 2 32
+ depends on SMP || SPL_SMP
+ default 8
+ help
+ On multiprocessor machines, U-Boot sets up a stack for each CPU.
+ Stack memory is pre-allocated. U-Boot must therefore know the
+ maximum number of CPUs that may be present.
+
+config SBI
+ bool
+ default y if RISCV_SMODE || SPL_RISCV_SMODE
+
+choice
+ prompt "SBI support"
+ default SBI_V02
+
+config SBI_V01
+ bool "SBI v0.1 support"
+ depends on SBI
+ help
+ This config allows kernel to use SBI v0.1 APIs. This will be
+ deprecated in future once legacy M-mode software are no longer in use.
+
+config SBI_V02
+ bool "SBI v0.2 support"
+ depends on SBI
+ help
+ This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
+ scalable and extendable to handle future needs for RISC-V supervisor
+ interfaces. For example, with SBI v0.2 HSM extension, only a single
+ hart need to boot and enter operating system. The booting hart can
+ bring up secondary harts one by one afterwards.
+
+ Choose this option if OpenSBI v0.7 or above release is used together
+ with U-Boot.
+
+endchoice
+
+config SBI_IPI
+ bool
+ depends on SBI
+ default y if RISCV_SMODE || SPL_RISCV_SMODE
+ depends on SMP
+
+config XIP
+ bool "XIP mode"
+ help
+ XIP (eXecute In Place) is a method for executing code directly
+ from a NOR flash memory without copying the code to ram.
+ Say yes here if U-Boot boots from flash directly.
+
+config SHOW_REGS
+ bool "Show registers on unhandled exception"
+
+config RISCV_PRIV_1_9
+ bool "Use version 1.9 of the RISC-V priviledged specification"
+ help
+ Older versions of the RISC-V priviledged specification had
+ separate counter enable CSRs for each privilege mode. Writing
+ to the unified mcounteren CSR on a processor implementing the
+ old specification will result in an illegal instruction
+ exception. In addition to counter CSR changes, the way virtual
+ memory is configured was also changed.
+
+config STACK_SIZE_SHIFT
+ int
+ default 14
+