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powerpc: MPC8641: Remove macro CONFIG_MPC8641
[platform/kernel/u-boot.git]
/
arch
/
powerpc
/
include
/
asm
/
fsl_law.h
diff --git
a/arch/powerpc/include/asm/fsl_law.h
b/arch/powerpc/include/asm/fsl_law.h
index
13caffd
..
b348cc1
100644
(file)
--- a/
arch/powerpc/include/asm/fsl_law.h
+++ b/
arch/powerpc/include/asm/fsl_law.h
@@
-1,15
+1,14
@@
/*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
*
/*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _FSL_LAW_H_
#define _FSL_LAW_H_
#include <asm/io.h>
*/
#ifndef _FSL_LAW_H_
#define _FSL_LAW_H_
#include <asm/io.h>
+#include <linux/log2.h>
#define LAW_EN 0x80000000
#define LAW_EN 0x80000000
@@
-60,32
+59,56
@@
enum law_trgt_if {
LAW_TRGT_IF_DDR_1 = 0x10,
LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */
LAW_TRGT_IF_DDR_1 = 0x10,
LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */
+ LAW_TRGT_IF_DDR_3 = 0x12,
+ LAW_TRGT_IF_DDR_4 = 0x13,
LAW_TRGT_IF_DDR_INTRLV = 0x14,
LAW_TRGT_IF_DDR_INTRLV = 0x14,
-
+ LAW_TRGT_IF_DDR_INTLV_34 = 0x15,
+ LAW_TRGT_IF_DDR_INTLV_123 = 0x17,
+ LAW_TRGT_IF_DDR_INTLV_1234 = 0x16,
LAW_TRGT_IF_BMAN = 0x18,
LAW_TRGT_IF_DCSR = 0x1d,
LAW_TRGT_IF_BMAN = 0x18,
LAW_TRGT_IF_DCSR = 0x1d,
+ LAW_TRGT_IF_CCSR = 0x1e,
LAW_TRGT_IF_LBC = 0x1f,
LAW_TRGT_IF_QMAN = 0x3c,
LAW_TRGT_IF_LBC = 0x1f,
LAW_TRGT_IF_QMAN = 0x3c,
+
+ LAW_TRGT_IF_MAPLE = 0x50,
};
#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1
};
#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1
+#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
#else
enum law_trgt_if {
LAW_TRGT_IF_PCI = 0x00,
LAW_TRGT_IF_PCI_2 = 0x01,
#else
enum law_trgt_if {
LAW_TRGT_IF_PCI = 0x00,
LAW_TRGT_IF_PCI_2 = 0x01,
-#ifndef CONFIG_MPC8641
+#ifndef CONFIG_
ARCH_
MPC8641
LAW_TRGT_IF_PCIE_1 = 0x02,
#endif
LAW_TRGT_IF_PCIE_1 = 0x02,
#endif
-#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
+#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
+ LAW_TRGT_IF_OCN_DSP = 0x03,
+#else
+#if !defined(CONFIG_ARCH_MPC8572) && !defined(CONFIG_ARCH_P2020)
LAW_TRGT_IF_PCIE_3 = 0x03,
#endif
LAW_TRGT_IF_PCIE_3 = 0x03,
#endif
+#endif
LAW_TRGT_IF_LBC = 0x04,
LAW_TRGT_IF_CCSR = 0x08,
LAW_TRGT_IF_LBC = 0x04,
LAW_TRGT_IF_CCSR = 0x08,
+ LAW_TRGT_IF_DSP_CCSR = 0x09,
+ LAW_TRGT_IF_PLATFORM_SRAM = 0x0a,
LAW_TRGT_IF_DDR_INTRLV = 0x0b,
LAW_TRGT_IF_RIO = 0x0c,
LAW_TRGT_IF_DDR_INTRLV = 0x0b,
LAW_TRGT_IF_RIO = 0x0c,
+#if defined(CONFIG_ARCH_BSC9132)
+ LAW_TRGT_IF_CLASS_DSP = 0x0d,
+#else
LAW_TRGT_IF_RIO_2 = 0x0d,
LAW_TRGT_IF_RIO_2 = 0x0d,
+#endif
LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e,
LAW_TRGT_IF_DDR = 0x0f,
LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e,
LAW_TRGT_IF_DDR = 0x0f,
LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
+ /* place holder for 3-way and 4-way interleaving */
+ LAW_TRGT_IF_DDR_3,
+ LAW_TRGT_IF_DDR_4,
+ LAW_TRGT_IF_DDR_INTLV_34,
+ LAW_TRGT_IF_DDR_INTLV_123,
+ LAW_TRGT_IF_DDR_INTLV_1234,
};
#define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR
#define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI
};
#define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR
#define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI
@@
-94,11
+117,11
@@
enum law_trgt_if {
#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
-#ifdef CONFIG_MPC8641
+#ifdef CONFIG_
ARCH_
MPC8641
#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
#endif
#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
#endif
-#if defined(CONFIG_
MPC8572) || defined(CONFIG
_P2020)
+#if defined(CONFIG_
ARCH_MPC8572) || defined(CONFIG_ARCH
_P2020)
#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
#endif
#endif /* CONFIG_FSL_CORENET */
#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
#endif
#endif /* CONFIG_FSL_CORENET */