-
-#if defined(CONFIG_NAND_SPL)
-/*
- * void nand_boot_relocate(dst, src, bytes)
- *
- * r3 = Destination address to copy code to (in SDRAM)
- * r4 = Source address to copy code from
- * r5 = size to copy in bytes
- */
-nand_boot_relocate:
- mr r6,r3
- mr r7,r4
- mflr r8
-
- /*
- * Copy SPL from icache into SDRAM
- */
- subi r3,r3,4
- subi r4,r4,4
- srwi r5,r5,2
- mtctr r5
-..spl_loop:
- lwzu r0,4(r4)
- stwu r0,4(r3)
- bdnz ..spl_loop
-
- /*
- * Calculate "corrected" link register, so that we "continue"
- * in execution in destination range
- */
- sub r3,r7,r6 /* r3 = src - dst */
- sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
- mtlr r8
- blr
-
-nand_boot_common:
- /*
- * First initialize SDRAM. It has to be available *before* calling
- * nand_boot().
- */
- lis r3,CONFIG_SYS_SDRAM_BASE@h
- ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
- bl initdram
-
- /*
- * Now copy the 4k SPL code into SDRAM and continue execution
- * from there.
- */
- lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
- ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
- lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
- ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
- lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
- ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
- bl nand_boot_relocate
-
- /*
- * We're running from SDRAM now!!!
- *
- * It is necessary for 4xx systems to relocate from running at
- * the original location (0xfffffxxx) to somewhere else (SDRAM
- * preferably). This is because CS0 needs to be reconfigured for
- * NAND access. And we can't reconfigure this CS when currently
- * "running" from it.
- */
-
- /*
- * Finally call nand_boot() to load main NAND U-Boot image from
- * NAND and jump to it.
- */
- bl nand_boot /* will not return */
-#endif /* CONFIG_NAND_SPL */