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Coding Style cleanup: remove trailing white space
[platform/kernel/u-boot.git]
/
arch
/
powerpc
/
cpu
/
mpc85xx
/
start.S
diff --git
a/arch/powerpc/cpu/mpc85xx/start.S
b/arch/powerpc/cpu/mpc85xx/start.S
index
cfc3a60
..
d329aa8
100644
(file)
--- a/
arch/powerpc/cpu/mpc85xx/start.S
+++ b/
arch/powerpc/cpu/mpc85xx/start.S
@@
-2,7
+2,7
@@
* Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
* Copyright (C) 2003 Motorola,Inc.
*
* Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
* Copyright (C) 2003 Motorola,Inc.
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
*/
/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
*/
/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
@@
-33,7
+33,8
@@
#define MINIMAL_SPL
#endif
#define MINIMAL_SPL
#endif
-#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
+ !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define NOR_BOOT
#endif
#define NOR_BOOT
#endif
@@
-107,6
+108,14
@@
_start_e500:
isync
2:
#endif
isync
2:
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
+ msync
+ isync
+ mfspr r3, SPRN_HDBCR0
+ oris r3, r3, 0x0080
+ mtspr SPRN_HDBCR0, r3
+#endif
+
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
/* ISBC uses L2 as stack.
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
/* ISBC uses L2 as stack.