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powerpc: P4080: Remove macro CONFIG_PPC_P4080
[platform/kernel/u-boot.git]
/
arch
/
powerpc
/
cpu
/
mpc85xx
/
fsl_corenet_serdes.c
diff --git
a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index
680b522
..
20d039f
100644
(file)
--- a/
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@
-13,7
+13,7
@@
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/fsl_law.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/fsl_law.h>
-#include <
asm
/errno.h>
+#include <
linux
/errno.h>
#include "fsl_corenet_serdes.h"
/*
#include "fsl_corenet_serdes.h"
/*
@@
-76,7
+76,7
@@
static const struct {
{ 17, 163, FSL_SRDS_BANK_2 },
{ 18, 164, FSL_SRDS_BANK_2 },
{ 19, 165, FSL_SRDS_BANK_2 },
{ 17, 163, FSL_SRDS_BANK_2 },
{ 18, 164, FSL_SRDS_BANK_2 },
{ 19, 165, FSL_SRDS_BANK_2 },
-#ifdef CONFIG_
PPC
_P4080
+#ifdef CONFIG_
ARCH
_P4080
{ 20, 170, FSL_SRDS_BANK_3 },
{ 21, 171, FSL_SRDS_BANK_3 },
{ 22, 172, FSL_SRDS_BANK_3 },
{ 20, 170, FSL_SRDS_BANK_3 },
{ 21, 171, FSL_SRDS_BANK_3 },
{ 22, 172, FSL_SRDS_BANK_3 },
@@
-136,6
+136,9
@@
int is_serdes_configured(enum srds_prtcl device)
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
return 0;
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
return 0;
+ if (!(serdes_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes_prtcl_map;
}
return (1 << device) & serdes_prtcl_map;
}
@@
-514,6
+517,8
@@
void fsl_serdes_init(void)
if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
buf = buffer;
#endif
if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
buf = buffer;
#endif
+ if (serdes_prtcl_map & (1 << NONE))
+ return;
/* Is serdes enabled at all? */
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
/* Is serdes enabled at all? */
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
@@
-857,4
+862,24
@@
void fsl_serdes_init(void)
SRDS_RSTCTL_SDPD);
}
#endif
SRDS_RSTCTL_SDPD);
}
#endif
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes_prtcl_map |= (1 << NONE);
}
}
+
+const char *serdes_clock_to_string(u32 clock)
+{
+ switch (clock) {
+ case SRDS_PLLCR0_RFCK_SEL_100:
+ return "100";
+ case SRDS_PLLCR0_RFCK_SEL_125:
+ return "125";
+ case SRDS_PLLCR0_RFCK_SEL_156_25:
+ return "156.25";
+ case SRDS_PLLCR0_RFCK_SEL_161_13:
+ return "161.1328123";
+ default:
+ return "150";
+ }
+}
+