+config SYS_CCSRBAR_DEFAULT
+ hex "Default CCSRBAR address"
+ default 0xff700000 if ARCH_BSC9131 || \
+ ARCH_BSC9132 || \
+ ARCH_C29X || \
+ ARCH_MPC8536 || \
+ ARCH_MPC8540 || \
+ ARCH_MPC8541 || \
+ ARCH_MPC8544 || \
+ ARCH_MPC8548 || \
+ ARCH_MPC8555 || \
+ ARCH_MPC8560 || \
+ ARCH_MPC8568 || \
+ ARCH_MPC8569 || \
+ ARCH_MPC8572 || \
+ ARCH_P1010 || \
+ ARCH_P1011 || \
+ ARCH_P1020 || \
+ ARCH_P1021 || \
+ ARCH_P1022 || \
+ ARCH_P1024 || \
+ ARCH_P1025 || \
+ ARCH_P2020
+ default 0xff600000 if ARCH_P1023
+ default 0xfe000000 if ARCH_B4420 || \
+ ARCH_B4860 || \
+ ARCH_P2041 || \
+ ARCH_P3041 || \
+ ARCH_P4080 || \
+ ARCH_P5020 || \
+ ARCH_P5040 || \
+ ARCH_T1023 || \
+ ARCH_T1024 || \
+ ARCH_T1040 || \
+ ARCH_T1042 || \
+ ARCH_T2080 || \
+ ARCH_T2081 || \
+ ARCH_T4160 || \
+ ARCH_T4240
+ default 0xe0000000 if ARCH_QEMU_E500
+ help
+ Default value of CCSRBAR comes from power-on-reset. It
+ is fixed on each SoC. Some SoCs can have different value
+ if changed by pre-boot regime. The value here must match
+ the current value in SoC. If not sure, do not change.
+
+config SYS_FSL_ERRATUM_A004468
+ bool
+
+config SYS_FSL_ERRATUM_A004477
+ bool
+
+config SYS_FSL_ERRATUM_A004508
+ bool
+
+config SYS_FSL_ERRATUM_A004580
+ bool
+
+config SYS_FSL_ERRATUM_A004699
+ bool
+
+config SYS_FSL_ERRATUM_A004849
+ bool
+
+config SYS_FSL_ERRATUM_A004510
+ bool
+
+config SYS_FSL_ERRATUM_A004510_SVR_REV
+ hex
+ depends on SYS_FSL_ERRATUM_A004510
+ default 0x20 if ARCH_P4080
+ default 0x10
+
+config SYS_FSL_ERRATUM_A004510_SVR_REV2
+ hex
+ depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
+ default 0x11
+
+config SYS_FSL_ERRATUM_A005125
+ bool
+
+config SYS_FSL_ERRATUM_A005434
+ bool
+
+config SYS_FSL_ERRATUM_A005812
+ bool
+
+config SYS_FSL_ERRATUM_A005871
+ bool
+
+config SYS_FSL_ERRATUM_A006261
+ bool
+
+config SYS_FSL_ERRATUM_A006379
+ bool
+
+config SYS_FSL_ERRATUM_A006384
+ bool
+
+config SYS_FSL_ERRATUM_A006475
+ bool
+
+config SYS_FSL_ERRATUM_A006593
+ bool
+
+config SYS_FSL_ERRATUM_A007075
+ bool
+
+config SYS_FSL_ERRATUM_A007186
+ bool
+
+config SYS_FSL_ERRATUM_A007212
+ bool
+
+config SYS_FSL_ERRATUM_A007798
+ bool
+
+config SYS_FSL_ERRATUM_A007907
+ bool
+
+config SYS_FSL_ERRATUM_A008044
+ bool
+
+config SYS_FSL_ERRATUM_CPC_A002
+ bool
+
+config SYS_FSL_ERRATUM_CPC_A003
+ bool
+
+config SYS_FSL_ERRATUM_CPU_A003999
+ bool
+
+config SYS_FSL_ERRATUM_ELBC_A001
+ bool
+
+config SYS_FSL_ERRATUM_I2C_A004447
+ bool
+
+config SYS_FSL_A004447_SVR_REV
+ hex
+ depends on SYS_FSL_ERRATUM_I2C_A004447
+ default 0x00 if ARCH_MPC8548
+ default 0x10 if ARCH_P1010
+ default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
+ default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
+
+config SYS_FSL_ERRATUM_IFC_A002769
+ bool
+
+config SYS_FSL_ERRATUM_IFC_A003399
+ bool
+
+config SYS_FSL_ERRATUM_NMG_CPU_A011
+ bool
+
+config SYS_FSL_ERRATUM_NMG_ETSEC129
+ bool
+
+config SYS_FSL_ERRATUM_NMG_LBC103
+ bool
+
+config SYS_FSL_ERRATUM_P1010_A003549
+ bool
+
+config SYS_FSL_ERRATUM_SATA_A001
+ bool
+
+config SYS_FSL_ERRATUM_SEC_A003571
+ bool
+
+config SYS_FSL_ERRATUM_SRIO_A004034
+ bool
+
+config SYS_FSL_ERRATUM_USB14
+ bool
+
+config SYS_P4080_ERRATUM_CPU22
+ bool
+
+config SYS_P4080_ERRATUM_PCIE_A003
+ bool
+
+config SYS_P4080_ERRATUM_SERDES8
+ bool
+
+config SYS_P4080_ERRATUM_SERDES9
+ bool
+
+config SYS_P4080_ERRATUM_SERDES_A001
+ bool
+
+config SYS_P4080_ERRATUM_SERDES_A005
+ bool
+
+config SYS_FSL_QORIQ_CHASSIS1
+ bool
+
+config SYS_FSL_QORIQ_CHASSIS2
+ bool
+
+config SYS_FSL_NUM_LAWS
+ int "Number of local access windows"
+ depends on FSL_LAW
+ default 32 if ARCH_B4420 || \
+ ARCH_B4860 || \
+ ARCH_P2041 || \
+ ARCH_P3041 || \
+ ARCH_P4080 || \
+ ARCH_P5020 || \
+ ARCH_P5040 || \
+ ARCH_T2080 || \
+ ARCH_T2081 || \
+ ARCH_T4160 || \
+ ARCH_T4240
+ default 16 if ARCH_T1023 || \
+ ARCH_T1024 || \
+ ARCH_T1040 || \
+ ARCH_T1042
+ default 12 if ARCH_BSC9131 || \
+ ARCH_BSC9132 || \
+ ARCH_C29X || \
+ ARCH_MPC8536 || \
+ ARCH_MPC8572 || \
+ ARCH_P1010 || \
+ ARCH_P1011 || \
+ ARCH_P1020 || \
+ ARCH_P1021 || \
+ ARCH_P1022 || \
+ ARCH_P1023 || \
+ ARCH_P1024 || \
+ ARCH_P1025 || \
+ ARCH_P2020
+ default 10 if ARCH_MPC8544 || \
+ ARCH_MPC8548 || \
+ ARCH_MPC8568 || \
+ ARCH_MPC8569
+ default 8 if ARCH_MPC8540 || \
+ ARCH_MPC8541 || \
+ ARCH_MPC8555 || \
+ ARCH_MPC8560
+ help
+ Number of local access windows. This is fixed per SoC.
+ If not sure, do not change.
+
+config SYS_FSL_THREADS_PER_CORE
+ int
+ default 2 if E6500
+ default 1
+
+config SYS_NUM_TLBCAMS
+ int "Number of TLB CAM entries"
+ default 64 if E500MC
+ default 16
+ help
+ Number of TLB CAM entries for Book-E chips. 64 for E500MC,
+ 16 for other E500 SoCs.
+
+config SYS_PPC64
+ bool
+
+config SYS_PPC_E500_USE_DEBUG_TLB
+ bool
+
+config SYS_PPC_E500_DEBUG_TLB
+ int "Temporary TLB entry for external debugger"
+ depends on SYS_PPC_E500_USE_DEBUG_TLB
+ default 0 if ARCH_MPC8544 || ARCH_MPC8548
+ default 1 if ARCH_MPC8536
+ default 2 if ARCH_MPC8572 || \
+ ARCH_P1011 || \
+ ARCH_P1020 || \
+ ARCH_P1021 || \
+ ARCH_P1022 || \
+ ARCH_P1024 || \
+ ARCH_P1025 || \
+ ARCH_P2020
+ default 3 if ARCH_P1010 || \
+ ARCH_BSC9132 || \
+ ARCH_C29X
+ help
+ Select a temporary TLB entry to be used during boot to work
+ around limitations in e500v1 and e500v2 external debugger
+ support. This reduces the portions of the boot code where
+ breakpoints and single stepping do not work. The value of this
+ symbol should be set to the TLB1 entry to be used for this
+ purpose. If unsure, do not change.
+
projects / platform / kernel / u-boot.git / blobdiff