+config ENABLE_36BIT_PHYS
+ bool "Enable 36bit physical address space support"
+
+config SYS_BOOK3E_HV
+ bool "Category E.HV is supported"
+ depends on BOOKE
+
+config FSL_CORENET
+ bool
+ select SYS_FSL_CPC
+
+config FSL_NGPIXIS
+ bool
+
+config SYS_CPC_REINIT_F
+ bool
+ help
+ The CPC is configured as SRAM at the time of U-Boot entry and is
+ required to be re-initialized.
+
+config SYS_FSL_CPC
+ bool
+
+config SYS_CACHE_STASHING
+ bool "Enable cache stashing"
+
+config SYS_FSL_PCIE_COMPAT_P4080_PCIE
+ bool
+
+config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
+ bool
+
+config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
+ bool
+
+config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
+ bool
+
+config SYS_FSL_PCIE_COMPAT
+ string
+ depends on FSL_CORENET
+ default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE
+ default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
+ default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
+ default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
+ help
+ Defines the string to utilize when trying to match PCIe device tree
+ nodes for the given platform.
+
+config SYS_FSL_SINGLE_SOURCE_CLK
+ bool
+
+config SYS_FSL_SRIO_LIODN
+ bool
+
+config SYS_FSL_TBCLK_DIV
+ int
+ default 32 if ARCH_P2041 || ARCH_P3041
+ default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \
+ ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \
+ ARCH_T1024 || ARCH_T2080
+ default 8
+ help
+ Defines the core time base clock divider ratio compared to the system
+ clock. On most PQ3 devices this is 8, on newer QorIQ devices it can
+ be 16 or 32. The ratio varies from SoC to Soc.
+
+config SYS_FSL_USB1_PHY_ENABLE
+ bool
+
+config SYS_FSL_USB2_PHY_ENABLE
+ bool
+
+config SYS_FSL_USB_DUAL_PHY_ENABLE
+ bool
+
+config SYS_MPC85XX_NO_RESETVEC
+ bool "Discard resetvec section and move bootpg section up"
+ depends on MPC85xx
+ help
+ If this variable is specified, the section .resetvec is not kept and
+ the section .bootpg is placed in the previous 4k of the .text section.
+
+config SPL_SYS_MPC85XX_NO_RESETVEC
+ bool "Discard resetvec section and move bootpg section up, in SPL"
+ depends on MPC85xx && SPL
+ help
+ If this variable is specified, the section .resetvec is not kept and
+ the section .bootpg is placed in the previous 4k of the .text section,
+ of the SPL portion of the binary.
+
+config TPL_SYS_MPC85XX_NO_RESETVEC
+ bool "Discard resetvec section and move bootpg section up, in TPL"
+ depends on MPC85xx && TPL
+ help
+ If this variable is specified, the section .resetvec is not kept and
+ the section .bootpg is placed in the previous 4k of the .text section,
+ of the SPL portion of the binary.
+