+ /* Call board_init_f_alloc_reserve with the current stack pointer as
+ * parameter. */
+ add r5, r0, r1
+ bralid r15, board_init_f_alloc_reserve
+ nop
+
+ /* board_init_f_alloc_reserve returns a pointer to the allocated area
+ * in r3. Set the new stack pointer below this area. */
+ add r1, r0, r3
+ mts rshr, r1
+ addi r1, r1, -4
+
+ /* Call board_init_f_init_reserve with the address returned by
+ * board_init_f_alloc_reserve as parameter. */
+ add r5, r0, r3
+ bralid r15, board_init_f_init_reserve
+ nop
+
+#if !defined(CONFIG_SPL_BUILD)
+ /* Setup vectors with pre-relocation symbols */
+ or r5, r0, r0
+ bralid r15, __setup_exceptions
+ nop
+#endif
+
+ /* Flush cache before enable cache */
+ addik r5, r0, 0
+ addik r6, r0, XILINX_DCACHE_BYTE_SIZE
+ bralid r15, flush_cache
+ nop
+
+ /* enable instruction and data cache */
+ mfs r12, rmsr
+ ori r12, r12, 0x1a0
+ mts rmsr, r12
+
+clear_bss:
+ /* clear BSS segments */
+ addi r5, r0, __bss_start
+ addi r4, r0, __bss_end
+ cmp r6, r5, r4
+ beqi r6, 3f
+2:
+ swi r0, r5, 0 /* write zero to loc */
+ addi r5, r5, 4 /* increment to next loc */
+ cmp r6, r5, r4 /* check if we have reach the end */
+ bnei r6, 2b
+3: /* jumping to board_init */
+#ifdef CONFIG_DEBUG_UART
+ bralid r15, debug_uart_init
+ nop
+#endif
+#ifndef CONFIG_SPL_BUILD
+ or r5, r0, r0 /* flags - empty */
+ brai board_init_f
+#else
+ brai board_init_r
+#endif
+1: bri 1b
+
+#ifndef CONFIG_SPL_BUILD
+ .text
+ .ent __setup_exceptions
+ .align 2
+/*
+ * Set up reset, interrupt, user exception and hardware exception vectors.
+ *
+ * Parameters:
+ * r5 - relocation offset (zero when setting up vectors before
+ * relocation, and gd->reloc_off when setting up vectors after
+ * relocation)
+ * - the relocation offset is added to the _exception_handler,
+ * _interrupt_handler and _hw_exception_handler symbols to reflect the
+ * post-relocation memory addresses
+ *
+ * Reserve registers:
+ * r10: Stores little/big endian offset for vectors
+ * r2: Stores imm opcode
+ * r3: Stores brai opcode
+ * r4: Stores the vector base address
+ */
+__setup_exceptions:
+ addik r1, r1, -32
+ swi r2, r1, 4
+ swi r3, r1, 8
+ swi r4, r1, 12
+ swi r6, r1, 16
+ swi r7, r1, 20
+ swi r8, r1, 24
+ swi r10, r1, 28
+