- /* read slave CPU number into r0 firstly */
- mrc p15, 0, r0, c0, c0, 5
- and r0, r0, #0x0f
+ /* enable GIC as cores will be waken up by IPI */
+ ldr r2, =GIC_CPU_BASE
+ mov r1, #0xf0
+ str r1, [r2, #4]
+ mov r1, #1
+ str r1, [r2, #0]
+
+ ldr r1, [r2]
+ orr r1, #1
+ str r1, [r2]
+
+ /* copy wait code into SRAM */
+ ldr r0, =slave_cpu_wait
+ ldm r0, {r1 - r8} @ slave_cpu_wait has eight insns
+ ldr r0, =WAIT_CODE_SRAM_BASE
+ stm r0, {r1 - r8}
+
+ /* pass args to slave_cpu_wait */
+ ldr r0, =SLAVE1_MAGIC_REG
+ ldr r1, =SLAVE1_MAGIC_NUM
+
+ /* jump to wait code in SRAM */
+ ldr pc, =WAIT_CODE_SRAM_BASE