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Merge git://git.denx.de/u-boot-socfpga
[platform/kernel/u-boot.git]
/
arch
/
arm
/
include
/
asm
/
arch-stm32f7
/
stm32.h
diff --git
a/arch/arm/include/asm/arch-stm32f7/stm32.h
b/arch/arm/include/asm/arch-stm32f7/stm32.h
index
de55ae5
..
87aee60
100644
(file)
--- a/
arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/
arch/arm/include/asm/arch-stm32f7/stm32.h
@@
-32,6
+32,7
@@
#define USART1_BASE (APB2_PERIPH_BASE + 0x1000)
#define USART6_BASE (APB2_PERIPH_BASE + 0x1400)
#define USART1_BASE (APB2_PERIPH_BASE + 0x1000)
#define USART6_BASE (APB2_PERIPH_BASE + 0x1400)
+#define STM32_SYSCFG_BASE (APB2_PERIPH_BASE + 0x3800)
#define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000)
#define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400)
#define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000)
#define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400)
@@
-48,7
+49,7
@@
#define FLASH_CNTL_BASE (AHB1_PERIPH_BASE + 0x3C00)
#define FLASH_CNTL_BASE (AHB1_PERIPH_BASE + 0x3C00)
-#define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x4
A
0000140)
+#define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x40000140)
static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
[0 ... 3] = 32 * 1024,
static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
[0 ... 3] = 32 * 1024,
@@
-56,13
+57,7
@@
static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
[5 ... 7] = 256 * 1024
};
[5 ... 7] = 256 * 1024
};
-enum clock {
- CLOCK_CORE,
- CLOCK_AHB,
- CLOCK_APB1,
- CLOCK_APB2
-};
-#define STM32_BUS_MASK 0xFFFF0000
+#define STM32_BUS_MASK GENMASK(31, 16)
struct stm32_rcc_regs {
u32 cr; /* RCC clock control */
struct stm32_rcc_regs {
u32 cr; /* RCC clock control */
@@
-95,8
+90,8
@@
struct stm32_rcc_regs {
u32 rsv6[2];
u32 sscgr; /* RCC spread spectrum clock generation */
u32 plli2scfgr; /* RCC PLLI2S configuration */
u32 rsv6[2];
u32 sscgr; /* RCC spread spectrum clock generation */
u32 plli2scfgr; /* RCC PLLI2S configuration */
- u32 pllsaicfgr;
- u32 dckcfgr;
+ u32 pllsaicfgr;
/* PLLSAI configuration */
+ u32 dckcfgr;
/* dedicated clocks configuration register */
};
#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
};
#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
@@
-108,8
+103,6
@@
struct stm32_pwr_regs {
};
#define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE)
};
#define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE)
-int configure_clocks(void);
-unsigned long clock_get(enum clock clck);
void stm32_flash_latency_cfg(int latency);
#endif /* _ASM_ARCH_HARDWARE_H */
void stm32_flash_latency_cfg(int latency);
#endif /* _ASM_ARCH_HARDWARE_H */