Merge branch 'master' of git://git.denx.de/u-boot-sunxi

[platform/kernel/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a77a68d..f48481f 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -1,54 +1,131 @@
 config ARCH_LS1012A
        bool
        select ARMV8_SET_SMPEN
 config ARCH_LS1012A
        bool
        select ARMV8_SET_SMPEN

+       select ARM_ERRATA_855873 if !TFABOOT
+       select FSL_LAYERSCAPE

        select FSL_LSCH2
        select FSL_LSCH2

+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES

        select SYS_FSL_DDR_BE
        select SYS_FSL_MMDC
        select SYS_FSL_ERRATUM_A010315
        select SYS_FSL_DDR_BE
        select SYS_FSL_MMDC
        select SYS_FSL_ERRATUM_A010315

+       select SYS_FSL_ERRATUM_A009798
+       select SYS_FSL_ERRATUM_A008997
+       select SYS_FSL_ERRATUM_A009007
+       select SYS_FSL_ERRATUM_A009008

        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F

+       select SYS_I2C_MXC
+       select SYS_I2C_MXC_I2C1
+       select SYS_I2C_MXC_I2C2
+       imply PANIC_HANG

 
 config ARCH_LS1043A
        bool
        select ARMV8_SET_SMPEN
 
 config ARCH_LS1043A
        bool
        select ARMV8_SET_SMPEN

+       select ARM_ERRATA_855873 if !TFABOOT
+       select FSL_LAYERSCAPE

        select FSL_LSCH2
        select FSL_LSCH2

+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES

        select SYS_FSL_DDR
        select SYS_FSL_DDR_BE
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_DDR
        select SYS_FSL_DDR_BE
        select SYS_FSL_DDR_VER_50

-       select SYS_FSL_ERRATUM_A008850
-       select SYS_FSL_ERRATUM_A009660
-       select SYS_FSL_ERRATUM_A009663
+       select SYS_FSL_ERRATUM_A008850 if !TFABOOT
+       select SYS_FSL_ERRATUM_A008997
+       select SYS_FSL_ERRATUM_A009007
+       select SYS_FSL_ERRATUM_A009008
+       select SYS_FSL_ERRATUM_A009660 if !TFABOOT
+       select SYS_FSL_ERRATUM_A009663 if !TFABOOT
+       select SYS_FSL_ERRATUM_A009798

        select SYS_FSL_ERRATUM_A009929
        select SYS_FSL_ERRATUM_A009929

-       select SYS_FSL_ERRATUM_A009942
+       select SYS_FSL_ERRATUM_A009942 if !TFABOOT

        select SYS_FSL_ERRATUM_A010315
        select SYS_FSL_ERRATUM_A010539
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_DDR4
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_FSL_ERRATUM_A010315
        select SYS_FSL_ERRATUM_A010539
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_DDR4
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F

-       imply SCSI
+       select SYS_I2C_MXC
+       select SYS_I2C_MXC_I2C1
+       select SYS_I2C_MXC_I2C2
+       select SYS_I2C_MXC_I2C3
+       select SYS_I2C_MXC_I2C4

        imply CMD_PCI
 
 config ARCH_LS1046A
        bool
        select ARMV8_SET_SMPEN
        imply CMD_PCI
 
 config ARCH_LS1046A
        bool
        select ARMV8_SET_SMPEN

+       select FSL_LAYERSCAPE

        select FSL_LSCH2
        select FSL_LSCH2

+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES

        select SYS_FSL_DDR
        select SYS_FSL_DDR_BE
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_DDR
        select SYS_FSL_DDR_BE
        select SYS_FSL_DDR_VER_50

-       select SYS_FSL_ERRATUM_A008336
-       select SYS_FSL_ERRATUM_A008511
-       select SYS_FSL_ERRATUM_A008850
+       select SYS_FSL_ERRATUM_A008336 if !TFABOOT
+       select SYS_FSL_ERRATUM_A008511 if !TFABOOT
+       select SYS_FSL_ERRATUM_A008850 if !TFABOOT
+       select SYS_FSL_ERRATUM_A008997
+       select SYS_FSL_ERRATUM_A009007
+       select SYS_FSL_ERRATUM_A009008
+       select SYS_FSL_ERRATUM_A009798

        select SYS_FSL_ERRATUM_A009801
        select SYS_FSL_ERRATUM_A009801

-       select SYS_FSL_ERRATUM_A009803
-       select SYS_FSL_ERRATUM_A009942
-       select SYS_FSL_ERRATUM_A010165
+       select SYS_FSL_ERRATUM_A009803 if !TFABOOT
+       select SYS_FSL_ERRATUM_A009942 if !TFABOOT
+       select SYS_FSL_ERRATUM_A010165 if !TFABOOT

        select SYS_FSL_ERRATUM_A010539
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_SRDS_2
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_FSL_ERRATUM_A010539
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_SRDS_2
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F

+       select SYS_I2C_MXC
+       select SYS_I2C_MXC_I2C1
+       select SYS_I2C_MXC_I2C2
+       select SYS_I2C_MXC_I2C3
+       select SYS_I2C_MXC_I2C4
+       imply SCSI
+       imply SCSI_AHCI
+
+config ARCH_LS1088A
+       bool
+       select ARMV8_SET_SMPEN
+       select ARM_ERRATA_855873 if !TFABOOT
+       select FSL_LAYERSCAPE
+       select FSL_LSCH3
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
+       select SYS_FSL_DDR
+       select SYS_FSL_DDR_LE
+       select SYS_FSL_DDR_VER_50
+       select SYS_FSL_EC1
+       select SYS_FSL_EC2
+       select SYS_FSL_ERRATUM_A009803 if !TFABOOT
+       select SYS_FSL_ERRATUM_A009942 if !TFABOOT
+       select SYS_FSL_ERRATUM_A010165 if !TFABOOT
+       select SYS_FSL_ERRATUM_A008511 if !TFABOOT
+       select SYS_FSL_ERRATUM_A008850 if !TFABOOT
+       select SYS_FSL_ERRATUM_A009007
+       select SYS_FSL_HAS_CCI400
+       select SYS_FSL_HAS_DDR4
+       select SYS_FSL_HAS_RGMII
+       select SYS_FSL_HAS_SEC
+       select SYS_FSL_SEC_COMPAT_5
+       select SYS_FSL_SEC_LE
+       select SYS_FSL_SRDS_1
+       select SYS_FSL_SRDS_2
+       select FSL_TZASC_1
+       select FSL_TZASC_400
+       select FSL_TZPC_BP147
+       select ARCH_EARLY_INIT_R
+       select BOARD_EARLY_INIT_F
+       select SYS_I2C_MXC
+       select SYS_I2C_MXC_I2C1
+       select SYS_I2C_MXC_I2C2
+       select SYS_I2C_MXC_I2C3
+       select SYS_I2C_MXC_I2C4

        imply SCSI
        imply SCSI

+       imply PANIC_HANG

 
 config ARCH_LS2080A
        bool
 
 config ARCH_LS2080A
        bool


@@ -57,10 +134,14 @@ config ARCH_LS2080A
        select ARM_ERRATA_828024
        select ARM_ERRATA_829520
        select ARM_ERRATA_833471
        select ARM_ERRATA_828024
        select ARM_ERRATA_829520
        select ARM_ERRATA_833471

+       select FSL_LAYERSCAPE

        select FSL_LSCH3
        select FSL_LSCH3

+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES

        select SYS_FSL_DDR
        select SYS_FSL_DDR_LE
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_DDR
        select SYS_FSL_DDR_LE
        select SYS_FSL_DDR_VER_50

+       select SYS_FSL_HAS_CCN504

        select SYS_FSL_HAS_DP_DDR
        select SYS_FSL_HAS_SEC
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_HAS_DP_DDR
        select SYS_FSL_HAS_SEC
        select SYS_FSL_HAS_DDR4


@@ -69,19 +150,68 @@ config ARCH_LS2080A
        select SYS_FSL_SRDS_2
        select FSL_TZASC_1
        select FSL_TZASC_2
        select SYS_FSL_SRDS_2
        select FSL_TZASC_1
        select FSL_TZASC_2

-       select SYS_FSL_ERRATUM_A008336
-       select SYS_FSL_ERRATUM_A008511
-       select SYS_FSL_ERRATUM_A008514
+       select FSL_TZASC_400
+       select FSL_TZPC_BP147
+       select SYS_FSL_ERRATUM_A008336 if !TFABOOT
+       select SYS_FSL_ERRATUM_A008511 if !TFABOOT
+       select SYS_FSL_ERRATUM_A008514 if !TFABOOT

        select SYS_FSL_ERRATUM_A008585
        select SYS_FSL_ERRATUM_A008585

+       select SYS_FSL_ERRATUM_A008997
+       select SYS_FSL_ERRATUM_A009007
+       select SYS_FSL_ERRATUM_A009008

        select SYS_FSL_ERRATUM_A009635
        select SYS_FSL_ERRATUM_A009635

-       select SYS_FSL_ERRATUM_A009663
+       select SYS_FSL_ERRATUM_A009663 if !TFABOOT
+       select SYS_FSL_ERRATUM_A009798

        select SYS_FSL_ERRATUM_A009801
        select SYS_FSL_ERRATUM_A009801

-       select SYS_FSL_ERRATUM_A009803
-       select SYS_FSL_ERRATUM_A009942
-       select SYS_FSL_ERRATUM_A010165
+       select SYS_FSL_ERRATUM_A009803 if !TFABOOT
+       select SYS_FSL_ERRATUM_A009942 if !TFABOOT
+       select SYS_FSL_ERRATUM_A010165 if !TFABOOT

        select SYS_FSL_ERRATUM_A009203
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_FSL_ERRATUM_A009203
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F

+       select SYS_I2C_MXC
+       select SYS_I2C_MXC_I2C1
+       select SYS_I2C_MXC_I2C2
+       select SYS_I2C_MXC_I2C3
+       select SYS_I2C_MXC_I2C4
+       imply DISTRO_DEFAULTS
+       imply PANIC_HANG
+
+config ARCH_LX2160A
+       bool
+       select ARMV8_SET_SMPEN
+       select FSL_LSCH3
+       select NXP_LSCH3_2
+       select SYS_HAS_SERDES
+       select SYS_FSL_SRDS_1
+       select SYS_FSL_SRDS_2
+       select SYS_NXP_SRDS_3
+       select SYS_FSL_DDR
+       select SYS_FSL_DDR_LE
+       select SYS_FSL_DDR_VER_50
+       select SYS_FSL_EC1
+       select SYS_FSL_EC2
+       select SYS_FSL_HAS_RGMII
+       select SYS_FSL_HAS_SEC
+       select SYS_FSL_HAS_CCN508
+       select SYS_FSL_HAS_DDR4
+       select SYS_FSL_SEC_COMPAT_5
+       select SYS_FSL_SEC_LE
+       select ARCH_EARLY_INIT_R
+       select BOARD_EARLY_INIT_F
+       select SYS_I2C_MXC
+       select SYS_I2C_MXC_I2C1
+       select SYS_I2C_MXC_I2C2
+       select SYS_I2C_MXC_I2C3
+       select SYS_I2C_MXC_I2C4
+       select SYS_I2C_MXC_I2C5
+       select SYS_I2C_MXC_I2C6
+       select SYS_I2C_MXC_I2C7
+       select SYS_I2C_MXC_I2C8
+       imply DISTRO_DEFAULTS
+       imply PANIC_HANG
+       imply SCSI
+       imply SCSI_AHCI

 
 config FSL_LSCH2
        bool
 
 config FSL_LSCH2
        bool


@@ -89,17 +219,16 @@ config FSL_LSCH2
        select SYS_FSL_HAS_SEC
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_SEC_BE
        select SYS_FSL_HAS_SEC
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_SEC_BE

-       select SYS_FSL_SRDS_1
-       select SYS_HAS_SERDES

 
 config FSL_LSCH3
        bool
 
 config FSL_LSCH3
        bool

-       select SYS_FSL_SRDS_1
-       select SYS_HAS_SERDES
+
+config NXP_LSCH3_2
+       bool

 
 config FSL_MC_ENET
        bool "Management Complex network"
 
 config FSL_MC_ENET
        bool "Management Complex network"

-       depends on ARCH_LS2080A
+       depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A

        default y
        select RESV_RAM
        help
        default y
        select RESV_RAM
        help


@@ -108,6 +237,9 @@ config FSL_MC_ENET
 menu "Layerscape architecture"
        depends on FSL_LSCH2 || FSL_LSCH3
 
 menu "Layerscape architecture"
        depends on FSL_LSCH2 || FSL_LSCH3
 

+config FSL_LAYERSCAPE
+       bool
+

 config FSL_PCIE_COMPAT
        string "PCIe compatible of Kernel DT"
        depends on PCIE_LAYERSCAPE
 config FSL_PCIE_COMPAT
        string "PCIe compatible of Kernel DT"
        depends on PCIE_LAYERSCAPE


@@ -115,6 +247,8 @@ config FSL_PCIE_COMPAT
        default "fsl,ls1043a-pcie" if ARCH_LS1043A
        default "fsl,ls1046a-pcie" if ARCH_LS1046A
        default "fsl,ls2080a-pcie" if ARCH_LS2080A
        default "fsl,ls1043a-pcie" if ARCH_LS1043A
        default "fsl,ls1046a-pcie" if ARCH_LS1046A
        default "fsl,ls2080a-pcie" if ARCH_LS2080A

+       default "fsl,ls1088a-pcie" if ARCH_LS1088A
+       default "fsl,lx2160a-pcie" if ARCH_LX2160A

        help
          This compatible is used to find pci controller node in Kernel DT
          to complete fixup.
        help
          This compatible is used to find pci controller node in Kernel DT
          to complete fixup.


@@ -177,37 +311,6 @@ config SYS_LS_PPA_FW_IN_NAND
 
 endchoice
 
 
 endchoice
 

-config SYS_LS_PPA_FW_ADDR
-       hex "Address of PPA firmware loading from"
-       depends on FSL_LS_PPA
-       default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
-       default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
-       default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
-       default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
-       default 0x400000 if SYS_LS_PPA_FW_IN_MMC
-       default 0x400000 if SYS_LS_PPA_FW_IN_NAND
-
-       help
-         If the PPA firmware locate at XIP flash, such as NOR or
-         QSPI flash, this address is a directly memory-mapped.
-         If it is in a serial accessed flash, such as NAND and SD
-         card, it is a byte offset.
-
-config SYS_LS_PPA_ESBC_ADDR
-       hex "hdr address of PPA firmware loading from"
-       depends on FSL_LS_PPA && CHAIN_OF_TRUST
-       default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
-       default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
-       default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
-       default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
-       default 0x680000 if SYS_LS_PPA_FW_IN_MMC
-       default 0x680000 if SYS_LS_PPA_FW_IN_NAND
-       help
-         If the PPA header firmware locate at XIP flash, such as NOR or
-         QSPI flash, this address is a directly memory-mapped.
-         If it is in a serial accessed flash, such as NAND and SD
-         card, it is a byte offset.
-

 config LS_PPA_ESBC_HDR_SIZE
        hex "Length of PPA ESBC header"
        depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
 config LS_PPA_ESBC_HDR_SIZE
        hex "Length of PPA ESBC header"
        depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP


@@ -218,6 +321,20 @@ config LS_PPA_ESBC_HDR_SIZE
 
 endmenu
 
 
 endmenu
 

+config SYS_FSL_ERRATUM_A008997
+       bool "Workaround for USB PHY erratum A008997"
+
+config SYS_FSL_ERRATUM_A009007
+       bool
+       help
+         Workaround for USB PHY erratum A009007
+
+config SYS_FSL_ERRATUM_A009008
+       bool "Workaround for USB PHY erratum A009008"
+
+config SYS_FSL_ERRATUM_A009798
+       bool "Workaround for USB PHY erratum A009798"
+

 config SYS_FSL_ERRATUM_A010315
        bool "Workaround for PCIe erratum A010315"
 
 config SYS_FSL_ERRATUM_A010315
        bool "Workaround for PCIe erratum A010315"
 


@@ -229,6 +346,8 @@ config MAX_CPUS
        default 4 if ARCH_LS1043A
        default 4 if ARCH_LS1046A
        default 16 if ARCH_LS2080A
        default 4 if ARCH_LS1043A
        default 4 if ARCH_LS1046A
        default 16 if ARCH_LS2080A

+       default 8 if ARCH_LS1088A
+       default 16 if ARCH_LX2160A

        default 1
        help
          Set this number to the maximum number of possible CPUs in the SoC.
        default 1
        help
          Set this number to the maximum number of possible CPUs in the SoC.


@@ -237,6 +356,12 @@ config MAX_CPUS
          cores, count the reserved ports. This will allocate enough memory
          in spin table to properly handle all cores.
 
          cores, count the reserved ports. This will allocate enough memory
          in spin table to properly handle all cores.
 

+config EMC2305
+       bool "Fan controller"
+       help
+        Enable the EMC2305 fan controller for configuration of fan
+        speed.
+

 config SECURE_BOOT
        bool "Secure Boot"
        help
 config SECURE_BOOT
        bool "Secure Boot"
        help


@@ -260,14 +385,20 @@ config SYS_CCI400_OFFSET
 
 config SYS_FSL_IFC_BANK_COUNT
        int "Maximum banks of Integrated flash controller"
 
 config SYS_FSL_IFC_BANK_COUNT
        int "Maximum banks of Integrated flash controller"

-       depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
+       depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A

        default 4 if ARCH_LS1043A
        default 4 if ARCH_LS1046A
        default 4 if ARCH_LS1043A
        default 4 if ARCH_LS1046A

-       default 8 if ARCH_LS2080A
+       default 8 if ARCH_LS2080A || ARCH_LS1088A

 
 config SYS_FSL_HAS_CCI400
        bool
 
 
 config SYS_FSL_HAS_CCI400
        bool
 

+config SYS_FSL_HAS_CCN504
+       bool
+
+config SYS_FSL_HAS_CCN508
+       bool
+

 config SYS_FSL_HAS_DP_DDR
        bool
 
 config SYS_FSL_HAS_DP_DDR
        bool
 


@@ -277,6 +408,9 @@ config SYS_FSL_SRDS_1
 config SYS_FSL_SRDS_2
        bool
 
 config SYS_FSL_SRDS_2
        bool
 

+config SYS_NXP_SRDS_3
+       bool
+

 config SYS_HAS_SERDES
        bool
 
 config SYS_HAS_SERDES
        bool
 


@@ -286,6 +420,11 @@ config FSL_TZASC_1
 config FSL_TZASC_2
        bool
 
 config FSL_TZASC_2
        bool
 

+config FSL_TZASC_400
+       bool
+
+config FSL_TZPC_BP147
+       bool

 endmenu
 
 menu "Layerscape clock tree configuration"
 endmenu
 
 menu "Layerscape clock tree configuration"


@@ -309,6 +448,7 @@ config SYS_FSL_PCLK_DIV
        int "Platform clock divider"
        default 1 if ARCH_LS1043A
        default 1 if ARCH_LS1046A
        int "Platform clock divider"
        default 1 if ARCH_LS1043A
        default 1 if ARCH_LS1046A

+       default 1 if ARCH_LS1088A

        default 2
        help
          This is the divider that is used to derive Platform clock from
        default 2
        help
          This is the divider that is used to derive Platform clock from


@@ -326,6 +466,7 @@ config SYS_FSL_DSPI_CLK_DIV
 config SYS_FSL_DUART_CLK_DIV
        int "DUART clock divider"
        default 1 if ARCH_LS1043A
 config SYS_FSL_DUART_CLK_DIV
        int "DUART clock divider"
        default 1 if ARCH_LS1043A

+       default 4 if ARCH_LX2160A

        default 2
        help
          This is the divider that is used to derive DUART clock from Platform
        default 2
        help
          This is the divider that is used to derive DUART clock from Platform


@@ -363,6 +504,14 @@ config SYS_FSL_SDHC_CLK_DIV
        help
          This is the divider that is used to derive SDHC clock from Platform
          clock, in another word SDHC_clk = Platform_clk / this_divider.
        help
          This is the divider that is used to derive SDHC clock from Platform
          clock, in another word SDHC_clk = Platform_clk / this_divider.

+
+config SYS_FSL_QMAN_CLK_DIV
+       int "QMAN clock divider"
+       default 1 if ARCH_LS1043A
+       default 2
+       help
+         This is the divider that is used to derive QMAN clock from Platform
+         clock, in another word QMAN_clk = Platform_clk / this_divider.

 endmenu
 
 config RESV_RAM
 endmenu
 
 config RESV_RAM


@@ -375,6 +524,20 @@ config RESV_RAM
          be at the high end of physical memory. The reserve RAM may be
          excluded from memory bank(s) passed to OS, or marked as reserved.
 
          be at the high end of physical memory. The reserve RAM may be
          excluded from memory bank(s) passed to OS, or marked as reserved.
 

+config SYS_FSL_EC1
+       bool
+       help
+         Ethernet controller 1, this is connected to
+         MAC17 for LX2160A or to MAC3 for other SoCs
+         Provides DPAA2 capabilities
+
+config SYS_FSL_EC2
+       bool
+       help
+         Ethernet controller 2, this is connected to
+         MAC18 for LX2160A or to MAC4 for other SoCs
+         Provides DPAA2 capabilities
+

 config SYS_FSL_ERRATUM_A008336
        bool
 
 config SYS_FSL_ERRATUM_A008336
        bool
 


@@ -399,13 +562,33 @@ config SYS_FSL_ERRATUM_A009660
 config SYS_FSL_ERRATUM_A009929
        bool
 
 config SYS_FSL_ERRATUM_A009929
        bool
 

+
+config SYS_FSL_HAS_RGMII
+       bool
+       depends on SYS_FSL_EC1 || SYS_FSL_EC2
+
+

 config SYS_MC_RSV_MEM_ALIGN
        hex "Management Complex reserved memory alignment"
        depends on RESV_RAM
 config SYS_MC_RSV_MEM_ALIGN
        hex "Management Complex reserved memory alignment"
        depends on RESV_RAM

-       default 0x20000000
+       default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A

        help
          Reserved memory needs to be aligned for MC to use. Default value
          is 512MB.
 
 config SPL_LDSCRIPT
        default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
        help
          Reserved memory needs to be aligned for MC to use. Default value
          is 512MB.
 
 config SPL_LDSCRIPT
        default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A

+
+config HAS_FSL_XHCI_USB
+       bool
+       default y if ARCH_LS1043A || ARCH_LS1046A
+       help
+         For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
+         pins, select it when the pins are assigned to USB.
+
+config TFABOOT
+       bool "Support for booting from TFA"
+       default n
+       help
+         Enabling this will make a U-Boot binary that is capable of being
+         booted via TFA.