Merge tag 'u-boot-atmel-fixes-2021.01-b' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index f48481f..4d46587 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -16,8 +16,38 @@ config ARCH_LS1012A
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_I2C_MXC
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_I2C_MXC

-       select SYS_I2C_MXC_I2C1
-       select SYS_I2C_MXC_I2C2
+       select SYS_I2C_MXC_I2C1 if !DM_I2C
+       select SYS_I2C_MXC_I2C2 if !DM_I2C
+       imply PANIC_HANG
+
+config ARCH_LS1028A
+       bool
+       select ARMV8_SET_SMPEN
+       select FSL_LAYERSCAPE
+       select FSL_LSCH3
+       select NXP_LSCH3_2
+       select SYS_FSL_HAS_CCI400
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
+       select SYS_FSL_DDR
+       select SYS_FSL_DDR_LE
+       select SYS_FSL_DDR_VER_50
+       select SYS_FSL_HAS_DDR3
+       select SYS_FSL_HAS_DDR4
+       select SYS_FSL_HAS_SEC
+       select SYS_FSL_SEC_COMPAT_5
+       select SYS_FSL_SEC_LE
+       select FSL_TZASC_1
+       select ARCH_EARLY_INIT_R
+       select BOARD_EARLY_INIT_F
+       select SYS_I2C_MXC
+       select SYS_FSL_ERRATUM_A008997
+       select SYS_FSL_ERRATUM_A009007
+       select SYS_FSL_ERRATUM_A008514 if !TFABOOT
+       select SYS_FSL_ERRATUM_A009663 if !TFABOOT
+       select SYS_FSL_ERRATUM_A009942 if !TFABOOT
+       select SYS_FSL_ERRATUM_A050382
+       select RESV_RAM if GIC_V3_ITS

        imply PANIC_HANG
 
 config ARCH_LS1043A
        imply PANIC_HANG
 
 config ARCH_LS1043A


@@ -38,7 +68,6 @@ config ARCH_LS1043A
        select SYS_FSL_ERRATUM_A009660 if !TFABOOT
        select SYS_FSL_ERRATUM_A009663 if !TFABOOT
        select SYS_FSL_ERRATUM_A009798
        select SYS_FSL_ERRATUM_A009660 if !TFABOOT
        select SYS_FSL_ERRATUM_A009663 if !TFABOOT
        select SYS_FSL_ERRATUM_A009798

-       select SYS_FSL_ERRATUM_A009929

        select SYS_FSL_ERRATUM_A009942 if !TFABOOT
        select SYS_FSL_ERRATUM_A010315
        select SYS_FSL_ERRATUM_A010539
        select SYS_FSL_ERRATUM_A009942 if !TFABOOT
        select SYS_FSL_ERRATUM_A010315
        select SYS_FSL_ERRATUM_A010539


@@ -47,10 +76,10 @@ config ARCH_LS1043A
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_I2C_MXC
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_I2C_MXC

-       select SYS_I2C_MXC_I2C1
-       select SYS_I2C_MXC_I2C2
-       select SYS_I2C_MXC_I2C3
-       select SYS_I2C_MXC_I2C4
+       select SYS_I2C_MXC_I2C1 if !DM_I2C
+       select SYS_I2C_MXC_I2C2 if !DM_I2C
+       select SYS_I2C_MXC_I2C3 if !DM_I2C
+       select SYS_I2C_MXC_I2C4 if !DM_I2C

        imply CMD_PCI
 
 config ARCH_LS1046A
        imply CMD_PCI
 
 config ARCH_LS1046A


@@ -80,10 +109,10 @@ config ARCH_LS1046A
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_I2C_MXC
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_I2C_MXC

-       select SYS_I2C_MXC_I2C1
-       select SYS_I2C_MXC_I2C2
-       select SYS_I2C_MXC_I2C3
-       select SYS_I2C_MXC_I2C4
+       select SYS_I2C_MXC_I2C1 if !DM_I2C
+       select SYS_I2C_MXC_I2C2 if !DM_I2C
+       select SYS_I2C_MXC_I2C3 if !DM_I2C
+       select SYS_I2C_MXC_I2C4 if !DM_I2C

        imply SCSI
        imply SCSI_AHCI
 
        imply SCSI
        imply SCSI_AHCI
 


@@ -120,10 +149,11 @@ config ARCH_LS1088A
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_I2C_MXC
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_I2C_MXC

-       select SYS_I2C_MXC_I2C1
-       select SYS_I2C_MXC_I2C2
-       select SYS_I2C_MXC_I2C3
-       select SYS_I2C_MXC_I2C4
+       select SYS_I2C_MXC_I2C1 if !TFABOOT
+       select SYS_I2C_MXC_I2C2 if !TFABOOT
+       select SYS_I2C_MXC_I2C3 if !TFABOOT
+       select SYS_I2C_MXC_I2C4 if !TFABOOT
+       select RESV_RAM if GIC_V3_ITS

        imply SCSI
        imply PANIC_HANG
 
        imply SCSI
        imply PANIC_HANG
 


@@ -170,13 +200,43 @@ config ARCH_LS2080A
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_I2C_MXC
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_I2C_MXC

-       select SYS_I2C_MXC_I2C1
-       select SYS_I2C_MXC_I2C2
-       select SYS_I2C_MXC_I2C3
-       select SYS_I2C_MXC_I2C4
+       select SYS_I2C_MXC_I2C1 if !TFABOOT
+       select SYS_I2C_MXC_I2C2 if !TFABOOT
+       select SYS_I2C_MXC_I2C3 if !TFABOOT
+       select SYS_I2C_MXC_I2C4 if !TFABOOT
+       select RESV_RAM if GIC_V3_ITS

        imply DISTRO_DEFAULTS
        imply PANIC_HANG
 
        imply DISTRO_DEFAULTS
        imply PANIC_HANG
 

+config ARCH_LX2162A
+       bool
+       select ARMV8_SET_SMPEN
+       select FSL_LSCH3
+       select NXP_LSCH3_2
+       select SYS_HAS_SERDES
+       select SYS_FSL_SRDS_1
+       select SYS_FSL_SRDS_2
+       select SYS_FSL_DDR
+       select SYS_FSL_DDR_LE
+       select SYS_FSL_DDR_VER_50
+       select SYS_FSL_EC1
+       select SYS_FSL_EC2
+       select SYS_FSL_ERRATUM_A050106
+       select SYS_FSL_HAS_RGMII
+       select SYS_FSL_HAS_SEC
+       select SYS_FSL_HAS_CCN508
+       select SYS_FSL_HAS_DDR4
+       select SYS_FSL_SEC_COMPAT_5
+       select SYS_FSL_SEC_LE
+       select ARCH_EARLY_INIT_R
+       select BOARD_EARLY_INIT_F
+       select SYS_I2C_MXC
+       select RESV_RAM if GIC_V3_ITS
+       imply DISTRO_DEFAULTS
+       imply PANIC_HANG
+       imply SCSI
+       imply SCSI_AHCI
+

 config ARCH_LX2160A
        bool
        select ARMV8_SET_SMPEN
 config ARCH_LX2160A
        bool
        select ARMV8_SET_SMPEN


@@ -191,6 +251,7 @@ config ARCH_LX2160A
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_EC1
        select SYS_FSL_EC2
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_EC1
        select SYS_FSL_EC2

+       select SYS_FSL_ERRATUM_A050106

        select SYS_FSL_HAS_RGMII
        select SYS_FSL_HAS_SEC
        select SYS_FSL_HAS_CCN508
        select SYS_FSL_HAS_RGMII
        select SYS_FSL_HAS_SEC
        select SYS_FSL_HAS_CCN508


@@ -200,14 +261,7 @@ config ARCH_LX2160A
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_I2C_MXC
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_I2C_MXC

-       select SYS_I2C_MXC_I2C1
-       select SYS_I2C_MXC_I2C2
-       select SYS_I2C_MXC_I2C3
-       select SYS_I2C_MXC_I2C4
-       select SYS_I2C_MXC_I2C5
-       select SYS_I2C_MXC_I2C6
-       select SYS_I2C_MXC_I2C7
-       select SYS_I2C_MXC_I2C8
+       select RESV_RAM if GIC_V3_ITS

        imply DISTRO_DEFAULTS
        imply PANIC_HANG
        imply SCSI
        imply DISTRO_DEFAULTS
        imply PANIC_HANG
        imply SCSI


@@ -221,38 +275,18 @@ config FSL_LSCH2
        select SYS_FSL_SEC_BE
 
 config FSL_LSCH3
        select SYS_FSL_SEC_BE
 
 config FSL_LSCH3

+       select ARCH_MISC_INIT

        bool
 
 config NXP_LSCH3_2
        bool
 
        bool
 
 config NXP_LSCH3_2
        bool
 

-config FSL_MC_ENET
-       bool "Management Complex network"
-       depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
-       default y
-       select RESV_RAM
-       help
-         Enable Management Complex (MC) network
-

 menu "Layerscape architecture"
        depends on FSL_LSCH2 || FSL_LSCH3
 
 config FSL_LAYERSCAPE
        bool
 
 menu "Layerscape architecture"
        depends on FSL_LSCH2 || FSL_LSCH3
 
 config FSL_LAYERSCAPE
        bool
 

-config FSL_PCIE_COMPAT
-       string "PCIe compatible of Kernel DT"
-       depends on PCIE_LAYERSCAPE
-       default "fsl,ls1012a-pcie" if ARCH_LS1012A
-       default "fsl,ls1043a-pcie" if ARCH_LS1043A
-       default "fsl,ls1046a-pcie" if ARCH_LS1046A
-       default "fsl,ls2080a-pcie" if ARCH_LS2080A
-       default "fsl,ls1088a-pcie" if ARCH_LS1088A
-       default "fsl,lx2160a-pcie" if ARCH_LX2160A
-       help
-         This compatible is used to find pci controller node in Kernel DT
-         to complete fixup.
-

 config HAS_FEATURE_GIC64K_ALIGN
        bool
        default y if ARCH_LS1043A
 config HAS_FEATURE_GIC64K_ALIGN
        bool
        default y if ARCH_LS1043A


@@ -335,6 +369,14 @@ config SYS_FSL_ERRATUM_A009008
 config SYS_FSL_ERRATUM_A009798
        bool "Workaround for USB PHY erratum A009798"
 
 config SYS_FSL_ERRATUM_A009798
        bool "Workaround for USB PHY erratum A009798"
 

+config SYS_FSL_ERRATUM_A050106
+       bool "Workaround for USB PHY erratum A050106"
+       help
+         USB3.0 Receiver needs to enable fixed equalization
+         for each of PHY instances in an SOC. This is similar
+         to erratum A-009007, but this one is for LX2160A and LX2162A,
+         and the register value is different.
+

 config SYS_FSL_ERRATUM_A010315
        bool "Workaround for PCIe erratum A010315"
 
 config SYS_FSL_ERRATUM_A010315
        bool "Workaround for PCIe erratum A010315"
 


@@ -343,11 +385,13 @@ config SYS_FSL_ERRATUM_A010539
 
 config MAX_CPUS
        int "Maximum number of CPUs permitted for Layerscape"
 
 config MAX_CPUS
        int "Maximum number of CPUs permitted for Layerscape"

+       default 2 if ARCH_LS1028A

        default 4 if ARCH_LS1043A
        default 4 if ARCH_LS1046A
        default 16 if ARCH_LS2080A
        default 8 if ARCH_LS1088A
        default 16 if ARCH_LX2160A
        default 4 if ARCH_LS1043A
        default 4 if ARCH_LS1046A
        default 16 if ARCH_LS2080A
        default 8 if ARCH_LS1088A
        default 16 if ARCH_LX2160A

+       default 16 if ARCH_LX2162A

        default 1
        help
          Set this number to the maximum number of possible CPUs in the SoC.
        default 1
        help
          Set this number to the maximum number of possible CPUs in the SoC.


@@ -362,8 +406,8 @@ config EMC2305
         Enable the EMC2305 fan controller for configuration of fan
         speed.
 
         Enable the EMC2305 fan controller for configuration of fan
         speed.
 

-config SECURE_BOOT
-       bool "Secure Boot"
+config NXP_ESBC
+       bool "NXP_ESBC"

        help
                Enable Freescale Secure Boot feature
 
        help
                Enable Freescale Secure Boot feature
 


@@ -374,10 +418,19 @@ config QSPI_AHB_INIT
          But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
          bus for those flashes to support the full QSPI flash size.
 
          But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
          bus for those flashes to support the full QSPI flash size.
 

+config FSPI_AHB_EN_4BYTE
+       bool "Enable 4-byte Fast Read command for AHB mode"
+       default n
+       help
+         The default setting for FlexSPI AHB bus just supports 3-byte addressing.
+         But some FlexSPI flash sizes are up to 64MBytes.
+         This flag enables fast read command for AHB mode and modifies required
+         LUT to support full FlexSPI flash.
+

 config SYS_CCI400_OFFSET
        hex "Offset for CCI400 base"
        depends on SYS_FSL_HAS_CCI400
 config SYS_CCI400_OFFSET
        hex "Offset for CCI400 base"
        depends on SYS_FSL_HAS_CCI400

-       default 0x3090000 if ARCH_LS1088A
+       default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A

        default 0x180000 if FSL_LSCH2
        help
          Offset for CCI400 base
        default 0x180000 if FSL_LSCH2
        help
          Offset for CCI400 base


@@ -446,6 +499,7 @@ config CLUSTER_CLK_FREQ
 
 config SYS_FSL_PCLK_DIV
        int "Platform clock divider"
 
 config SYS_FSL_PCLK_DIV
        int "Platform clock divider"

+       default 1 if ARCH_LS1028A

        default 1 if ARCH_LS1043A
        default 1 if ARCH_LS1046A
        default 1 if ARCH_LS1088A
        default 1 if ARCH_LS1043A
        default 1 if ARCH_LS1046A
        default 1 if ARCH_LS1088A


@@ -467,6 +521,7 @@ config SYS_FSL_DUART_CLK_DIV
        int "DUART clock divider"
        default 1 if ARCH_LS1043A
        default 4 if ARCH_LX2160A
        int "DUART clock divider"
        default 1 if ARCH_LS1043A
        default 4 if ARCH_LX2160A

+       default 4 if ARCH_LX2162A

        default 2
        help
          This is the divider that is used to derive DUART clock from Platform
        default 2
        help
          This is the divider that is used to derive DUART clock from Platform


@@ -475,6 +530,11 @@ config SYS_FSL_DUART_CLK_DIV
 config SYS_FSL_I2C_CLK_DIV
        int "I2C clock divider"
        default 1 if ARCH_LS1043A
 config SYS_FSL_I2C_CLK_DIV
        int "I2C clock divider"
        default 1 if ARCH_LS1043A

+       default 4 if ARCH_LS1012A
+       default 4 if ARCH_LS1028A
+       default 8 if ARCH_LX2160A
+       default 8 if ARCH_LX2162A
+       default 8 if ARCH_LS1088A

        default 2
        help
          This is the divider that is used to derive I2C clock from Platform
        default 2
        help
          This is the divider that is used to derive I2C clock from Platform


@@ -483,6 +543,11 @@ config SYS_FSL_I2C_CLK_DIV
 config SYS_FSL_IFC_CLK_DIV
        int "IFC clock divider"
        default 1 if ARCH_LS1043A
 config SYS_FSL_IFC_CLK_DIV
        int "IFC clock divider"
        default 1 if ARCH_LS1043A

+       default 4 if ARCH_LS1012A
+       default 4 if ARCH_LS1028A
+       default 8 if ARCH_LX2160A
+       default 8 if ARCH_LX2162A
+       default 8 if ARCH_LS1088A

        default 2
        help
          This is the divider that is used to derive IFC clock from Platform
        default 2
        help
          This is the divider that is used to derive IFC clock from Platform


@@ -528,14 +593,14 @@ config SYS_FSL_EC1
        bool
        help
          Ethernet controller 1, this is connected to
        bool
        help
          Ethernet controller 1, this is connected to

-         MAC17 for LX2160A or to MAC3 for other SoCs
+         MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs

          Provides DPAA2 capabilities
 
 config SYS_FSL_EC2
        bool
        help
          Ethernet controller 2, this is connected to
          Provides DPAA2 capabilities
 
 config SYS_FSL_EC2
        bool
        help
          Ethernet controller 2, this is connected to

-         MAC18 for LX2160A or to MAC4 for other SoCs
+         MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs

          Provides DPAA2 capabilities
 
 config SYS_FSL_ERRATUM_A008336
          Provides DPAA2 capabilities
 
 config SYS_FSL_ERRATUM_A008336


@@ -559,23 +624,13 @@ config SYS_FSL_ERRATUM_A009635
 config SYS_FSL_ERRATUM_A009660
        bool
 
 config SYS_FSL_ERRATUM_A009660
        bool
 

-config SYS_FSL_ERRATUM_A009929
+config SYS_FSL_ERRATUM_A050382

        bool
 
        bool
 

-

 config SYS_FSL_HAS_RGMII
        bool
        depends on SYS_FSL_EC1 || SYS_FSL_EC2
 
 config SYS_FSL_HAS_RGMII
        bool
        depends on SYS_FSL_EC1 || SYS_FSL_EC2
 

-
-config SYS_MC_RSV_MEM_ALIGN
-       hex "Management Complex reserved memory alignment"
-       depends on RESV_RAM
-       default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
-       help
-         Reserved memory needs to be aligned for MC to use. Default value
-         is 512MB.
-

 config SPL_LDSCRIPT
        default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
 
 config SPL_LDSCRIPT
        default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
 


@@ -585,10 +640,3 @@ config HAS_FSL_XHCI_USB
        help
          For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
          pins, select it when the pins are assigned to USB.
        help
          For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
          pins, select it when the pins are assigned to USB.

-
-config TFABOOT
-       bool "Support for booting from TFA"
-       default n
-       help
-         Enabling this will make a U-Boot binary that is capable of being
-         booted via TFA.