+#define ARC_BCR_SLC 0xce
+#define ARC_AUX_SLC_CONFIG 0x901
+#define ARC_AUX_SLC_CTRL 0x903
+#define ARC_AUX_SLC_FLUSH 0x904
+#define ARC_AUX_SLC_INVALIDATE 0x905
+#define ARC_AUX_SLC_IVDL 0x910
+#define ARC_AUX_SLC_FLDL 0x912
+#define ARC_AUX_SLC_RGN_START 0x914
+#define ARC_AUX_SLC_RGN_START1 0x915
+#define ARC_AUX_SLC_RGN_END 0x916
+#define ARC_AUX_SLC_RGN_END1 0x917
+#define ARC_BCR_CLUSTER 0xcf
+
+/* MMU Management regs */
+#define ARC_AUX_MMU_BCR 0x6f
+
+/* IO coherency related auxiliary registers */
+#define ARC_AUX_IO_COH_ENABLE 0x500
+#define ARC_AUX_IO_COH_PARTIAL 0x501
+#define ARC_AUX_IO_COH_AP0_BASE 0x508
+#define ARC_AUX_IO_COH_AP0_SIZE 0x509
+
+/* XY-memory related */
+#define ARC_AUX_XY_BUILD 0x79
+
+/* DSP-extensions related auxiliary registers */
+#define ARC_AUX_DSP_BUILD 0x7A
+#define ARC_AUX_DSP_CTRL 0x59F
+
+/* ARC Subsystems related auxiliary registers */
+#define ARC_AUX_SUBSYS_BUILD 0xF0