+config SYS_IMMR
+ hex
+ depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
+ default 0xFF000000 if MPC8xx
+ default 0xF0000000 if ARCH_MPC8313
+ default 0xE0000000 if MPC83xx && !ARCH_MPC8313
+ default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
+ default SYS_CCSRBAR_DEFAULT
+ help
+ Address for the Internal Memory-Mapped Registers (IMMR) window used
+ to configure the features of many Freescale / NXP SoCs.
+
+config SKIP_LOWLEVEL_INIT
+ bool "Skip the calls to certain low level initialization functions"
+ depends on ARM || NDS32 || MIPS || RISCV
+ help
+ If enabled, then certain low level initializations (like setting up
+ the memory controller) are omitted and/or U-Boot does not relocate
+ itself into RAM.
+ Normally this variable MUST NOT be defined. The only exception is
+ when U-Boot is loaded (to RAM) by some other boot loader or by a
+ debugger which performs these initializations itself.
+
+config SPL_SKIP_LOWLEVEL_INIT
+ bool "Skip the calls to certain low level initialization functions"
+ depends on SPL && (ARM || NDS32 || MIPS || RISCV)
+ help
+ If enabled, then certain low level initializations (like setting up
+ the memory controller) are omitted and/or U-Boot does not relocate
+ itself into RAM.
+ Normally this variable MUST NOT be defined. The only exception is
+ when U-Boot is loaded (to RAM) by some other boot loader or by a
+ debugger which performs these initializations itself.
+
+config TPL_SKIP_LOWLEVEL_INIT
+ bool "Skip the calls to certain low level initialization functions"
+ depends on SPL && ARM
+ help
+ If enabled, then certain low level initializations (like setting up
+ the memory controller) are omitted and/or U-Boot does not relocate
+ itself into RAM.
+ Normally this variable MUST NOT be defined. The only exception is
+ when U-Boot is loaded (to RAM) by some other boot loader or by a
+ debugger which performs these initializations itself.
+
+config SKIP_LOWLEVEL_INIT_ONLY
+ bool "Skip the call to lowlevel_init during early boot ONLY"
+ depends on ARM
+ help
+ This allows just the call to lowlevel_init() to be skipped. The
+ normal CP15 init (such as enabling the instruction cache) is still
+ performed.
+
+config SPL_SKIP_LOWLEVEL_INIT_ONLY
+ bool "Skip the call to lowlevel_init during early boot ONLY"
+ depends on SPL && ARM
+ help
+ This allows just the call to lowlevel_init() to be skipped. The
+ normal CP15 init (such as enabling the instruction cache) is still
+ performed.
+
+config TPL_SKIP_LOWLEVEL_INIT_ONLY
+ bool "Skip the call to lowlevel_init during early boot ONLY"
+ depends on TPL && ARM
+ help
+ This allows just the call to lowlevel_init() to be skipped. The
+ normal CP15 init (such as enabling the instruction cache) is still
+ performed.
+