ARM: k2g: Program DDR PHY MR2 register with the default value

[platform/kernel/u-boot.git] / README

diff --git a/README b/README
index a6cf9d9..ee35dec 100644 (file)
--- a/README
+++ b/README
@@ -687,29 +687,10 @@ The following options need to be configured:
                Define this variable to enable hw flow control in serial driver.
                Current user of this option is drivers/serial/nsl16550.c driver
 
                Define this variable to enable hw flow control in serial driver.
                Current user of this option is drivers/serial/nsl16550.c driver
 

-- Console Interface:
-               Depending on board, define exactly one serial port
-               (CONFIG_8xx_CONS_SMC1 or CONFIG_8xx_CONS_SMC2),
-               or switch off the serial console by defining
-               CONFIG_8xx_CONS_NONE
-
-               Note: if CONFIG_8xx_CONS_NONE is defined, the serial
-               port routines must be defined elsewhere
-               (i.e. serial_init(), serial_getc(), ...)
-

 - Console Baudrate:
                CONFIG_BAUDRATE - in bps
                Select one of the baudrates listed in
                CONFIG_SYS_BAUDRATE_TABLE, see below.
 - Console Baudrate:
                CONFIG_BAUDRATE - in bps
                Select one of the baudrates listed in
                CONFIG_SYS_BAUDRATE_TABLE, see below.

-               CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale
-
-- Console Rx buffer length
-               With CONFIG_SYS_SMC_RXBUFLEN it is possible to define
-               the maximum receive buffer length for the SMC.
-               This option is actual only for 8xx possible.
-               If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE
-               must be defined, to setup the maximum idle timeout for
-               the SMC.

 
 - Autoboot Command:
                CONFIG_BOOTCOMMAND
 
 - Autoboot Command:
                CONFIG_BOOTCOMMAND


@@ -4079,21 +4060,6 @@ Low Level (hardware related) configuration options:
                Only for 83xx systems. If specified, then DDR should
                be configured using CS0 and CS1 instead of CS2 and CS3.
 
                Only for 83xx systems. If specified, then DDR should
                be configured using CS0 and CS1 instead of CS2 and CS3.
 

-- CONFIG_ETHER_ON_FEC[12]
-               Define to enable FEC[12] on a 8xx series processor.
-
-- CONFIG_FEC[12]_PHY
-               Define to the hardcoded PHY address which corresponds
-               to the given FEC; i. e.
-                       #define CONFIG_FEC1_PHY 4
-               means that the PHY with address 4 is connected to FEC1
-
-               When set to -1, means to probe for first available.
-
-- CONFIG_FEC[12]_PHY_NORXERR
-               The PHY does not have a RXERR line (RMII only).
-               (so program the FEC to ignore it).
-

 - CONFIG_RMII
                Enable RMII mode for all FECs.
                Note that this is a global option, we can't
 - CONFIG_RMII
                Enable RMII mode for all FECs.
                Note that this is a global option, we can't