/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * Authors: * Zhao Yakui */ // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // Module name: Save_AVS_RGBX.asm // // Save packed ARGB 444 frame data block of size 16x16 // // To save 16x16 block (64x16 byte layout for ARGB8888) we need 4 send instructions with 32x8 in each // -------- // | 0 | 1 | // | 2 | 3 | // --------- // the 4 32x8 block send is used // Module name: Save.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Msg payload buffers; upto 4 full-size messages can be written .declare mudMSGPAYLOAD0 Base=r29.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD1 Base=r38.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD2 Base=r47.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD3 Base=r56.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare muwMSGPAYLOAD0 Base=r29.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD1 Base=r38.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD2 Base=r47.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD3 Base=r56.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mubMSGPAYLOAD0 Base=r29.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD1 Base=r38.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD2 Base=r47.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD3 Base=r56.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD4 Base=r32.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD5 Base=r41.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD6 Base=r50.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD7 Base=r59.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub // the r17 register (nTEMP0) is originally defined from "Common.inc" // instead of re-defining a nTEMP0 here, we use "SAVE_RGB" suffix for its naming .declare uwTemp0 Base=r17.0 ElementSize=2 Type=uw //_SAVE_INC_ // At the save module we have all 8 address sub-registers available. // So we will use PING-PONG type of scheme to save the data using // pointers pBUF_CHNL_TOP_8x4 and pBUF_CHNL_BOT_8x4. This will help // reduce dependency. - rT //Internal LAYOUT:(RRGGBBAA) //Assign buffer channel order for Buffer 0123 in the order RGBA a0.3>A, a0.2>B, a0.1>G, a0.0>R // R = 0, G= 4, B = 8, A = 12. mov (4) acc0.0<1>:w 0x62EA:v add (4) acc0.0<1>:w acc0<4;4,1>:w 70:uw shl (4) r22.0<1>:w acc0<4;4,1>:w 5:uw // if channel swap? // This means that it should be BGRA(B is the LSB) or RGBA // the internal format is always RGBA(MSB-A-B-G-R). and.nz.f0.0 null<1>:w r2.3<0;1,0>:uw 0x01:w //wBUFF_CHNL_PTR points to either buffer 0 or buffer 4. //Add appropriate offsets to get pointers for all buffers (1,2,3 or 5). //Offsets are zero for buffer 0 and buffer 4. add (4) a0.0:uw r22.0<4;4,1>:w 0:uw // pointer swap (f0.0) mov (1) uwTemp0<1> a0.0:uw (f0.0) mov (1) a0.0:uw a0.2:uw (f0.0) mov (1) a0.2:uw uwTemp0<0;1,0> shl (1) r27.0<1>:d r7.0<0;1,0>:w 2:w { NoDDClr } // H. block origin need to be quadrupled mov (1) r27.1<1>:d r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin (1st quadrant) mov (1) r27.2<1>:ud 0x7001F:ud { NoDDChk } // Block width and height (64x4) mov (4) a0.4:uw a0.0<4;4,1>:uw mov (8) r28<1>:ud r27<8;8,1>:ud mov (8) r37<1>:ud r27<8;8,1>:ud mov (8) r46<1>:ud r27<8;8,1>:ud mov (8) r55<1>:ud r27<8;8,1>:ud mov (8) r31<1>:ud r27<8;8,1>:ud mov (8) r40<1>:ud r27<8;8,1>:ud mov (8) r49<1>:ud r27<8;8,1>:ud mov (8) r58<1>:ud r27<8;8,1>:ud //for block 1(The right part of buffer 0 and buffer 1) add (1) r37.0<1>:d r27.0<0;1,0>:d 32:d //for block 2(the left part of buffer 2 and buffer 3) add (1) r46.1<1>:d r27.1<0;1,0>:d 8:d //for block 3(the right part of buffer 2 and buffer 3) add (1) r55.1<1>:d r27.1<0;1,0>:d 8:d add (1) r55.0<1>:d r27.0<0;1,0>:d 32:d // write Buf_0 to 1st quarter of four horizontal output blocks // Please note the scattered order of NODDCLR, NODDCHK flags. Since the sub-registers // of destination reg are not updated at one place and hence even flags are scattered. -rT /* for block 0 the left part of buffer 0 and 1 */ mov (8) mubMSGPAYLOAD0(0, 0)<4> r[a0.0, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(0, 1)<4> r[a0.1, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(0, 2)<4> r[a0.2, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD0(1, 0)<4> r[a0.0, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(1, 1)<4> r[a0.1, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(1, 2)<4> r[a0.2, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(0, 0)<4> r[a0.0, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(0, 1)<4> r[a0.1, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(0, 2)<4> r[a0.2, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(1, 0)<4> r[a0.0, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(1, 1)<4> r[a0.1, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(1, 2)<4> r[a0.2, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(1, 3)<4> r2.31:ub add (4) a0.0:uw a0.0<4;4,1>:uw 64:uw mov (8) mubMSGPAYLOAD0(2, 0)<4> r[a0.0, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(2, 1)<4> r[a0.1, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(2, 2)<4> r[a0.2, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD0(3, 0)<4> r[a0.0, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(3, 1)<4> r[a0.1, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(3, 2)<4> r[a0.2, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(3, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(2, 0)<4> r[a0.0, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(2, 1)<4> r[a0.1, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(2, 2)<4> r[a0.2, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(3, 0)<4> r[a0.0, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(3, 1)<4> r[a0.1, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(3, 2)<4> r[a0.2, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(3, 3)<4> r2.31:ub add (4) a0.0:uw a0.4<4;4,1>:uw 512:uw mov (8) mubMSGPAYLOAD0(4, 0)<4> r[a0.0, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(4, 1)<4> r[a0.1, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(4, 2)<4> r[a0.2, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(4, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD0(5, 0)<4> r[a0.0, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(5, 1)<4> r[a0.1, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(5, 2)<4> r[a0.2, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(5, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(4, 0)<4> r[a0.0, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(4, 1)<4> r[a0.1, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(4, 2)<4> r[a0.2, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(4, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(5, 0)<4> r[a0.0, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(5, 1)<4> r[a0.1, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(5, 2)<4> r[a0.2, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(5, 3)<4> r2.31:ub add (4) a0.0:uw a0.0<4;4,1>:uw 64:uw mov (8) mubMSGPAYLOAD0(6, 0)<4> r[a0.0, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(6, 1)<4> r[a0.1, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(6, 2)<4> r[a0.2, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(6, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD0(7, 0)<4> r[a0.0, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(7, 1)<4> r[a0.1, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(7, 2)<4> r[a0.2, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(7, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(6, 0)<4> r[a0.0, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(6, 1)<4> r[a0.1, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(6, 2)<4> r[a0.2, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(6, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(7, 0)<4> r[a0.0, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(7, 1)<4> r[a0.1, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(7, 2)<4> r[a0.2, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(7, 3)<4> r2.31:ub // send buffer 1/2 send (16) null<1>:d r28 0x5 0x120A8018:ud send (16) null<1>:d r37 0x5 0x120A8018:ud //for the block 2 and 3 add (4) a0.0:uw a0.4<4;4,1>:uw 1024:uw mov (8) mubMSGPAYLOAD2(0, 0)<4> r[a0.0, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(0, 1)<4> r[a0.1, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(0, 2)<4> r[a0.2, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD2(1, 0)<4> r[a0.0, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(1, 1)<4> r[a0.1, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(1, 2)<4> r[a0.2, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(0, 0)<4> r[a0.0, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(0, 1)<4> r[a0.1, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(0, 2)<4> r[a0.2, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(1, 0)<4> r[a0.0, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(1, 1)<4> r[a0.1, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(1, 2)<4> r[a0.2, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(1, 3)<4> r2.31:ub add (4) a0.0:uw a0.0<4;4,1>:uw 64:uw mov (8) mubMSGPAYLOAD2(2, 0)<4> r[a0.0, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(2, 1)<4> r[a0.1, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(2, 2)<4> r[a0.2, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD2(3, 0)<4> r[a0.0, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(3, 1)<4> r[a0.1, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(3, 2)<4> r[a0.2, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(3, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(2, 0)<4> r[a0.0, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(2, 1)<4> r[a0.1, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(2, 2)<4> r[a0.2, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(3, 0)<4> r[a0.0, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(3, 1)<4> r[a0.1, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(3, 2)<4> r[a0.2, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(3, 3)<4> r2.31:ub add (4) a0.0:uw a0.4<4;4,1>:uw 1536:uw mov (8) mubMSGPAYLOAD2(4, 0)<4> r[a0.0, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(4, 1)<4> r[a0.1, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(4, 2)<4> r[a0.2, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(4, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD2(5, 0)<4> r[a0.0, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(5, 1)<4> r[a0.1, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(5, 2)<4> r[a0.2, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(5, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(4, 0)<4> r[a0.0, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(4, 1)<4> r[a0.1, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(4, 2)<4> r[a0.2, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(4, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(5, 0)<4> r[a0.0, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(5, 1)<4> r[a0.1, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(5, 2)<4> r[a0.2, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(5, 3)<4> r2.31:ub add (4) a0.0:uw a0.0<4;4,1>:uw 64:uw mov (8) mubMSGPAYLOAD2(6, 0)<4> r[a0.0, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(6, 1)<4> r[a0.1, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(6, 2)<4> r[a0.2, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(6, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD2(7, 0)<4> r[a0.0, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(7, 1)<4> r[a0.1, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(7, 2)<4> r[a0.2, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(7, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(6, 0)<4> r[a0.0, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(6, 1)<4> r[a0.1, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(6, 2)<4> r[a0.2, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(6, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(7, 0)<4> r[a0.0, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(7, 1)<4> r[a0.1, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(7, 2)<4> r[a0.2, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(7, 3)<4> r2.31:ub // send buffer 3/4 send (16) null<1>:d r46 0x5 0x120A8018:ud send (16) null<1>:d r55 0x5 0x120A8018:ud