M32R Dependent Features
***********************

M32R Options
============

The Renease M32R version of AS has a few machine dependent options:

-m32rx
     AS can assemble code for several different members of the Renesas M32R family.  Normally the default is to assemble code for the M32R microprocessor.  This option may be used to change the default to the M32RX microprocessor, which adds some more instructions to the basic M32R instruction set, and some additional parameters to some of the original instructions.

-m32r2
     This option changes the target processor to the the M32R2 microprocessor.

-m32r
     This option can be used to restore the assembler's default behaviour of assembling for the M32R microprocessor.  This can be useful if the default has been changed by a previous command line option.

-little
     This option tells the assembler to produce little-endian code and data.  The default is dependent upon how the toolchain was configured.

-EL
     This is a synonym for -little.

-big
     This option tells the assembler to produce big-endian code and data.

-EB
     This is a synonum for -big.

-KPIC
     This option specifies that the output of the assembler should be marked as position-independent code (PIC).

-parallel
     This option tells the assembler to attempts to combine two sequential instructions into a single, parallel instruction, where it is legal to do so.

-no-parallel
     This option disables a previously enabled -parallel option.

-no-bitinst
     This option disables the support for the extended bit-field instructions provided by the M32R2.  If this support needs to be re-enabled the -bitinst switch can be used to restore it.

-O
     This option tells the assembler to attempt to optimize the instructions that it produces.  This includes filling delay slots and converting sequential instructions into parallel ones.  This option implies -parallel.

-warn-explicit-parallel-conflicts
     Instructs AS to produce warning messages when questionable parallel instructions are encountered.  This option is enabled by default, but GCC disables it when it invokes AS directly.  Questionable instructions are those whose behaviour would be different if they were executed sequentially.  For example the code fragment mv r1, r2 || mv r3, r1 produces a different result from mv r1, r2 \n mv r3, r1 since the former moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1 and r3.

-Wp
     This is a shorter synonym for the -warn-explicit-parallel-conflicts option.

-no-warn-explicit-parallel-conflicts
     Instructs AS not to produce warning messages when questionable parallel instructions are encountered.

-Wnp
     This is a shorter synonym for the -no-warn-explicit-parallel-conflicts option.

-ignore-parallel-conflicts
     This option tells the assembler's to stop checking parallel instructions for constraint violations.  This ability is provided for hardware vendors testing chip designs and should not be used under normal circumstances.

-no-ignore-parallel-conflicts
     This option restores the assembler's default behaviour of checking parallel instructions to detect constraint violations.

-Ip
     This is a shorter synonym for the -ignore-parallel-conflicts option.

-nIp
     This is a shorter synonym for the -no-ignore-parallel-conflicts option.

-warn-unmatched-high
     This option tells the assembler to produce a warning message if a .high pseudo op is encountered without a matching .low pseudo op.  The presence of such an unmatched pseudo op usually indicates a programming error.

-no-warn-unmatched-high
     Disables a previously enabled -warn-unmatched-high option.

-Wuh
     This is a shorter synonym for the -warn-unmatched-high option.

-Wnuh
     This is a shorter synonym for the -no-warn-unmatched-high option.

M32R Directives
===============

The Renease M32R version of AS has a few architecture specific directives:

low EXPRESSION
     The low directive computes the value of its expression and places the lower 16-bits of the result into the immediate-field of the instruction.  For example:

             or3   r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678
             add3, r0, r0, #low(fred)   ; compute r0 = r0 + low 16-bits of address of fred

high EXPRESSION
     The high directive computes the value of its expression and places the upper 16-bits of the result into the immediate-field of the instruction.  For example:

             seth  r0, #high(0x12345678) ; compute r0 = 0x12340000
             seth, r0, #high(fred)       ; compute r0 = upper 16-bits of address of fred

shigh EXPRESSION
     The shigh directive is very similar to the high directive.  It also computes the value of its expression and places the upper 16-bits of the result into the immediate-field of the instruction.  The difference is that shigh also checks to see if the lower 16-bits could be interpreted as a signed number, and if so it assumes that a borrow will occur from the upper-16 bits.  To compensate for this the shigh directive pre-biases the upper 16 bit value by adding one to it.  For example:

     For example:

             seth  r0, #shigh(0x12345678) ; compute r0 = 0x12340000
             seth  r0, #shigh(0x00008000) ; compute r0 = 0x00010000

     In the second example the lower 16-bits are 0x8000.  If these are treated as a signed value and sign extended to 32-bits then the value becomes 0xffff8000.  If this value is then added to 0x00010000 then the result is 0x00008000.

     This behaviour is to allow for the different semantics of the or3 and add3 instructions.  The or3 instruction treats its 16-bit immediate argument as unsigned whereas the add3 treats its 16-bit immediate as a signed value.  So for example:

             seth  r0, #shigh(0x00008000)
             add3  r0, r0, #low(0x00008000)

     Produces the correct result in r0, whereas:

             seth  r0, #shigh(0x00008000)
             or3   r0, r0, #low(0x00008000)

     Stores 0xffff8000 into r0.

     Note - the shigh directive does not know where in the assembly source code the lower 16-bits of the value are going set, so it cannot check to make sure that an or3 instruction is being used rather than an add3 instruction.  It is up to the programmer to make sure that correct directives are used.

.m32r
     The directive performs a similar thing as the -m32r command line option.  It tells the assembler to only accept M32R instructions from now on.  An instructions from later M32R architectures are refused.

.m32rx
     The directive performs a similar thing as the -m32rx command line option.  It tells the assembler to start accepting the extra instructions in the M32RX ISA as well as the ordinary M32R ISA.

.m32r2
     The directive performs a similar thing as the -m32r2 command line option.  It tells the assembler to start accepting the extra instructions in the M32R2 ISA as well as the ordinary M32R ISA.

.little
     The directive performs a similar thing as the -little command line option.  It tells the assembler to start producing little-endian code and data.  This option should be used with care as producing mixed-endian binary files is fraught with danger.

.big
     The directive performs a similar thing as the -big command line option.  It tells the assembler to start producing big-endian code and data.  This option should be used with care as producing mixed-endian binary files is fraught with danger.

M32R Warnings
=============

There are several warning and error messages that can be produced by AS which are specific to the M32R:

output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?
     This message is only produced if warnings for explicit parallel conflicts have been enabled.  It indicates that the assembler has encountered a parallel instruction in which the destination register of the left hand instruction is used as an input register in the right hand instruction.  For example in this code fragment mv r1, r2 || neg r3, r1 register r1 is the destination of the move instruction and the input to the neg instruction.

output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?
     This message is only produced if warnings for explicit parallel conflicts have been enabled.  It indicates that the assembler has encountered a parallel instruction in which the destination register of the right hand instruction is used as an input register in the left hand instruction.  For example in this code fragment mv r1, r2 || neg r2, r3 register r2 is the destination of the neg instruction and the input to the move instruction.

instruction ... is for the M32RX only
     This message is produced when the assembler encounters an instruction which is only supported by the M32Rx processor, and the -m32rx command line flag has not been specified to allow assembly of such instructions.

unknown instruction ...
     This message is produced when the assembler encounters an instruction which it does not recognize.

only the NOP instruction can be issued in parallel on the m32r
     This message is produced when the assembler encounters a parallel instruction which does not involve a NOP instruction and the -m32rx command line flag has not been specified.  Only the M32Rx processor is able to execute two instructions in parallel.

instruction ... cannot be executed in parallel.
     This message is produced when the assembler encounters a parallel instruction which is made up of one or two instructions which cannot be executed in parallel.

Instructions share the same execution pipeline
     This message is produced when the assembler encounters a parallel instruction whoes components both use the same execution pipeline.

Instructions write to the same destination register.
     This message is produced when the assembler encounters a parallel
     instruction where both components attempt to modify the same register.
     For example these code fragments will produce this message:
     mv r1, r2 || neg r1, r3
     jl r0 || mv r14, r1
     st r2, @-r1 || mv r1, r3
     mv r1, r2 || ld r0, @r1+
     cmp r1, r2 || addx r3, r4 (Both write to the condition bit)