24 #ifndef ARM_COMPUTE_TEST_HWC 25 #define ARM_COMPUTE_TEST_HWC 36 #include <sys/ioctl.h> 40 #ifndef DOXYGEN_SKIP_THIS 42 #if defined(ANDROID) || defined(__ANDROID__) 44 #define MALI_IOR(a, b, c) _IOR_BAD(a, b, c) 45 #define MALI_IOW(a, b, c) _IOW_BAD(a, b, c) 47 #define MALI_IOR(a, b, c) _IOR(a, b, c) 48 #define MALI_IOW(a, b, c) _IOW(a, b, c) 51 namespace mali_userspace
60 #define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 3 61 #define BASE_MAX_COHERENT_GROUPS 16 63 struct mali_base_gpu_core_props
66 uint16_t version_status;
67 uint16_t minor_revision;
68 uint16_t major_revision;
70 uint32_t gpu_speed_mhz;
71 uint32_t gpu_freq_khz_max;
72 uint32_t gpu_freq_khz_min;
73 uint32_t log2_program_counter_size;
74 uint32_t texture_features[BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS];
75 uint64_t gpu_available_memory_size;
78 struct mali_base_gpu_l2_cache_props
80 uint8_t log2_line_size;
81 uint8_t log2_cache_size;
82 uint8_t num_l2_slices;
86 struct mali_base_gpu_tiler_props
88 uint32_t bin_size_bytes;
89 uint32_t max_active_levels;
92 struct mali_base_gpu_thread_props
95 uint32_t max_workgroup_size;
96 uint32_t max_barrier_size;
97 uint16_t max_registers;
98 uint8_t max_task_queue;
99 uint8_t max_thread_group_split;
104 struct mali_base_gpu_coherent_group
111 struct mali_base_gpu_coherent_group_info
114 uint32_t num_core_groups;
117 mali_base_gpu_coherent_group group[BASE_MAX_COHERENT_GROUPS];
120 #define GPU_MAX_JOB_SLOTS 16 121 struct gpu_raw_gpu_props
123 uint64_t shader_present;
124 uint64_t tiler_present;
128 uint32_t l2_features;
129 uint32_t suspend_size;
130 uint32_t mem_features;
131 uint32_t mmu_features;
136 uint32_t js_features[GPU_MAX_JOB_SLOTS];
137 uint32_t tiler_features;
138 uint32_t texture_features[3];
142 uint32_t thread_max_threads;
143 uint32_t thread_max_workgroup_size;
144 uint32_t thread_max_barrier_size;
145 uint32_t thread_features;
147 uint32_t coherency_mode;
150 struct mali_base_gpu_props
152 mali_base_gpu_core_props core_props;
153 mali_base_gpu_l2_cache_props l2_props;
155 mali_base_gpu_tiler_props tiler_props;
156 mali_base_gpu_thread_props thread_props;
157 gpu_raw_gpu_props raw_props;
158 mali_base_gpu_coherent_group_info coherency_info;
161 struct kbase_uk_gpuprops
164 mali_base_gpu_props props;
167 #define KBASE_GPUPROP_VALUE_SIZE_U8 (0x0) 168 #define KBASE_GPUPROP_VALUE_SIZE_U16 (0x1) 169 #define KBASE_GPUPROP_VALUE_SIZE_U32 (0x2) 170 #define KBASE_GPUPROP_VALUE_SIZE_U64 (0x3) 172 #define KBASE_GPUPROP_PRODUCT_ID 1 173 #define KBASE_GPUPROP_MINOR_REVISION 3 174 #define KBASE_GPUPROP_MAJOR_REVISION 4 176 #define KBASE_GPUPROP_COHERENCY_NUM_GROUPS 61 177 #define KBASE_GPUPROP_COHERENCY_NUM_CORE_GROUPS 62 178 #define KBASE_GPUPROP_COHERENCY_GROUP_0 64 179 #define KBASE_GPUPROP_COHERENCY_GROUP_1 65 180 #define KBASE_GPUPROP_COHERENCY_GROUP_2 66 181 #define KBASE_GPUPROP_COHERENCY_GROUP_3 67 182 #define KBASE_GPUPROP_COHERENCY_GROUP_4 68 183 #define KBASE_GPUPROP_COHERENCY_GROUP_5 69 184 #define KBASE_GPUPROP_COHERENCY_GROUP_6 70 185 #define KBASE_GPUPROP_COHERENCY_GROUP_7 71 186 #define KBASE_GPUPROP_COHERENCY_GROUP_8 72 187 #define KBASE_GPUPROP_COHERENCY_GROUP_9 73 188 #define KBASE_GPUPROP_COHERENCY_GROUP_10 74 189 #define KBASE_GPUPROP_COHERENCY_GROUP_11 75 190 #define KBASE_GPUPROP_COHERENCY_GROUP_12 76 191 #define KBASE_GPUPROP_COHERENCY_GROUP_13 77 192 #define KBASE_GPUPROP_COHERENCY_GROUP_14 78 193 #define KBASE_GPUPROP_COHERENCY_GROUP_15 79 198 uint16_t minor_revision;
199 uint16_t major_revision;
201 uint32_t num_core_groups;
210 } gpu_property_mapping[] =
212 #define PROP(name, member) \ 214 KBASE_GPUPROP_##name, offsetof(struct gpu_props, member), \ 215 sizeof(((struct gpu_props *)0)->member) \ 217 #define PROP2(name, member, off) \ 219 KBASE_GPUPROP_##name, offsetof(struct gpu_props, member) + off, \ 220 sizeof(((struct gpu_props *)0)->member) \ 222 PROP(PRODUCT_ID, product_id),
223 PROP(MINOR_REVISION, minor_revision),
224 PROP(MAJOR_REVISION, major_revision),
225 PROP(COHERENCY_NUM_GROUPS, num_groups),
226 PROP(COHERENCY_NUM_CORE_GROUPS, num_core_groups),
237 PROP2(COHERENCY_GROUP_10,
core_mask, 10),
238 PROP2(COHERENCY_GROUP_11,
core_mask, 11),
239 PROP2(COHERENCY_GROUP_12,
core_mask, 12),
240 PROP2(COHERENCY_GROUP_13,
core_mask, 13),
241 PROP2(COHERENCY_GROUP_14,
core_mask, 14),
242 PROP2(COHERENCY_GROUP_15,
core_mask, 15),
248 struct kbase_hwcnt_reader_metadata
250 uint64_t timestamp = 0;
251 uint32_t event_id = 0;
252 uint32_t buffer_idx = 0;
258 union kbase_uk_hwcnt_header
269 struct kbase_uk_hwcnt_reader_version_check_args
271 union kbase_uk_hwcnt_header header;
281 uint32_t compat_value;
285 struct kbase_ioctl_get_gpuprops
287 kbase_pointer buffer;
292 #define KBASE_IOCTL_TYPE 0x80 293 #define KBASE_IOCTL_GET_GPUPROPS MALI_IOW(KBASE_IOCTL_TYPE, 3, struct kbase_ioctl_get_gpuprops) 296 struct kbase_uk_hwcnt_reader_set_flags
298 union kbase_uk_hwcnt_header header;
300 uint32_t create_flags;
305 struct kbase_uk_hwcnt_reader_setup
307 union kbase_uk_hwcnt_header header;
310 uint32_t buffer_count;
320 static const uint32_t HWCNT_READER_API = 1;
322 struct uku_version_check_args
332 UKP_FUNC_ID_CHECK_VERSION = 0,
334 LINUX_UK_BASE_MAGIC = 0x80,
335 BASE_CONTEXT_CREATE_KERNEL_FLAGS = 0x2,
336 KBASE_FUNC_HWCNT_UK_FUNC_ID = 512,
337 KBASE_FUNC_GPU_PROPS_REG_DUMP = KBASE_FUNC_HWCNT_UK_FUNC_ID + 14,
338 KBASE_FUNC_HWCNT_READER_SETUP = KBASE_FUNC_HWCNT_UK_FUNC_ID + 36,
339 KBASE_FUNC_HWCNT_DUMP = KBASE_FUNC_HWCNT_UK_FUNC_ID + 11,
340 KBASE_FUNC_HWCNT_CLEAR = KBASE_FUNC_HWCNT_UK_FUNC_ID + 12,
341 KBASE_FUNC_SET_FLAGS = KBASE_FUNC_HWCNT_UK_FUNC_ID + 18,
344 KBASE_HWCNT_READER = 0xBE,
345 KBASE_HWCNT_READER_GET_HWVER = MALI_IOR(KBASE_HWCNT_READER, 0x00, uint32_t),
346 KBASE_HWCNT_READER_GET_BUFFER_SIZE = MALI_IOR(KBASE_HWCNT_READER, 0x01, uint32_t),
347 KBASE_HWCNT_READER_DUMP = MALI_IOW(KBASE_HWCNT_READER, 0x10, uint32_t),
348 KBASE_HWCNT_READER_CLEAR = MALI_IOW(KBASE_HWCNT_READER, 0x11, uint32_t),
349 KBASE_HWCNT_READER_GET_BUFFER = MALI_IOR(KBASE_HWCNT_READER, 0x20,
struct kbase_hwcnt_reader_metadata),
350 KBASE_HWCNT_READER_PUT_BUFFER = MALI_IOW(KBASE_HWCNT_READER, 0x21,
struct kbase_hwcnt_reader_metadata),
351 KBASE_HWCNT_READER_SET_INTERVAL = MALI_IOW(KBASE_HWCNT_READER, 0x30, uint32_t),
352 KBASE_HWCNT_READER_ENABLE_EVENT = MALI_IOW(KBASE_HWCNT_READER, 0x40, uint32_t),
353 KBASE_HWCNT_READER_DISABLE_EVENT = MALI_IOW(KBASE_HWCNT_READER, 0x41, uint32_t),
354 KBASE_HWCNT_READER_GET_API_VERSION = MALI_IOW(KBASE_HWCNT_READER, 0xFF, uint32_t)
363 PIPE_DESCRIPTOR_COUNT
368 POLL_DESCRIPTOR_SIGNAL,
369 POLL_DESCRIPTOR_HWCNT_READER,
371 POLL_DESCRIPTOR_COUNT
375 typedef char poll_data_t;
378 template <
typename T>
379 static inline int mali_ioctl(
int fd, T &arg)
381 auto *hdr = &arg.header;
382 const int cmd = _IOC(_IOC_READ | _IOC_WRITE, LINUX_UK_BASE_MAGIC, hdr->id,
sizeof(T));
384 if(ioctl(fd, cmd, &arg))
__global uchar * offset(const Image *img, int x, int y)
Get the pointer position of a Image.