// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright (C) 2022 StarFive Technology Co., Ltd. * Copyright (C) 2022 Hal Feng */ /dts-v1/; #include "jh7110_clk.dtsi" #include #include #include #include / { compatible = "starfive,jh7110"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "sifive,u74-mc", "riscv"; reg = <0>; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <8192>; d-tlb-sets = <1>; d-tlb-size = <40>; device_type = "cpu"; i-cache-block-size = <64>; i-cache-sets = <64>; i-cache-size = <16384>; i-tlb-sets = <1>; i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; riscv,isa = "rv64imac"; tlb-split; status = "disabled"; cpu0intctrl: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; cpu1: cpu@1 { compatible = "sifive,u74-mc", "riscv"; reg = <1>; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; d-tlb-sets = <1>; d-tlb-size = <40>; device_type = "cpu"; i-cache-block-size = <64>; i-cache-sets = <64>; i-cache-size = <32768>; i-tlb-sets = <1>; i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; riscv,isa = "rv64imafdc"; tlb-split; status = "okay"; cpu1intctrl: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; cpu2: cpu@2 { compatible = "sifive,u74-mc", "riscv"; reg = <2>; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; d-tlb-sets = <1>; d-tlb-size = <40>; device_type = "cpu"; i-cache-block-size = <64>; i-cache-sets = <64>; i-cache-size = <32768>; i-tlb-sets = <1>; i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; riscv,isa = "rv64imafdc"; tlb-split; status = "okay"; cpu2intctrl: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; cpu3: cpu@3 { compatible = "sifive,u74-mc", "riscv"; reg = <3>; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; d-tlb-sets = <1>; d-tlb-size = <40>; device_type = "cpu"; i-cache-block-size = <64>; i-cache-sets = <64>; i-cache-size = <32768>; i-tlb-sets = <1>; i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; riscv,isa = "rv64imafdc"; tlb-split; status = "okay"; cpu3intctrl: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; cpu4: cpu@4 { compatible = "sifive,u74-mc", "riscv"; reg = <4>; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; d-tlb-sets = <1>; d-tlb-size = <40>; device_type = "cpu"; i-cache-block-size = <64>; i-cache-sets = <64>; i-cache-size = <32768>; i-tlb-sets = <1>; i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; riscv,isa = "rv64imafdc"; tlb-split; status = "okay"; cpu4intctrl: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; }; soc: soc { compatible = "simple-bus"; interrupt-parent = <&plic>; #address-cells = <2>; #size-cells = <2>; #clock-cells = <1>; ranges; cachectrl: cache-controller@2010000 { compatible = "sifive,fu740-c000-ccache", "cache"; reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>; reg-names = "control", "sideband"; interrupts = <1 3 4 2>; cache-block-size = <64>; cache-level = <2>; cache-sets = <2048>; cache-size = <2097152>; cache-unified; }; aon_syscon: aon_syscon@17010000 { compatible = "syscon"; reg = <0x0 0x17010000 0x0 0x1000>; }; stg_syscon: stg_syscon@10240000 { compatible = "syscon"; reg = <0x0 0x10240000 0x0 0x1000>; }; sys_syscon: sys_syscon@13030000 { compatible = "syscon"; reg = <0x0 0x13030000 0x0 0x1000>; }; clint: clint@2000000 { compatible = "riscv,clint0"; reg = <0x0 0x2000000 0x0 0x10000>; reg-names = "control"; interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7 &cpu1intctrl 3 &cpu1intctrl 7 &cpu2intctrl 3 &cpu2intctrl 7 &cpu3intctrl 3 &cpu3intctrl 7 &cpu4intctrl 3 &cpu4intctrl 7>; #interrupt-cells = <1>; }; plic: plic@c000000 { compatible = "riscv,plic0"; reg = <0x0 0xc000000 0x0 0x4000000>; reg-names = "control"; interrupts-extended = <&cpu0intctrl 11 &cpu1intctrl 11 &cpu1intctrl 9 &cpu2intctrl 11 &cpu2intctrl 9 &cpu3intctrl 11 &cpu3intctrl 9 &cpu4intctrl 11 &cpu4intctrl 9>; interrupt-controller; #interrupt-cells = <1>; riscv,max-priority = <7>; riscv,ndev = <136>; }; clkgen: clock-controller { compatible = "starfive,jh7110-clkgen"; reg = <0x0 0x13020000 0x0 0x10000>, <0x0 0x10230000 0x0 0x10000>, <0x0 0x17000000 0x0 0x10000>; reg-names = "sys", "stg", "aon"; clocks = <&osc>, <&gmac1_rmii_refin>, <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, <&tdm_ext>, <&mclk_ext>, <&jtag_tck_inner>, <&bist_apb>, <&stg_apb>, <&clk_rtc>, <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>; clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", "i2srx_bclk_ext", "i2srx_lrck_ext", "tdm_ext", "mclk_ext", "jtag_tck_inner", "bist_apb", "stg_apb", "clk_rtc", "gmac0_rmii_refin", "gmac0_rgmii_rxin"; #clock-cells = <1>; status = "okay"; }; clkvout: clock-controller@295C0000 { compatible = "starfive,jh7110-clk-vout"; reg = <0x0 0x295C0000 0x0 0x10000>; reg-names = "vout"; clocks = <&hdmitx0_pixelclk>, <&mipitx_dphy_rxesc>, <&mipitx_dphy_txbytehs>; clock-names = "hdmitx0_pixelclk", "mipitx_dphy_rxesc", "mipitx_dphy_txbytehs"; #clock-cells = <1>; status = "okay"; }; clkisp: clock-controller@19810000 { compatible = "starfive,jh7110-clk-isp"; reg = <0x0 0x19810000 0x0 0x10000>; reg-names = "isp"; #clock-cells = <1>; clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>, <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>, <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>; clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp", "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x", "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi"; resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>, <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>; reset-names = "rst_isp_top_n", "rst_isp_top_axi"; status = "disabled"; }; qspi: qspi@13010000 { compatible = "cadence,qspi","cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x13010000 0x0 0x10000 0x0 0x21000000 0x0 0x400000>; clocks = <&clkgen JH7110_QSPI_CLK_REF>; clock-names = "clk_ref"; resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>, <&rstgen RSTN_U0_CDNS_QSPI_AHB>, <&rstgen RSTN_U0_CDNS_QSPI_REF>; resets-names = "rst_apb", "rst_ahb", "rst_ref"; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; spi-max-frequency = <250000000>; nor_flash: nor-flash@0 { compatible = "jedec,spi-nor"; reg=<0>; spi-max-frequency = <100000000>; cdns,tshsl-ns = <1>; cdns,tsd2d-ns = <1>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; }; }; otp: otp@17050000 { compatible = "starfive,jh7110-otp"; reg = <0x0 0x17050000 0x0 0x10000>; clock-frequency = <4000000>; clocks = <&clkgen JH7110_OTPC_CLK_APB>; clock-names = "apb"; }; USB30: usb@10100000 { compatible = "cdns,usb3"; reg = <0x0 0x10100000 0x0 0x10000>, <0x0 0x10110000 0x0 0x10000>, <0x0 0x10120000 0x0 0x10000>; reg-names = "otg", "xhci", "dev"; phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy"; clocks = <&clkgen JH7110_USB0_CLK_APP_125>, <&clkgen JH7110_USB0_CLK_LPM>, <&clkgen JH7110_USB0_CLK_STB>, <&clkgen JH7110_USB0_CLK_USB_APB>, <&clkgen JH7110_USB0_CLK_AXI>, <&clkgen JH7110_USB0_CLK_UTMI_APB>; clock-names = "app","lpm","stb","apb","axi","utmi"; resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>, <&rstgen RSTN_U0_CDN_USB_APB>, <&rstgen RSTN_U0_CDN_USB_AXI>, <&rstgen RSTN_U0_CDN_USB_UTMI_APB>; reset-names = "rst_pwrup","rst_apb","rst_axi","rst_utmi"; }; timer: timer@13050000 { compatible = "starfive,si5-timers"; reg = <0x0 0x13050000 0x0 0x10000>; interrupts = <69>, <70>, <71> ,<72>; interrupt-names = "timer0", "timer1", "timer2", "timer3"; clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>, <&clkgen JH7110_TIMER_CLK_TIMER1>, <&clkgen JH7110_TIMER_CLK_TIMER2>, <&clkgen JH7110_TIMER_CLK_TIMER3>, <&clkgen JH7110_TIMER_CLK_APB>; clock-names = "timer0", "timer1", "timer2", "timer3", "apb_clk"; clock-frequency = <2000000>; status = "okay"; }; wdog: wdog@13070000 { compatible = "starfive,dskit-wdt"; reg = <0x0 0x13070000 0x0 0x10000>; interrupts = <68>; interrupt-names = "wdog"; clock-frequency = <2000000>; clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>, <&clkgen JH7110_DSKIT_WDT_CLK_APB>; clock-names = "core_clk", "apb_clk"; resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>, <&rstgen RSTN_U0_DSKIT_WDT_CORE>; reset-names = "rst_apb", "rst_core"; timeout-sec = <15>; status = "okay"; }; rtc: rtc@17040000 { compatible = "starfive,rtc_hms"; reg = <0x0 0x17040000 0x0 0x10000>; interrupts = <10>, <11>, <12>; interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc"; clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>, <&clkgen JH7110_RTC_HMS_CLK_CAL>; clock-names = "pclk", "cal_clk"; resets = <&rstgen RSTN_U0_RTC_HMS_APB>, <&rstgen RSTN_U0_RTC_HMS_CAL>, <&rstgen RSTN_U0_RTC_HMS_OSC32K>; reset-names = "rst_apb", "rst_cal", "rst_osc"; rtc,cal-clock-freq = <1000000>; status = "okay"; }; pmu: pmu@17030000 { compatible = "starfive,jh7110-pmu"; reg = <0x0 0x17030000 0x0 0x10000>; interrupts = <111>; status = "okay"; }; uart0: serial@10000000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x10000000 0x0 0x10000>; reg-io-width = <4>; reg-shift = <2>; clocks = <&clkgen JH7110_UART0_CLK_CORE>, <&clkgen JH7110_UART0_CLK_APB>; clock-names = "baudclk", "apb_pclk"; resets = <&rstgen RSTN_U0_DW_UART_APB>; interrupts = <32>; status = "disabled"; }; uart1: serial@10010000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x10010000 0x0 0x10000>; reg-io-width = <4>; reg-shift = <2>; clocks = <&clkgen JH7110_UART1_CLK_CORE>, <&clkgen JH7110_UART1_CLK_APB>; clock-names = "baudclk", "apb_pclk"; resets = <&rstgen RSTN_U1_DW_UART_APB>; interrupts = <33>; status = "disabled"; }; uart2: serial@10020000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x10020000 0x0 0x10000>; reg-io-width = <4>; reg-shift = <2>; clocks = <&clkgen JH7110_UART2_CLK_CORE>, <&clkgen JH7110_UART2_CLK_APB>; clock-names = "baudclk", "apb_pclk"; resets = <&rstgen RSTN_U2_DW_UART_APB>; interrupts = <34>; status = "disabled"; }; uart3: serial@12000000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x12000000 0x0 0x10000>; reg-io-width = <4>; reg-shift = <2>; clocks = <&clkgen JH7110_UART3_CLK_CORE>, <&clkgen JH7110_UART3_CLK_APB>; clock-names = "baudclk", "apb_pclk"; resets = <&rstgen RSTN_U3_DW_UART_APB>; interrupts = <45>; status = "disabled"; }; uart4: serial@12010000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x12010000 0x0 0x10000>; reg-io-width = <4>; reg-shift = <2>; clocks = <&clkgen JH7110_UART4_CLK_CORE>, <&clkgen JH7110_UART4_CLK_APB>; clock-names = "baudclk", "apb_pclk"; resets = <&rstgen RSTN_U4_DW_UART_APB>; interrupts = <46>; status = "disabled"; }; uart5: serial@12020000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x12020000 0x0 0x10000>; reg-io-width = <4>; reg-shift = <2>; clocks = <&clkgen JH7110_UART5_CLK_CORE>, <&clkgen JH7110_UART5_CLK_APB>; clock-names = "baudclk", "apb_pclk"; resets = <&rstgen RSTN_U5_DW_UART_APB>; interrupts = <47>; status = "disabled"; }; dma: dma-controller@16050000 { compatible = "starfive,axi-dma"; reg = <0x0 0x16050000 0x0 0x10000>; clocks = <&clkgen JH7110_DMA1P_CLK_AXI>, <&clkgen JH7110_DMA1P_CLK_AHB>; clock-names = "core-clk", "cfgr-clk"; resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>, <&rstgen RSTN_U0_DW_DMA1P_AHB>; reset-names = "rst_axi", "rst_ahb"; interrupts = <73>; #dma-cells = <2>; dma-channels = <4>; snps,dma-masters = <1>; snps,data-width = <3>; snps,num-hs-if = <56>; snps,block-size = <65536 65536 65536 65536>; snps,priority = <0 1 2 3>; snps,axi-max-burst-len = <16>; status = "disabled"; }; gpio: gpio@13040000 { compatible = "starfive_jh7110-sys-pinctrl"; reg = <0x0 0x13040000 0x0 0x10000>; reg-names = "control"; interrupts = <91>; interrupt-controller; #gpio-cells = <2>; ngpios = <64>; status = "okay"; }; gpioa: gpio@17020000 { compatible = "starfive_jh7110-aon-pinctrl"; reg = <0x0 0x17020000 0x0 0x10000>; reg-names = "control"; interrupts = <90>; interrupt-controller; #gpio-cells = <2>; ngpios = <4>; status = "okay"; }; trng: trng@1600C000 { compatible = "starfive,trng"; reg = <0x0 0x1600C000 0x0 0x4000>; clocks = <&clkgen JH7110_SEC_HCLK>, <&clkgen JH7110_SEC_MISCAHB_CLK>; clock-names = "hclk", "miscahb_clk"; resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>; interrupts = <30>; status = "disabled"; }; sec_dma: sec_dma@16008000 { /*compatible = "arm,pl080", "arm,primecell";*/ compatible = "starfive,pl080"; reg = <0x0 0x16008000 0x0 0x4000>; reg-names = "sec_dma"; interrupt-parent = <&plic>; interrupts = <29>; clocks = <&oscclk>; clock-names = "apb_pclk"; lli-bus-interface-ahb1; /*lli-bus-interface-ahb2;*/ mem-bus-interface-ahb1; /*mem-bus-interface-ahb2;*/ memcpy-burst-size = <256>; memcpy-bus-width = <32>; #dma-cells = <2>; /*status = "disabled";*/ }; crypto: crypto@16000000 { compatible = "starfive,jh7110-sec"; reg = <0x0 0x16000000 0x0 0x4000>, <0x0 0x16008000 0x0 0x4000>; reg-names = "secreg","secdma"; interrupts = <28>, <29>; interrupt-names = "secirq", "dmairq"; clocks = <&clkgen JH7110_SEC_HCLK>, <&clkgen JH7110_SEC_MISCAHB_CLK>; clock-names = "sec_hclk","sec_ahb"; resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>; reset-names = "sec_hre"; status = "disabled"; }; i2c6: i2c@12060000 { compatible = "snps,designware-i2c"; reg = <0x0 0x12060000 0x0 0x10000>; clocks = <&clkgen JH7110_I2C6_CLK_CORE>, <&clkgen JH7110_I2C6_CLK_APB>; clock-names = "ref", "pclk"; resets = <&rstgen RSTN_U6_DW_I2C_APB>; interrupts = <51>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c0: i2c@10030000 { compatible = "snps,designware-i2c"; reg = <0x0 0x10030000 0x0 0x10000>; clocks = <&clkgen JH7110_I2C0_CLK_CORE>, <&clkgen JH7110_I2C0_CLK_APB>; clock-names = "ref", "pclk"; resets = <&rstgen RSTN_U0_DW_I2C_APB>; interrupts = <35>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c1: i2c@10040000 { compatible = "snps,designware-i2c"; reg = <0x0 0x10040000 0x0 0x10000>; clocks = <&clkgen JH7110_I2C1_CLK_CORE>, <&clkgen JH7110_I2C1_CLK_APB>; clock-names = "ref", "pclk"; resets = <&rstgen RSTN_U1_DW_I2C_APB>; interrupts = <36>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; /* unremovable emmc as mmcblk0 */ sdio0: sdio0@16010000 { compatible = "snps,dw-mshc"; reg = <0x0 0x16010000 0x0 0x10000>; clocks = <&clkgen JH7110_SDIO0_CLK_AHB>, <&clkgen JH7110_SDIO0_CLK_SDCARD>; clock-names = "biu","ciu"; resets = <&rstgen RSTN_U0_DW_SDIO_AHB>; reset-names = "reset"; interrupts = <74>; fifo-depth = <32>; fifo-watermark-aligned; data-addr = <0>; status = "disabled"; }; sdio1: sdio1@16020000 { compatible = "snps,dw-mshc"; reg = <0x0 0x16020000 0x0 0x10000>; clocks = <&clkgen JH7110_SDIO1_CLK_AHB>, <&clkgen JH7110_SDIO1_CLK_SDCARD>; clock-names = "biu","ciu"; resets = <&rstgen RSTN_U1_DW_SDIO_AHB>; reset-names = "reset"; interrupts = <75>; fifo-depth = <32>; fifo-watermark-aligned; data-addr = <0>; status = "disabled"; }; vin_sysctl: vin_sysctl@19800000 { compatible = "starfive,stf-vin"; reg = <0x0 0x19800000 0x0 0x10000>, <0x0 0x19810000 0x0 0x10000>, <0x0 0x19820000 0x0 0x10000>, <0x0 0x19830000 0x0 0x10000>, <0x0 0x19840000 0x0 0x10000>, <0x0 0x19870000 0x0 0x30000>, <0x0 0x198a0000 0x0 0x30000>, <0x0 0x11840000 0x0 0x10000>, <0x0 0x17030000 0x0 0x10000>, <0x0 0x13020000 0x0 0x10000>; reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl", "isp0", "isp1", "trst", "pmu", "syscrg"; clocks = <&clkisp JH7110_DOM4_APB_FUNC>, <&clkisp JH7110_U0_VIN_PCLK>, <&clkisp JH7110_U0_VIN_SYS_CLK>, <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>, <&clkisp JH7110_DVP_INV>, <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>, <&clkisp JH7110_MIPI_RX0_PXL>, <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>, <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>, <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>, <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>; clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk", "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr", "clk_mipi_rx0_pxl", "clk_pixel_clk_if0", "clk_pixel_clk_if1", "clk_pixel_clk_if2", "clk_pixel_clk_if3"; resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>, <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>, <&rstgen RSTN_U0_VIN_N_PCLK>, <&rstgen RSTN_U0_VIN_N_SYS_CLK>, <&rstgen RSTN_U0_VIN_P_AXIRD>, <&rstgen RSTN_U0_VIN_P_AXIWR>, <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>, <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>, <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>, <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>; reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk", "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0", "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3"; interrupts = <92 87 86>; status = "disabled"; }; jpu: jpu@11900000 { compatible = "starfive,jpu"; reg = <0x0 0x13090000 0x0 0x300>; interrupts = <14>; clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>, <&clkgen JH7110_CODAJ12_CLK_CORE>, <&clkgen JH7110_CODAJ12_CLK_APB>; clock-names = "axi_clk", "core_clk", "apb_clk"; resets = <&rstgen RSTN_U0_CODAJ12_AXI>, <&rstgen RSTN_U0_CODAJ12_CORE>, <&rstgen RSTN_U0_CODAJ12_APB>; reset-names = "rst_axi", "rst_core", "rst_apb"; status = "disabled"; }; vpu_dec: vpu_dec@130A0000 { compatible = "starfive,vdec"; reg = <0x0 0x130A0000 0x0 0x10000>; interrupts = <13>; clocks = <&clkgen JH7110_WAVE511_CLK_AXI>, <&clkgen JH7110_WAVE511_CLK_BPU>, <&clkgen JH7110_WAVE511_CLK_VCE>, <&clkgen JH7110_WAVE511_CLK_APB>, <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>; clock-names = "axi_clk", "bpu_clk", "vce_clk", "apb_clk", "noc_bus"; resets = <&rstgen RSTN_U0_WAVE511_AXI>, <&rstgen RSTN_U0_WAVE511_BPU>, <&rstgen RSTN_U0_WAVE511_VCE>, <&rstgen RSTN_U0_WAVE511_APB>, <&rstgen RSTN_U0_AXIMEM_128B_AXI>; reset-names = "rst_axi", "rst_bpu", "rst_vce", "rst_apb", "rst_sram"; starfive,vdec_noc_ctrl; status = "disabled"; }; vpu_enc: vpu_enc@130B0000 { compatible = "starfive,venc"; reg = <0x0 0x130B0000 0x0 0x10000>; interrupts = <15>; clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>, <&clkgen JH7110_WAVE420L_CLK_BPU>, <&clkgen JH7110_WAVE420L_CLK_VCE>, <&clkgen JH7110_WAVE420L_CLK_APB>, <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>; clock-names = "axi_clk", "bpu_clk", "vce_clk", "apb_clk", "noc_bus"; resets = <&rstgen RSTN_U0_WAVE420L_AXI>, <&rstgen RSTN_U0_WAVE420L_BPU>, <&rstgen RSTN_U0_WAVE420L_VCE>, <&rstgen RSTN_U0_WAVE420L_APB>, <&rstgen RSTN_U1_AXIMEM_128B_AXI>; reset-names = "rst_axi", "rst_bpu", "rst_vce", "rst_apb", "rst_sram"; starfive,venc_noc_ctrl; status = "disabled"; }; rstgen: reset-controller { compatible = "starfive,jh7110-reset"; reg = <0x0 0x13020000 0x0 0x10000>, <0x0 0x10230000 0x0 0x10000>, <0x0 0x17000000 0x0 0x10000>, <0x0 0x19810000 0x0 0x10000>, <0x0 0x295C0000 0x0 0x10000>; reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg"; #reset-cells = <1>; status = "okay"; }; stmmac_axi_setup: stmmac-axi-config { snps,wr_osr_lmt = <0xf>; snps,rd_osr_lmt = <0xf>; snps,blen = <256 128 64 32 0 0 0>; }; gmac0: ethernet@16030000 { compatible = "starfive,jh7110-eqos-5.20"; reg = <0x0 0x16030000 0x0 0x10000>; clock-names = "gtx", "tx", "ptp_ref", "stmmaceth", "pclk"; clocks = <&clkgen JH7110_GMAC0_GTXCLK>, <&clkgen JH7110_U0_GMAC5_CLK_TX>, <&clkgen JH7110_GMAC0_PTP>, <&clkgen JH7110_U0_GMAC5_CLK_AHB>, <&clkgen JH7110_U0_GMAC5_CLK_AXI>; resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>, <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>; reset-names = "ahb", "stmmaceth"; interrupts = <7>, <6>, <5> ; interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; max-frame-size = <9000>; phy-mode = "rgmii-id"; snps,multicast-filter-bins = <256>; snps,perfect-filter-entries = <128>; rx-fifo-depth = <262144>; tx-fifo-depth = <131072>; snps,fixed-burst; snps,no-pbl-x8; snps,force_thresh_dma_mode; snps,axi-config = <&stmmac_axi_setup>; snps,tso; snps,en-tx-lpi-clockgating; snps,en-lpi; snps,write-requests = <2>; snps,read-requests = <16>; snps,burst-map = <0x7>; snps,txpbl = <16>; snps,rxpbl = <16>; status = "disabled"; }; gmac1: ethernet@16040000 { compatible = "starfive,jh7110-eqos-5.20"; reg = <0x0 0x16040000 0x0 0x10000>; clock-names = "gtx", "tx", "ptp_ref", "stmmaceth", "pclk"; clocks = <&clkgen JH7110_GMAC1_GTXCLK>, <&clkgen JH7110_GMAC5_CLK_TX>, <&clkgen JH7110_GMAC5_CLK_PTP>, <&clkgen JH7110_GMAC5_CLK_AHB>, <&clkgen JH7110_GMAC5_CLK_AXI>; resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>, <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>; reset-names = "ahb", "stmmaceth"; interrupts = <78>, <77>, <76> ; interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; max-frame-size = <9000>; phy-mode = "rgmii-id"; snps,multicast-filter-bins = <256>; snps,perfect-filter-entries = <128>; rx-fifo-depth = <262144>; tx-fifo-depth = <131072>; snps,fixed-burst; snps,no-pbl-x8; snps,force_thresh_dma_mode; snps,axi-config = <&stmmac_axi_setup>; snps,tso; snps,en-tx-lpi-clockgating; snps,en-lpi; snps,write-requests = <2>; snps,read-requests = <16>; snps,burst-map = <0x7>; snps,txpbl = <16>; snps,rxpbl = <16>; status = "disabled"; }; gpu: gpu@18000000 { compatible = "img-gpu"; reg = <0x0 0x18000000 0x0 0x100000 0x0 0x130C000 0x0 0x10000>; clocks = <&gpu_core_clk>, <&gpu_sys_clk>; clock-names = "gpu_core_clk","gpu_sys_clk"; interrupts = <82>; current-clock = <8000000>; status = "disabled"; }; can0: can@130d0000 { compatible = "ipms,can"; reg = <0x0 0x130d0000 0x0 0x1000>; interrupts = <112>; clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>, <&clkgen JH7110_CAN0_CTRL_CLK_CAN>, <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>; clock-names = "apb_clk", "core_clk", "timer_clk"; resets = <&rstgen RSTN_U0_CAN_CTRL_APB>, <&rstgen RSTN_U0_CAN_CTRL_CORE>, <&rstgen RSTN_U0_CAN_CTRL_TIMER>; reset-names = "rst_apb", "rst_core", "rst_timer"; starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>; syscon,can_or_canfd = <0>; status = "disabled"; }; can1: can@130e0000 { compatible = "ipms,can"; reg = <0x0 0x130e0000 0x0 0x1000>; interrupts = <113>; clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>, <&clkgen JH7110_CAN1_CTRL_CLK_CAN>, <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>; clock-names = "apb_clk", "core_clk", "timer_clk"; resets = <&rstgen RSTN_U1_CAN_CTRL_APB>, <&rstgen RSTN_U1_CAN_CTRL_CORE>, <&rstgen RSTN_U1_CAN_CTRL_TIMER>; reset-names = "rst_apb", "rst_core", "rst_timer"; starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>; syscon,can_or_canfd = <0>; status = "disabled"; }; tdm: tdm@10090000 { compatible = "starfive,tdm"; reg = <0x0 0x10090000 0x0 0x1000>; reg-names = "tdm"; clocks = <&audioclk>; clock-names = "audioclk"; dmas = <&dma 20 1>, <&dma 21 1>; dma-names = "rx","tx"; #sound-dai-cells = <0>; status = "disabled"; }; spdif0: spdif0@100a0000 { compatible = "starfive,sf-spdif"; reg = <0x0 0x100a0000 0x0 0x1000>; clocks = <&audioclk>; clock-names = "audioclk"; interrupts = <84>; interrupt-names = "tx"; #sound-dai-cells = <0>; status = "disabled"; }; pwmdac: pwmdac@100b0000 { compatible = "sf,pwmdac"; reg = <0x0 0x100b0000 0x0 0x1000>; clocks = <&apb0clk>; dmas = <&dma 22 1>; dma-names = "tx"; #sound-dai-cells = <0>; status = "disabled"; }; i2stx: i2stx@100c0000 { compatible = "snps,designware-i2stx"; reg = <0x0 0x100c0000 0x0 0x1000>; clocks = <&apb0clk>; clock-names = "i2sclk"; interrupt-names = "tx"; #sound-dai-cells = <0>; dmas = <&dma 28 1>; dma-names = "rx"; status = "disabled"; }; pdm: pdm@100d0000 { compatible = "starfive,sf-pdm"; reg = <0x0 0x100d0000 0x0 0x1000>; reg-names = "pdm"; clocks = <&audioclk>; clock-names = "audioclk"; #sound-dai-cells = <0>; status = "disabled"; }; i2srx_3ch: i2srx-3ch@100e0000 { compatible = "snps,designware-i2srx"; reg = <0x0 0x100e0000 0x0 0x1000>; clocks = <&apb0clk>; clock-names = "i2sclk"; interrupts = <42>; interrupt-names = "rx"; #sound-dai-cells = <0>; status = "disabled"; }; i2stx_4ch0: i2stx-4ch0@120b0000 { compatible = "snps,designware-i2stx-4ch0"; reg = <0x0 0x120b0000 0x0 0x1000>; clocks = <&apb0clk>; clock-names = "i2sclk"; interrupts = <58>; interrupt-names = "tx"; #sound-dai-cells = <0>; status = "disabled"; }; i2stx_4ch1: i2sdac1@120c0000 { compatible = "snps,designware-i2stx-4ch1"; reg = <0x0 0x120c0000 0x0 0x1000>; clocks = <&apb0clk>; clock-names = "i2sclk"; interrupts = <59>; interrupt-names = "tx"; #sound-dai-cells = <0>; status = "disabled"; }; ptc: pwm@120d0000 { compatible = "starfive,pwm0"; reg = <0x0 0x120d0000 0x0 0x10000>; reg-names = "control"; clocks = <&clkgen JH7110_PWM_CLK_APB>; resets = <&rstgen RSTN_U0_PWM_8CH_APB>; starfive,approx-period = <2000000>; #pwm-cells=<3>; starfive,npwm = <8>; status = "disabled"; }; spdif_transmitter: spdif_transmitter { compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; status = "disabled"; }; spdif_receiver: spdif_receiver { compatible = "linux,spdif-dir"; #sound-dai-cells = <0>; status = "disabled"; }; pwmdac_codec: pwmdac-transmitter { compatible = "linux,pwmdac-dit"; #sound-dai-cells = <0>; status = "disabled"; }; dmic_codec: dmic_codec { compatible = "dmic-codec"; #sound-dai-cells = <0>; status = "disabled"; }; spi0: spi0@10060000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x0 0x10060000 0x0 0x10000>; clocks = <&ahb1clk>; clock-names = "apb_pclk"; interrupts = <38>; dmas = <&dma 14 1>, <&dma 15 1>; dma-names = "rx","tx"; arm,primecell-periphid = <0x00041022>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; pcie0: pcie0@2B000000 { compatible = "plda,pci-xpressrich3-axi"; reg = <0x0 0x2B000000 0x0 0x1000000 0x9 0x40000000 0x0 0x10000000>; reg-names = "reg", "config"; interrupts = <56>; interrupt-controller; interrupt-names = "msi"; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>, <0x0 0x0 0x0 0x2 &plic 0x2>, <0x0 0x0 0x0 0x3 &plic 0x3>, <0x0 0x0 0x0 0x4 &plic 0x4>; resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>, <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>, <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>, <&rstgen RSTN_U0_PLDA_PCIE_BRG>, <&rstgen RSTN_U0_PLDA_PCIE_CORE>, <&rstgen RSTN_U0_PLDA_PCIE_APB>; reset-names = "rst_mst0", "rst_slv0", "rst_slv", "rst_brg", "rst_core", "rst_apb"; clocks = <&clkgen JH7110_PCIE0_CLK_TL>, <&clkgen JH7110_PCIE0_CLK_AXI_MST0>, <&clkgen JH7110_PCIE0_CLK_APB>; clock-names = "tl", "axi_mst0", "apb"; #interrupt-cells = <1>; device_type = "pci"; starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>; bus-range = <0x0 0xff>; msi-parent = <&plic>; #address-cells = <3>; #size-cells = <2>; ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x06000000>; status = "disabled"; }; pcie1:pcie1@2C000000 { compatible = "plda,pci-xpressrich3-axi"; reg = <0x0 0x2C000000 0x0 0x1000000 0x9 0xc0000000 0x0 0x10000000>; reg-names = "reg", "config"; device_type = "pci"; starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>; bus-range = <0x0 0xff>; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x06000000>; msi-parent = <&plic>; interrupts = <57>; interrupt-controller; interrupt-names = "msi"; interrupt-parent = <&plic>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>, <0x0 0x0 0x0 0x2 &plic 0x2>, <0x0 0x0 0x0 0x3 &plic 0x3>, <0x0 0x0 0x0 0x4 &plic 0x4>; resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>, <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>, <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>, <&rstgen RSTN_U1_PLDA_PCIE_BRG>, <&rstgen RSTN_U1_PLDA_PCIE_CORE>, <&rstgen RSTN_U1_PLDA_PCIE_APB>; reset-names = "rst_mst0", "rst_slv0", "rst_slv", "rst_brg", "rst_core", "rst_apb"; clocks = <&clkgen JH7110_PCIE1_CLK_TL>, <&clkgen JH7110_PCIE1_CLK_AXI_MST0>, <&clkgen JH7110_PCIE1_CLK_APB>; clock-names = "tl", "axi_mst0", "apb"; status = "disabled"; }; mailbox_contrl0: mailbox@0 { compatible = "starfive,mail_box"; reg = <0x0 0x13060000 0x0 0x0001000>; clocks = <&clkgen JH7110_MAILBOX_CLK_APB>; clock-names = "clk_apb"; resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>; reset-names = "mbx_rre"; interrupts = <26 27>; #mbox-cells = <2>; status = "disabled"; }; mailbox_client0: mailbox_client@0 { compatible = "starfive,mailbox-test"; mbox-names = "rx", "tx"; mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>; status = "disabled"; }; display: display-subsystem { compatible = "verisilicon,display-subsystem"; ports = <&dc_out_dpi0>; status = "disabled"; }; dssctrl: dssctrl@295B0000 { compatible = "verisilicon,dss-ctrl", "syscon"; reg = <0 0x295B0000 0 0x90>; }; hdmi_output: hdmi-output { compatible = "verisilicon,hdmi-encoder"; verisilicon,dss-syscon = <&dssctrl>; verisilicon,mux-mask = <0x70 0x380>; verisilicon,mux-val = <0x40 0x280>; status = "disabled"; }; dc8200: dc8200@29400000 { compatible = "verisilicon,dc8200"; reg = <0x0 0x29400000 0x0 0x100>, <0x0 0x29400800 0x0 0x2000>, <0x0 0x17030000 0x0 0x1000>; interrupts = <95>; status = "disabled"; clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>, <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>, <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>, <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>, <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>, <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>, <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>, <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>, <&clkgen JH7110_VOUT_SRC>, <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>, <&clkgen JH7110_AHB1>, <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>, <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>, <&clkgen JH7110_I2STX_4CH0_BCLK_MST>, <&clkvout JH7110_U0_DC8200_CLK_PIX0>, <&clkvout JH7110_U0_DC8200_CLK_PIX1>, <&clkvout JH7110_U0_DC8200_CLK_AXI>, <&clkvout JH7110_U0_DC8200_CLK_CORE>, <&clkvout JH7110_U0_DC8200_CLK_AHB>; clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc", "noc_disp","noc_isp","noc_stg","vout_src", "top_vout_axi","ahb1","top_vout_ahb", "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1", "axi_clk","core_clk","vout_ahb"; resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>, <&rstgen RSTN_U0_DC8200_AXI>, <&rstgen RSTN_U0_DC8200_AHB>, <&rstgen RSTN_U0_DC8200_CORE>, <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>, <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>, <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>, <&rstgen RSTN_U0_NOC_BUS_GPU_AXI_N>, <&rstgen RSTN_U0_NOC_BUS_VDEC_AXI_N>, <&rstgen RSTN_U0_JTAG2APB_PRESETN>, <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>, <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>, <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>, <&rstgen RSTN_U0_NOC_BUS_DDRC_N>; reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core", "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb", "rst_noc_gpu","rst_noc_vdec","rst_jtag2apb", "rst_noc_disp","rst_noc_isp","rst_noc_stg","rst_noc_ddrc"; }; mipi_dphy: mipi-dphy@295e0000{ compatible = "starfive,jh7100-mipi-dphy-tx"; reg = <0x0 0x295e0000 0x0 0x10000>; /*clocks = <&uartclk>, <&apb2clk>;*/ /*clock-names = "baudclk", "apb_pclk";*/ clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>; clock-names = "dphy_txesc"; resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>, <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>; reset-names = "dphy_sys", "dphy_txbytehs"; #phy-cells = <0>; status = "disabled"; }; mipi_dsi: mipi@295d0000 { compatible = "cdns,dsi"; reg = <0x0 0x295d0000 0x0 0x10000>; reg-names = "dsi"; /*clocks = <&apb1clk>, <&apb2clk>;*/ /*clock-names = "dsi_p_clk", "dsi_sys_clk";*/ clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>, <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>, <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>, <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>; clock-names = "sys", "apb", "txesc", "dpi"; resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>, <&rstgen RSTN_U0_CDNS_DSITX_APB>, <&rstgen RSTN_U0_CDNS_DSITX_RXESC>, <&rstgen RSTN_U0_CDNS_DSITX_SYS>, <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>, <&rstgen RSTN_U0_CDNS_DSITX_TXESC>; reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc", "dsi_sys", "dsi_txbytehs", "dsi_txesc"; phys = <&mipi_dphy>; phy-names = "dphy"; status = "disabled"; port { dsi_out_port: endpoint { /*remote-endpoint = <&panel_dsi_port>;*/ }; }; mipi_panel: panel@0 { /*compatible = "";*/ status = "disabled"; }; }; hdmi: hdmi@29590000 { compatible = "rockchip,rk3036-inno-hdmi"; reg = <0x29590000 0x4000>; /*interrupts = ;*/ /*clocks = <&cru PCLK_HDMI>;*/ /*clock-names = "pclk";*/ /*pinctrl-names = "default";*/ /*pinctrl-0 = <&hdmi_ctl>;*/ status = "disabled"; clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>, <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>, <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>; clock-names = "sysclk", "mclk", "bclk"; resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>; reset-names = "hdmi_tx"; hdmi_in: port { #address-cells = <1>; #size-cells = <0>; hdmi_in_lcdc: endpoint@0 { reg = <0>; remote-endpoint = <&dc_out_dpi0>; }; }; }; sound_pwmdac: snd-card_pwmdac { compatible = "simple-audio-card"; simple-audio-card,name = "Starfive-Pwmdac-Sound-Card"; simple-audio-card,bitclock-master = <&pwmdac_dailink_master>; simple-audio-card,frame-master = <&pwmdac_dailink_master>; simple-audio-card,format = "left_j"; status = "disabled"; pwmdac_dailink_master: simple-audio-card,cpu { sound-dai = <&pwmdac>; }; simple-audio-card,codec { sound-dai = <&pwmdac_codec>; }; }; co_process: e24@0 { compatible = "starfive,e24"; reg = <0x0 0xc0110000 0x0 0x00001000 0x0 0xc0111000 0x0 0x0001f000>; reg-names = "ecmd","espace"; clocks = <&clkgen JH7110_E2_RTC_CLK>, <&clkgen JH7110_E2_CLK_CORE>, <&clkgen JH7110_E2_CLK_DBG>; clock-names = "clk_rtc","clk_core","clk_dbg"; resets = <&rstgen RSTN_U0_E24_CORE>; reset-names = "e24_core"; starfive,stg-syscon = <&stg_syscon>; interrupt-parent = <&plic>; firmware-name = "e24_elf"; irq-mode = <1>; mbox-names = "tx", "rx"; mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>; #address-cells = <1>; #size-cells = <1>; ranges = <0xc0000000 0x0 0xc0000000 0x200000>; status = "disabled"; dsp@0 {}; }; }; };