/*
 * Copyright (C) 2013 Spreadtrum Communication Incorporated
 *		http://www.spreadtrum.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@f00 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf00>;
		};

		cpu@f01 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf01>;
		};
	};

	fb0: fb@20800000 {
		compatible = "sprd,sprdfb";
		reg = <0xf5122000 0x1000>,<0xf5146000 0x1000>;
		interrupts = <0 46 0x0>,<0 48 0x0>, <0 49 0x0>;
		clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent";
		clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>;
		clock-src = <256000000 256000000 384000000>;
		dpi_clk_div = <7>;
		sprd,fb_use_reservemem;
		sprd,fb_mem = <0x9F73E000 0x1c2000>;
	};

	sprd_sensor {
		compatible  = "sprd,sprd_sensor";
		gpios = <&d_gpio_gpio 186 0   /*reset*/
		        &d_gpio_gpio 188 0    /*main*/
		        &d_gpio_gpio 187 0>;  /*sub */
		clock-names ="clk_mm_i","clk_sensor","clk_ccir","clk_dcam","clk_dcam_mipi";
		clocks = <&clk_mm>, <&clk_sensor>,<&clk_ccir>, <&clk_dcam>, <&clk_dcam_mipi>;
	};

	sdhci0: sdhci@f5117000 {
		compatible  = "sprd,sdhci-shark";
		interrupts = <0 57 0x0>;
		reg = <0xf5117000 0x1000>;
		id = <0>;
		bus-width = <4>;
		max-frequency = <384000000>;
		keep-power-in-suspend = <1>;
		caps = <0x80000000>;
		caps2 = <0x202>;
		host-caps-mask = <0x05000000>;
		vdd-vqmmc = "vddsdcore";
		sd-supply = <&vddsdio>;
		vdd-level = <0 0 1800000 3000000>;
		pinmap-offset = <0x0184>;
		d3-gpio = <100>;
		d3-index = <0>;
		sd-func = <0>;
		gpio-func = <3>;
		clock-names = "clk_sdio0";
		clocks = <&clk_sdio0>, <&clk_384m>;
		enb-bit = <0x100>;
		rst-bit = <0x800>;
		keep-power = <0>;
		runtime = <1>;
	};

	gpu {
		compatible  = "sprd,mali-utgard";
		mali_pp_core_number = <1>;
		interrupt-names = "mali_gp_irq",
				"mali_gp_mmu_irq",
				"mali_pp0_irq",
				"mali_pp0_mmu_irq";
		reg-names = "mali_l2",
				"mali_gp",
				"mali_gp_mmu",
				"mali_pp0",
				"mali_pp0_mmu",
				"mali_pmu";
		interrupts =  <0 39 0x0>,  //  MALI_GP_IRQ,
					<0 39 0x0>,  //  MALI_GP_MMU_IRQ,
					<0 39 0x0>,  //  MALI_PP0_IRQ,
					<0 39 0x0>;  //  MALI_PP0_MMU_IRQ,
		reg = <0x60001000 0x200>,//  MALI_L2,MALI_GPU_RESOURCE_L2(base_addr + 0x1000)
			<0x60000000 0x100>,//  MALI_GP,
			<0x60003000 0x100>,//  MALI_GP_MMU,
			<0x60008000 0x1100>,//  MALI_PP0,
			<0x60004000 0x100>,//  MALI_PP0_MMU,
			<0x60002000 0x100>;//  MALI_PMU,
		clock-names = "clk_gpu_axi","clk_gpu","clk_153m6","clk_208m","clk_256m","clk_312m","clk_384m","clk_460m8";
		clocks = <&clk_gpu_axi>,<&clk_gpu>,<&clk_153m6>,<&clk_208m>,<&clk_256m>,<&clk_312m>,<&clk_384m>,<&clk_460m8>;
	};

	ion {
		compatible = "sprd,ion-sprd";
		#address-cells = <1>;
		#size-cells = <0>;

		sprd,ion-heap@1 {
			reg = <1>;                      /* SYSTEM */
			reg-names = "ion_heap_system";
			sprd,ion-heap-type = <0>;       /* SYSTEM */
			sprd,ion-heap-mem = <0x0 0x0>;
		};

		sprd,ion-heap@2 {
			reg = <2>;                      /* MM */
			reg-names = "ion_heap_carveout_mm";
			sprd,ion-heap-type = <0>;       /* carveout mm */
			sprd,ion-heap-mem = <0x0 0x0>;
		};

		sprd,ion-heap@3 {
			reg = <3>;                      /* OVERLAY */
			reg-names = "ion_heap_carveout_overlay";
			sprd,ion-heap-type = <2>;       /* CARVEOUT */
			sprd,ion-heap-mem = <0x9f900000 0x700000>;      /* 7M */
		};
	};

	/* sipc initializer */
	sipc: sipc-common {
		compatible = "sprd,sipc";
		reg = <0x87800000 0x240000>; /* <SMEM SIZE>*/
		//#interrupt-cells = <2>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x8000000 0x88000000 0x1b00000>,
				<0x07800000 0x87800000 0x180000>,
				<0x9aff000 0x89aff000 0x1000>;
		sipc_cpw@0x8000000 {
			sprd,name = "sipc-w";
			sprd,dst = <2>;
			sprd,ap2cp = <0xf5240000>; /* base on ipi reggister */
			sprd,cp2ap = <0xf5240004>;
			sprd,trig = <0x01>; /* trigger bit */
			sprd,clr = <0x01>; /* clear bit */
			interrupts = <0 68 0x0>;
			reg = <0x8000000 0x1b00000> , /* <CP_start_addr size> */
				<0x07800000 0x180000>, /* <SMEM_phy_addr total_size> */
				<0x9aff000 0x1000>; /* smsg ring buffer <base size> */
		};
	};

	/* cpw virtual devices */

	scproc_cpw: scproc@0x88000000 {
		compatible = "sprd,scproc";
		sprd,name = "cpw";
		sprd,ctrl-reg = <0x44 0x44 0xb0 0xbc>; /* <shut_down deep_sleep reset get_status> */
		sprd,ctrl-mask = <0x02000000 0x10000000 0x01 0xf0000>; /* masks <> */
		sprd,iram-data = <0xe59f0000 0xe12fff10 0x88300000>; /* 3rd param equals modem_addr*/
		reg = <0x88000000 0x1b00000>, /* <CP_start_addr total_size> = <+128M 27M> */
			<0xf53d4000 0x0c>, /* <iram1_base size> */
			<0xf5230000 0x10000>; /* <pmu_base size> */
		interrupts = <0 84 0x0>; /* cp1_wdg_int */
		#address-cells = <1>;
		#size-cells = <1>;
		/* segnr=2 */
		ranges = <0x300000 0x88300000 0x00800000>,
				<0x20000 0x88020000 0x00220000>;
		modem@0x300000 {
			cproc,name = "modem";
			reg = <0x300000 0x00800000>; /* <modem_addr size> */
		};
		dsp@0x20000 {
			cproc,name = "dsp";
			reg = <0x20000 0x00220000>; /* <dsp_addr size>*/
		};
	};

	
};