2 * Copyright (c) 2010 The WebM project authors. All Rights Reserved.
4 * Use of this source code is governed by a BSD-style license
5 * that can be found in the LICENSE file in the root of the source
6 * tree. An additional intellectual property rights grant can be found
7 * in the file PATENTS. All contributing project authors may
8 * be found in the AUTHORS file in the root of the source tree.
12 #ifndef VPX_PORTS_X86_H
13 #define VPX_PORTS_X86_H
15 #include "vpx_config.h"
30 VPX_CPU_TRANSMETA_OLD,
37 #if defined(__GNUC__) && __GNUC__
39 #define cpuid(func,ax,bx,cx,dx)\
40 __asm__ __volatile__ (\
42 : "=a" (ax), "=b" (bx), "=c" (cx), "=d" (dx) \
45 #define cpuid(func,ax,bx,cx,dx)\
46 __asm__ __volatile__ (\
47 "mov %%ebx, %%edi \n\t" \
49 "xchg %%edi, %%ebx \n\t" \
50 : "=a" (ax), "=D" (bx), "=c" (cx), "=d" (dx) \
53 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
55 #define cpuid(func,ax,bx,cx,dx)\
57 "xchg %rsi, %rbx \n\t" \
59 "movl %ebx, %edi \n\t" \
60 "xchg %rsi, %rbx \n\t" \
61 : "=a" (ax), "=D" (bx), "=c" (cx), "=d" (dx) \
64 #define cpuid(func,ax,bx,cx,dx)\
68 "movl %ebx, %edi \n\t" \
70 : "=a" (ax), "=D" (bx), "=c" (cx), "=d" (dx) \
75 void __cpuid(int CPUInfo[4], int info_type);
76 #pragma intrinsic(__cpuid)
77 #define cpuid(func,a,b,c,d) do{\
79 __cpuid(regs,func); a=regs[0]; b=regs[1]; c=regs[2]; d=regs[3];\
82 #define cpuid(func,a,b,c,d)\
96 #define HAS_SSSE3 0x10
97 #define HAS_SSE4_1 0x20
105 unsigned int flags = 0;
106 unsigned int mask = ~0;
107 unsigned int reg_eax, reg_ebx, reg_ecx, reg_edx;
111 /* See if the CPU capabilities are being overridden by the environment */
112 env = getenv("VPX_SIMD_CAPS");
115 return (int)strtol(env, NULL, 0);
117 env = getenv("VPX_SIMD_CAPS_MASK");
120 mask = strtol(env, NULL, 0);
122 /* Ensure that the CPUID instruction supports extended features */
123 cpuid(0, reg_eax, reg_ebx, reg_ecx, reg_edx);
128 /* Get the standard feature flags */
129 cpuid(1, reg_eax, reg_ebx, reg_ecx, reg_edx);
131 if (reg_edx & BIT(23)) flags |= HAS_MMX;
133 if (reg_edx & BIT(25)) flags |= HAS_SSE; /* aka xmm */
135 if (reg_edx & BIT(26)) flags |= HAS_SSE2; /* aka wmt */
137 if (reg_ecx & BIT(0)) flags |= HAS_SSE3;
139 if (reg_ecx & BIT(9)) flags |= HAS_SSSE3;
141 if (reg_ecx & BIT(19)) flags |= HAS_SSE4_1;
146 vpx_cpu_t vpx_x86_vendor(void);
148 #if ARCH_X86_64 && defined(_MSC_VER)
149 unsigned __int64 __rdtsc(void);
150 #pragma intrinsic(__rdtsc)
155 #if defined(__GNUC__) && __GNUC__
157 __asm__ __volatile__("rdtsc\n\t":"=a"(tsc):);
159 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
161 asm volatile("rdtsc\n\t":"=a"(tsc):);
173 #if defined(__GNUC__) && __GNUC__
174 #define x86_pause_hint()\
175 __asm__ __volatile__ ("pause \n\t")
176 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
177 #define x86_pause_hint()\
178 asm volatile ("pause \n\t")
181 #define x86_pause_hint()\
184 #define x86_pause_hint()\
189 #if defined(__GNUC__) && __GNUC__
191 x87_set_control_word(unsigned short mode)
193 __asm__ __volatile__("fldcw %0" : : "m"(*&mode));
195 static unsigned short
196 x87_get_control_word(void)
199 __asm__ __volatile__("fstcw %0\n\t":"=m"(*&mode):);
202 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
204 x87_set_control_word(unsigned short mode)
206 asm volatile("fldcw %0" : : "m"(*&mode));
208 static unsigned short
209 x87_get_control_word(void)
212 asm volatile("fstcw %0\n\t":"=m"(*&mode):);
216 /* No fldcw intrinsics on Windows x64, punt to external asm */
217 extern void vpx_winx64_fldcw(unsigned short mode);
218 extern unsigned short vpx_winx64_fstcw(void);
219 #define x87_set_control_word vpx_winx64_fldcw
220 #define x87_get_control_word vpx_winx64_fstcw
223 x87_set_control_word(unsigned short mode)
227 static unsigned short
228 x87_get_control_word(void)
236 static unsigned short
237 x87_set_double_precision(void)
239 unsigned short mode = x87_get_control_word();
240 x87_set_control_word((mode&~0x300) | 0x200);
245 extern void vpx_reset_mmx_state(void);