2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/cpu.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_host.h>
22 #include <linux/interrupt.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
28 #include <linux/irqchip/arm-gic.h>
30 #include <asm/kvm_emulate.h>
31 #include <asm/kvm_arm.h>
32 #include <asm/kvm_mmu.h>
35 * How the whole thing works (courtesy of Christoffer Dall):
37 * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
38 * something is pending
39 * - VGIC pending interrupts are stored on the vgic.irq_state vgic
40 * bitmap (this bitmap is updated by both user land ioctls and guest
41 * mmio ops, and other in-kernel peripherals such as the
42 * arch. timers) and indicate the 'wire' state.
43 * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
45 * - To calculate the oracle, we need info for each cpu from
46 * compute_pending_for_cpu, which considers:
47 * - PPI: dist->irq_state & dist->irq_enable
48 * - SPI: dist->irq_state & dist->irq_enable & dist->irq_spi_target
49 * - irq_spi_target is a 'formatted' version of the GICD_ICFGR
50 * registers, stored on each vcpu. We only keep one bit of
51 * information per interrupt, making sure that only one vcpu can
52 * accept the interrupt.
53 * - The same is true when injecting an interrupt, except that we only
54 * consider a single interrupt at a time. The irq_spi_cpu array
55 * contains the target CPU for each SPI.
57 * The handling of level interrupts adds some extra complexity. We
58 * need to track when the interrupt has been EOIed, so we can sample
59 * the 'line' again. This is achieved as such:
61 * - When a level interrupt is moved onto a vcpu, the corresponding
62 * bit in irq_active is set. As long as this bit is set, the line
63 * will be ignored for further interrupts. The interrupt is injected
64 * into the vcpu with the GICH_LR_EOI bit set (generate a
65 * maintenance interrupt on EOI).
66 * - When the interrupt is EOIed, the maintenance interrupt fires,
67 * and clears the corresponding bit in irq_active. This allow the
68 * interrupt line to be sampled again.
71 #define VGIC_ADDR_UNDEF (-1)
72 #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
74 /* Physical address of vgic virtual cpu interface */
75 static phys_addr_t vgic_vcpu_base;
77 /* Virtual control interface base address */
78 static void __iomem *vgic_vctrl_base;
80 static struct device_node *vgic_node;
82 #define ACCESS_READ_VALUE (1 << 0)
83 #define ACCESS_READ_RAZ (0 << 0)
84 #define ACCESS_READ_MASK(x) ((x) & (1 << 0))
85 #define ACCESS_WRITE_IGNORED (0 << 1)
86 #define ACCESS_WRITE_SETBIT (1 << 1)
87 #define ACCESS_WRITE_CLEARBIT (2 << 1)
88 #define ACCESS_WRITE_VALUE (3 << 1)
89 #define ACCESS_WRITE_MASK(x) ((x) & (3 << 1))
91 static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu);
92 static void vgic_update_state(struct kvm *kvm);
93 static void vgic_kick_vcpus(struct kvm *kvm);
94 static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg);
95 static u32 vgic_nr_lr;
97 static unsigned int vgic_maint_irq;
99 static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x,
100 int cpuid, u32 offset)
104 return x->percpu[cpuid].reg;
106 return x->shared.reg + offset - 1;
109 static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x,
112 if (irq < VGIC_NR_PRIVATE_IRQS)
113 return test_bit(irq, x->percpu[cpuid].reg_ul);
115 return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared.reg_ul);
118 static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
123 if (irq < VGIC_NR_PRIVATE_IRQS) {
124 reg = x->percpu[cpuid].reg_ul;
126 reg = x->shared.reg_ul;
127 irq -= VGIC_NR_PRIVATE_IRQS;
136 static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid)
138 if (unlikely(cpuid >= VGIC_MAX_CPUS))
140 return x->percpu[cpuid].reg_ul;
143 static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x)
145 return x->shared.reg_ul;
148 static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset)
151 BUG_ON(offset > (VGIC_NR_IRQS / 4));
153 return x->percpu[cpuid] + offset;
155 return x->shared + offset - 8;
158 #define VGIC_CFG_LEVEL 0
159 #define VGIC_CFG_EDGE 1
161 static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq)
163 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
166 irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq);
167 return irq_val == VGIC_CFG_EDGE;
170 static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq)
172 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
174 return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq);
177 static int vgic_irq_is_active(struct kvm_vcpu *vcpu, int irq)
179 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
181 return vgic_bitmap_get_irq_val(&dist->irq_active, vcpu->vcpu_id, irq);
184 static void vgic_irq_set_active(struct kvm_vcpu *vcpu, int irq)
186 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
188 vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 1);
191 static void vgic_irq_clear_active(struct kvm_vcpu *vcpu, int irq)
193 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
195 vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 0);
198 static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq)
200 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
202 return vgic_bitmap_get_irq_val(&dist->irq_state, vcpu->vcpu_id, irq);
205 static void vgic_dist_irq_set(struct kvm_vcpu *vcpu, int irq)
207 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
209 vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 1);
212 static void vgic_dist_irq_clear(struct kvm_vcpu *vcpu, int irq)
214 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
216 vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 0);
219 static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq)
221 if (irq < VGIC_NR_PRIVATE_IRQS)
222 set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
224 set_bit(irq - VGIC_NR_PRIVATE_IRQS,
225 vcpu->arch.vgic_cpu.pending_shared);
228 static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq)
230 if (irq < VGIC_NR_PRIVATE_IRQS)
231 clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
233 clear_bit(irq - VGIC_NR_PRIVATE_IRQS,
234 vcpu->arch.vgic_cpu.pending_shared);
237 static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask)
239 return *((u32 *)mmio->data) & mask;
242 static void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value)
244 *((u32 *)mmio->data) = value & mask;
248 * vgic_reg_access - access vgic register
249 * @mmio: pointer to the data describing the mmio access
250 * @reg: pointer to the virtual backing of vgic distributor data
251 * @offset: least significant 2 bits used for word offset
252 * @mode: ACCESS_ mode (see defines above)
254 * Helper to make vgic register access easier using one of the access
255 * modes defined for vgic register access
256 * (read,raz,write-ignored,setbit,clearbit,write)
258 static void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,
259 phys_addr_t offset, int mode)
261 int word_offset = (offset & 3) * 8;
262 u32 mask = (1UL << (mmio->len * 8)) - 1;
266 * Any alignment fault should have been delivered to the guest
267 * directly (ARM ARM B3.12.7 "Prioritization of aborts").
273 BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED));
277 if (mmio->is_write) {
278 u32 data = mmio_data_read(mmio, mask) << word_offset;
279 switch (ACCESS_WRITE_MASK(mode)) {
280 case ACCESS_WRITE_IGNORED:
283 case ACCESS_WRITE_SETBIT:
287 case ACCESS_WRITE_CLEARBIT:
291 case ACCESS_WRITE_VALUE:
292 regval = (regval & ~(mask << word_offset)) | data;
297 switch (ACCESS_READ_MASK(mode)) {
298 case ACCESS_READ_RAZ:
302 case ACCESS_READ_VALUE:
303 mmio_data_write(mmio, mask, regval >> word_offset);
308 static bool handle_mmio_misc(struct kvm_vcpu *vcpu,
309 struct kvm_exit_mmio *mmio, phys_addr_t offset)
312 u32 word_offset = offset & 3;
314 switch (offset & ~3) {
316 reg = vcpu->kvm->arch.vgic.enabled;
317 vgic_reg_access(mmio, ®, word_offset,
318 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
319 if (mmio->is_write) {
320 vcpu->kvm->arch.vgic.enabled = reg & 1;
321 vgic_update_state(vcpu->kvm);
327 reg = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
328 reg |= (VGIC_NR_IRQS >> 5) - 1;
329 vgic_reg_access(mmio, ®, word_offset,
330 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
335 vgic_reg_access(mmio, ®, word_offset,
336 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
343 static bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu,
344 struct kvm_exit_mmio *mmio, phys_addr_t offset)
346 vgic_reg_access(mmio, NULL, offset,
347 ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
351 static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu,
352 struct kvm_exit_mmio *mmio,
355 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
356 vcpu->vcpu_id, offset);
357 vgic_reg_access(mmio, reg, offset,
358 ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
359 if (mmio->is_write) {
360 vgic_update_state(vcpu->kvm);
367 static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu,
368 struct kvm_exit_mmio *mmio,
371 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
372 vcpu->vcpu_id, offset);
373 vgic_reg_access(mmio, reg, offset,
374 ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
375 if (mmio->is_write) {
376 if (offset < 4) /* Force SGI enabled */
378 vgic_retire_disabled_irqs(vcpu);
379 vgic_update_state(vcpu->kvm);
386 static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu,
387 struct kvm_exit_mmio *mmio,
390 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
391 vcpu->vcpu_id, offset);
392 vgic_reg_access(mmio, reg, offset,
393 ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
394 if (mmio->is_write) {
395 vgic_update_state(vcpu->kvm);
402 static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu,
403 struct kvm_exit_mmio *mmio,
406 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
407 vcpu->vcpu_id, offset);
408 vgic_reg_access(mmio, reg, offset,
409 ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
410 if (mmio->is_write) {
411 vgic_update_state(vcpu->kvm);
418 static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu,
419 struct kvm_exit_mmio *mmio,
422 u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority,
423 vcpu->vcpu_id, offset);
424 vgic_reg_access(mmio, reg, offset,
425 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
429 #define GICD_ITARGETSR_SIZE 32
430 #define GICD_CPUTARGETS_BITS 8
431 #define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS)
432 static u32 vgic_get_target_reg(struct kvm *kvm, int irq)
434 struct vgic_dist *dist = &kvm->arch.vgic;
438 irq -= VGIC_NR_PRIVATE_IRQS;
440 for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++)
441 val |= 1 << (dist->irq_spi_cpu[irq + i] + i * 8);
446 static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq)
448 struct vgic_dist *dist = &kvm->arch.vgic;
449 struct kvm_vcpu *vcpu;
454 irq -= VGIC_NR_PRIVATE_IRQS;
457 * Pick the LSB in each byte. This ensures we target exactly
458 * one vcpu per IRQ. If the byte is null, assume we target
461 for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) {
462 int shift = i * GICD_CPUTARGETS_BITS;
463 target = ffs((val >> shift) & 0xffU);
464 target = target ? (target - 1) : 0;
465 dist->irq_spi_cpu[irq + i] = target;
466 kvm_for_each_vcpu(c, vcpu, kvm) {
467 bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]);
469 set_bit(irq + i, bmap);
471 clear_bit(irq + i, bmap);
476 static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu,
477 struct kvm_exit_mmio *mmio,
482 /* We treat the banked interrupts targets as read-only */
484 u32 roreg = 1 << vcpu->vcpu_id;
486 roreg |= roreg << 16;
488 vgic_reg_access(mmio, &roreg, offset,
489 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
493 reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U);
494 vgic_reg_access(mmio, ®, offset,
495 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
496 if (mmio->is_write) {
497 vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U);
498 vgic_update_state(vcpu->kvm);
505 static u32 vgic_cfg_expand(u16 val)
511 * Turn a 16bit value like abcd...mnop into a 32bit word
512 * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
514 for (i = 0; i < 16; i++)
515 res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1);
520 static u16 vgic_cfg_compress(u32 val)
526 * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
527 * abcd...mnop which is what we really care about.
529 for (i = 0; i < 16; i++)
530 res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i;
536 * The distributor uses 2 bits per IRQ for the CFG register, but the
537 * LSB is always 0. As such, we only keep the upper bit, and use the
538 * two above functions to compress/expand the bits
540 static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu,
541 struct kvm_exit_mmio *mmio, phys_addr_t offset)
544 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,
545 vcpu->vcpu_id, offset >> 1);
551 val = vgic_cfg_expand(val);
552 vgic_reg_access(mmio, &val, offset,
553 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
554 if (mmio->is_write) {
556 *reg = ~0U; /* Force PPIs/SGIs to 1 */
560 val = vgic_cfg_compress(val);
565 *reg &= 0xffff << 16;
573 static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu,
574 struct kvm_exit_mmio *mmio, phys_addr_t offset)
577 vgic_reg_access(mmio, ®, offset,
578 ACCESS_READ_RAZ | ACCESS_WRITE_VALUE);
579 if (mmio->is_write) {
580 vgic_dispatch_sgi(vcpu, reg);
581 vgic_update_state(vcpu->kvm);
589 * I would have liked to use the kvm_bus_io_*() API instead, but it
590 * cannot cope with banked registers (only the VM pointer is passed
591 * around, and we need the vcpu). One of these days, someone please
597 bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
601 static const struct mmio_range vgic_ranges[] = {
603 .base = GIC_DIST_CTRL,
605 .handle_mmio = handle_mmio_misc,
608 .base = GIC_DIST_IGROUP,
609 .len = VGIC_NR_IRQS / 8,
610 .handle_mmio = handle_mmio_raz_wi,
613 .base = GIC_DIST_ENABLE_SET,
614 .len = VGIC_NR_IRQS / 8,
615 .handle_mmio = handle_mmio_set_enable_reg,
618 .base = GIC_DIST_ENABLE_CLEAR,
619 .len = VGIC_NR_IRQS / 8,
620 .handle_mmio = handle_mmio_clear_enable_reg,
623 .base = GIC_DIST_PENDING_SET,
624 .len = VGIC_NR_IRQS / 8,
625 .handle_mmio = handle_mmio_set_pending_reg,
628 .base = GIC_DIST_PENDING_CLEAR,
629 .len = VGIC_NR_IRQS / 8,
630 .handle_mmio = handle_mmio_clear_pending_reg,
633 .base = GIC_DIST_ACTIVE_SET,
634 .len = VGIC_NR_IRQS / 8,
635 .handle_mmio = handle_mmio_raz_wi,
638 .base = GIC_DIST_ACTIVE_CLEAR,
639 .len = VGIC_NR_IRQS / 8,
640 .handle_mmio = handle_mmio_raz_wi,
643 .base = GIC_DIST_PRI,
645 .handle_mmio = handle_mmio_priority_reg,
648 .base = GIC_DIST_TARGET,
650 .handle_mmio = handle_mmio_target_reg,
653 .base = GIC_DIST_CONFIG,
654 .len = VGIC_NR_IRQS / 4,
655 .handle_mmio = handle_mmio_cfg_reg,
658 .base = GIC_DIST_SOFTINT,
660 .handle_mmio = handle_mmio_sgi_reg,
666 struct mmio_range *find_matching_range(const struct mmio_range *ranges,
667 struct kvm_exit_mmio *mmio,
670 const struct mmio_range *r = ranges;
671 phys_addr_t addr = mmio->phys_addr - base;
674 if (addr >= r->base &&
675 (addr + mmio->len) <= (r->base + r->len))
684 * vgic_handle_mmio - handle an in-kernel MMIO access
685 * @vcpu: pointer to the vcpu performing the access
686 * @run: pointer to the kvm_run structure
687 * @mmio: pointer to the data describing the access
689 * returns true if the MMIO access has been performed in kernel space,
690 * and false if it needs to be emulated in user space.
692 bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
693 struct kvm_exit_mmio *mmio)
695 const struct mmio_range *range;
696 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
697 unsigned long base = dist->vgic_dist_base;
699 unsigned long offset;
701 if (!irqchip_in_kernel(vcpu->kvm) ||
702 mmio->phys_addr < base ||
703 (mmio->phys_addr + mmio->len) > (base + KVM_VGIC_V2_DIST_SIZE))
706 /* We don't support ldrd / strd or ldm / stm to the emulated vgic */
708 kvm_inject_dabt(vcpu, mmio->phys_addr);
712 range = find_matching_range(vgic_ranges, mmio, base);
713 if (unlikely(!range || !range->handle_mmio)) {
714 pr_warn("Unhandled access %d %08llx %d\n",
715 mmio->is_write, mmio->phys_addr, mmio->len);
719 spin_lock(&vcpu->kvm->arch.vgic.lock);
720 offset = mmio->phys_addr - range->base - base;
721 updated_state = range->handle_mmio(vcpu, mmio, offset);
722 spin_unlock(&vcpu->kvm->arch.vgic.lock);
723 kvm_prepare_mmio(run, mmio);
724 kvm_handle_mmio_return(vcpu, run);
727 vgic_kick_vcpus(vcpu->kvm);
732 static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg)
734 struct kvm *kvm = vcpu->kvm;
735 struct vgic_dist *dist = &kvm->arch.vgic;
736 int nrcpus = atomic_read(&kvm->online_vcpus);
738 int sgi, mode, c, vcpu_id;
740 vcpu_id = vcpu->vcpu_id;
743 target_cpus = (reg >> 16) & 0xff;
744 mode = (reg >> 24) & 3;
752 target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff;
756 target_cpus = 1 << vcpu_id;
760 kvm_for_each_vcpu(c, vcpu, kvm) {
761 if (target_cpus & 1) {
762 /* Flag the SGI as pending */
763 vgic_dist_irq_set(vcpu, sgi);
764 dist->irq_sgi_sources[c][sgi] |= 1 << vcpu_id;
765 kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c);
772 static int compute_pending_for_cpu(struct kvm_vcpu *vcpu)
774 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
775 unsigned long *pending, *enabled, *pend_percpu, *pend_shared;
776 unsigned long pending_private, pending_shared;
779 vcpu_id = vcpu->vcpu_id;
780 pend_percpu = vcpu->arch.vgic_cpu.pending_percpu;
781 pend_shared = vcpu->arch.vgic_cpu.pending_shared;
783 pending = vgic_bitmap_get_cpu_map(&dist->irq_state, vcpu_id);
784 enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
785 bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS);
787 pending = vgic_bitmap_get_shared_map(&dist->irq_state);
788 enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
789 bitmap_and(pend_shared, pending, enabled, VGIC_NR_SHARED_IRQS);
790 bitmap_and(pend_shared, pend_shared,
791 vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
792 VGIC_NR_SHARED_IRQS);
794 pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS);
795 pending_shared = find_first_bit(pend_shared, VGIC_NR_SHARED_IRQS);
796 return (pending_private < VGIC_NR_PRIVATE_IRQS ||
797 pending_shared < VGIC_NR_SHARED_IRQS);
801 * Update the interrupt state and determine which CPUs have pending
802 * interrupts. Must be called with distributor lock held.
804 static void vgic_update_state(struct kvm *kvm)
806 struct vgic_dist *dist = &kvm->arch.vgic;
807 struct kvm_vcpu *vcpu;
810 if (!dist->enabled) {
811 set_bit(0, &dist->irq_pending_on_cpu);
815 kvm_for_each_vcpu(c, vcpu, kvm) {
816 if (compute_pending_for_cpu(vcpu)) {
817 pr_debug("CPU%d has pending interrupts\n", c);
818 set_bit(c, &dist->irq_pending_on_cpu);
823 #define LR_CPUID(lr) \
824 (((lr) & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT)
825 #define MK_LR_PEND(src, irq) \
826 (GICH_LR_PENDING_BIT | ((src) << GICH_LR_PHYSID_CPUID_SHIFT) | (irq))
829 * An interrupt may have been disabled after being made pending on the
830 * CPU interface (the classic case is a timer running while we're
831 * rebooting the guest - the interrupt would kick as soon as the CPU
832 * interface gets enabled, with deadly consequences).
834 * The solution is to examine already active LRs, and check the
835 * interrupt is still enabled. If not, just retire it.
837 static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu)
839 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
842 for_each_set_bit(lr, vgic_cpu->lr_used, vgic_cpu->nr_lr) {
843 int irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
845 if (!vgic_irq_is_enabled(vcpu, irq)) {
846 vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
847 clear_bit(lr, vgic_cpu->lr_used);
848 vgic_cpu->vgic_lr[lr] &= ~GICH_LR_STATE;
849 if (vgic_irq_is_active(vcpu, irq))
850 vgic_irq_clear_active(vcpu, irq);
856 * Queue an interrupt to a CPU virtual interface. Return true on success,
857 * or false if it wasn't possible to queue it.
859 static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
861 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
864 /* Sanitize the input... */
865 BUG_ON(sgi_source_id & ~7);
866 BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS);
867 BUG_ON(irq >= VGIC_NR_IRQS);
869 kvm_debug("Queue IRQ%d\n", irq);
871 lr = vgic_cpu->vgic_irq_lr_map[irq];
873 /* Do we have an active interrupt for the same CPUID? */
874 if (lr != LR_EMPTY &&
875 (LR_CPUID(vgic_cpu->vgic_lr[lr]) == sgi_source_id)) {
876 kvm_debug("LR%d piggyback for IRQ%d %x\n",
877 lr, irq, vgic_cpu->vgic_lr[lr]);
878 BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
879 vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT;
883 /* Try to use another LR for this interrupt */
884 lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used,
886 if (lr >= vgic_cpu->nr_lr)
889 kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id);
890 vgic_cpu->vgic_lr[lr] = MK_LR_PEND(sgi_source_id, irq);
891 vgic_cpu->vgic_irq_lr_map[irq] = lr;
892 set_bit(lr, vgic_cpu->lr_used);
894 if (!vgic_irq_is_edge(vcpu, irq))
895 vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI;
900 static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq)
902 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
903 unsigned long sources;
904 int vcpu_id = vcpu->vcpu_id;
907 sources = dist->irq_sgi_sources[vcpu_id][irq];
909 for_each_set_bit(c, &sources, VGIC_MAX_CPUS) {
910 if (vgic_queue_irq(vcpu, c, irq))
911 clear_bit(c, &sources);
914 dist->irq_sgi_sources[vcpu_id][irq] = sources;
917 * If the sources bitmap has been cleared it means that we
918 * could queue all the SGIs onto link registers (see the
919 * clear_bit above), and therefore we are done with them in
920 * our emulated gic and can get rid of them.
923 vgic_dist_irq_clear(vcpu, irq);
924 vgic_cpu_irq_clear(vcpu, irq);
931 static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq)
933 if (vgic_irq_is_active(vcpu, irq))
934 return true; /* level interrupt, already queued */
936 if (vgic_queue_irq(vcpu, 0, irq)) {
937 if (vgic_irq_is_edge(vcpu, irq)) {
938 vgic_dist_irq_clear(vcpu, irq);
939 vgic_cpu_irq_clear(vcpu, irq);
941 vgic_irq_set_active(vcpu, irq);
951 * Fill the list registers with pending interrupts before running the
954 static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
956 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
957 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
961 vcpu_id = vcpu->vcpu_id;
964 * We may not have any pending interrupt, or the interrupts
965 * may have been serviced from another vcpu. In all cases,
968 if (!kvm_vgic_vcpu_pending_irq(vcpu)) {
969 pr_debug("CPU%d has no pending interrupt\n", vcpu_id);
974 for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) {
975 if (!vgic_queue_sgi(vcpu, i))
980 for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) {
981 if (!vgic_queue_hwirq(vcpu, i))
986 for_each_set_bit(i, vgic_cpu->pending_shared, VGIC_NR_SHARED_IRQS) {
987 if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS))
993 vgic_cpu->vgic_hcr |= GICH_HCR_UIE;
995 vgic_cpu->vgic_hcr &= ~GICH_HCR_UIE;
997 * We're about to run this VCPU, and we've consumed
998 * everything the distributor had in store for
999 * us. Claim we don't have anything pending. We'll
1000 * adjust that if needed while exiting.
1002 clear_bit(vcpu_id, &dist->irq_pending_on_cpu);
1006 static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
1008 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1009 bool level_pending = false;
1011 kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr);
1013 if (vgic_cpu->vgic_misr & GICH_MISR_EOI) {
1015 * Some level interrupts have been EOIed. Clear their
1020 for_each_set_bit(lr, (unsigned long *)vgic_cpu->vgic_eisr,
1022 irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
1024 vgic_irq_clear_active(vcpu, irq);
1025 vgic_cpu->vgic_lr[lr] &= ~GICH_LR_EOI;
1027 /* Any additional pending interrupt? */
1028 if (vgic_dist_irq_is_pending(vcpu, irq)) {
1029 vgic_cpu_irq_set(vcpu, irq);
1030 level_pending = true;
1032 vgic_cpu_irq_clear(vcpu, irq);
1036 * Despite being EOIed, the LR may not have
1037 * been marked as empty.
1039 set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr);
1040 vgic_cpu->vgic_lr[lr] &= ~GICH_LR_ACTIVE_BIT;
1044 if (vgic_cpu->vgic_misr & GICH_MISR_U)
1045 vgic_cpu->vgic_hcr &= ~GICH_HCR_UIE;
1047 return level_pending;
1051 * Sync back the VGIC state after a guest run. The distributor lock is
1052 * needed so we don't get preempted in the middle of the state processing.
1054 static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1056 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1057 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1061 level_pending = vgic_process_maintenance(vcpu);
1063 /* Clear mappings for empty LRs */
1064 for_each_set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr,
1068 if (!test_and_clear_bit(lr, vgic_cpu->lr_used))
1071 irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
1073 BUG_ON(irq >= VGIC_NR_IRQS);
1074 vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
1077 /* Check if we still have something up our sleeve... */
1078 pending = find_first_zero_bit((unsigned long *)vgic_cpu->vgic_elrsr,
1080 if (level_pending || pending < vgic_cpu->nr_lr)
1081 set_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
1084 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1086 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1088 if (!irqchip_in_kernel(vcpu->kvm))
1091 spin_lock(&dist->lock);
1092 __kvm_vgic_flush_hwstate(vcpu);
1093 spin_unlock(&dist->lock);
1096 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1098 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1100 if (!irqchip_in_kernel(vcpu->kvm))
1103 spin_lock(&dist->lock);
1104 __kvm_vgic_sync_hwstate(vcpu);
1105 spin_unlock(&dist->lock);
1108 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
1110 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1112 if (!irqchip_in_kernel(vcpu->kvm))
1115 return test_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
1118 static void vgic_kick_vcpus(struct kvm *kvm)
1120 struct kvm_vcpu *vcpu;
1124 * We've injected an interrupt, time to find out who deserves
1127 kvm_for_each_vcpu(c, vcpu, kvm) {
1128 if (kvm_vgic_vcpu_pending_irq(vcpu))
1129 kvm_vcpu_kick(vcpu);
1133 static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level)
1135 int is_edge = vgic_irq_is_edge(vcpu, irq);
1136 int state = vgic_dist_irq_is_pending(vcpu, irq);
1139 * Only inject an interrupt if:
1140 * - edge triggered and we have a rising edge
1141 * - level triggered and we change level
1144 return level > state;
1146 return level != state;
1149 static bool vgic_update_irq_state(struct kvm *kvm, int cpuid,
1150 unsigned int irq_num, bool level)
1152 struct vgic_dist *dist = &kvm->arch.vgic;
1153 struct kvm_vcpu *vcpu;
1154 int is_edge, is_level;
1158 spin_lock(&dist->lock);
1160 vcpu = kvm_get_vcpu(kvm, cpuid);
1161 is_edge = vgic_irq_is_edge(vcpu, irq_num);
1162 is_level = !is_edge;
1164 if (!vgic_validate_injection(vcpu, irq_num, level)) {
1169 if (irq_num >= VGIC_NR_PRIVATE_IRQS) {
1170 cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS];
1171 vcpu = kvm_get_vcpu(kvm, cpuid);
1174 kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid);
1177 vgic_dist_irq_set(vcpu, irq_num);
1179 vgic_dist_irq_clear(vcpu, irq_num);
1181 enabled = vgic_irq_is_enabled(vcpu, irq_num);
1188 if (is_level && vgic_irq_is_active(vcpu, irq_num)) {
1190 * Level interrupt in progress, will be picked up
1198 vgic_cpu_irq_set(vcpu, irq_num);
1199 set_bit(cpuid, &dist->irq_pending_on_cpu);
1203 spin_unlock(&dist->lock);
1209 * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
1210 * @kvm: The VM structure pointer
1211 * @cpuid: The CPU for PPIs
1212 * @irq_num: The IRQ number that is assigned to the device
1213 * @level: Edge-triggered: true: to trigger the interrupt
1214 * false: to ignore the call
1215 * Level-sensitive true: activates an interrupt
1216 * false: deactivates an interrupt
1218 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1219 * level-sensitive interrupts. You can think of the level parameter as 1
1220 * being HIGH and 0 being LOW and all devices being active-HIGH.
1222 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
1225 if (vgic_update_irq_state(kvm, cpuid, irq_num, level))
1226 vgic_kick_vcpus(kvm);
1231 static irqreturn_t vgic_maintenance_handler(int irq, void *data)
1234 * We cannot rely on the vgic maintenance interrupt to be
1235 * delivered synchronously. This means we can only use it to
1236 * exit the VM, and we perform the handling of EOIed
1237 * interrupts on the exit path (see vgic_process_maintenance).
1242 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
1244 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1245 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1248 if (!irqchip_in_kernel(vcpu->kvm))
1251 if (vcpu->vcpu_id >= VGIC_MAX_CPUS)
1254 for (i = 0; i < VGIC_NR_IRQS; i++) {
1255 if (i < VGIC_NR_PPIS)
1256 vgic_bitmap_set_irq_val(&dist->irq_enabled,
1257 vcpu->vcpu_id, i, 1);
1258 if (i < VGIC_NR_PRIVATE_IRQS)
1259 vgic_bitmap_set_irq_val(&dist->irq_cfg,
1260 vcpu->vcpu_id, i, VGIC_CFG_EDGE);
1262 vgic_cpu->vgic_irq_lr_map[i] = LR_EMPTY;
1266 * By forcing VMCR to zero, the GIC will restore the binary
1267 * points to their reset values. Anything else resets to zero
1270 vgic_cpu->vgic_vmcr = 0;
1272 vgic_cpu->nr_lr = vgic_nr_lr;
1273 vgic_cpu->vgic_hcr = GICH_HCR_EN; /* Get the show on the road... */
1278 static void vgic_init_maintenance_interrupt(void *info)
1280 enable_percpu_irq(vgic_maint_irq, 0);
1283 static int vgic_cpu_notify(struct notifier_block *self,
1284 unsigned long action, void *cpu)
1288 case CPU_STARTING_FROZEN:
1289 vgic_init_maintenance_interrupt(NULL);
1292 case CPU_DYING_FROZEN:
1293 disable_percpu_irq(vgic_maint_irq);
1300 static struct notifier_block vgic_cpu_nb = {
1301 .notifier_call = vgic_cpu_notify,
1304 int kvm_vgic_hyp_init(void)
1307 struct resource vctrl_res;
1308 struct resource vcpu_res;
1310 vgic_node = of_find_compatible_node(NULL, NULL, "arm,cortex-a15-gic");
1312 kvm_err("error: no compatible vgic node in DT\n");
1316 vgic_maint_irq = irq_of_parse_and_map(vgic_node, 0);
1317 if (!vgic_maint_irq) {
1318 kvm_err("error getting vgic maintenance irq from DT\n");
1323 ret = request_percpu_irq(vgic_maint_irq, vgic_maintenance_handler,
1324 "vgic", kvm_get_running_vcpus());
1326 kvm_err("Cannot register interrupt %d\n", vgic_maint_irq);
1330 ret = register_cpu_notifier(&vgic_cpu_nb);
1332 kvm_err("Cannot register vgic CPU notifier\n");
1336 ret = of_address_to_resource(vgic_node, 2, &vctrl_res);
1338 kvm_err("Cannot obtain VCTRL resource\n");
1342 vgic_vctrl_base = of_iomap(vgic_node, 2);
1343 if (!vgic_vctrl_base) {
1344 kvm_err("Cannot ioremap VCTRL\n");
1349 vgic_nr_lr = readl_relaxed(vgic_vctrl_base + GICH_VTR);
1350 vgic_nr_lr = (vgic_nr_lr & 0x3f) + 1;
1352 ret = create_hyp_io_mappings(vgic_vctrl_base,
1353 vgic_vctrl_base + resource_size(&vctrl_res),
1356 kvm_err("Cannot map VCTRL into hyp\n");
1360 kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
1361 vctrl_res.start, vgic_maint_irq);
1362 on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1);
1364 if (of_address_to_resource(vgic_node, 3, &vcpu_res)) {
1365 kvm_err("Cannot obtain VCPU resource\n");
1369 vgic_vcpu_base = vcpu_res.start;
1374 iounmap(vgic_vctrl_base);
1376 free_percpu_irq(vgic_maint_irq, kvm_get_running_vcpus());
1378 of_node_put(vgic_node);
1382 int kvm_vgic_init(struct kvm *kvm)
1386 mutex_lock(&kvm->lock);
1388 if (vgic_initialized(kvm))
1391 if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) ||
1392 IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) {
1393 kvm_err("Need to set vgic cpu and dist addresses first\n");
1398 ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base,
1399 vgic_vcpu_base, KVM_VGIC_V2_CPU_SIZE);
1401 kvm_err("Unable to remap VGIC CPU to VCPU\n");
1405 for (i = VGIC_NR_PRIVATE_IRQS; i < VGIC_NR_IRQS; i += 4)
1406 vgic_set_target_reg(kvm, 0, i);
1408 kvm_timer_init(kvm);
1409 kvm->arch.vgic.ready = true;
1411 mutex_unlock(&kvm->lock);
1415 int kvm_vgic_create(struct kvm *kvm)
1419 mutex_lock(&kvm->lock);
1421 if (atomic_read(&kvm->online_vcpus) || kvm->arch.vgic.vctrl_base) {
1426 spin_lock_init(&kvm->arch.vgic.lock);
1427 kvm->arch.vgic.vctrl_base = vgic_vctrl_base;
1428 kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF;
1429 kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF;
1432 mutex_unlock(&kvm->lock);
1436 static bool vgic_ioaddr_overlap(struct kvm *kvm)
1438 phys_addr_t dist = kvm->arch.vgic.vgic_dist_base;
1439 phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base;
1441 if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu))
1443 if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) ||
1444 (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist))
1449 static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr,
1450 phys_addr_t addr, phys_addr_t size)
1454 if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
1456 if (addr + size < addr)
1459 ret = vgic_ioaddr_overlap(kvm);
1466 int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
1469 struct vgic_dist *vgic = &kvm->arch.vgic;
1471 if (addr & ~KVM_PHYS_MASK)
1474 if (addr & (SZ_4K - 1))
1477 mutex_lock(&kvm->lock);
1479 case KVM_VGIC_V2_ADDR_TYPE_DIST:
1480 r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base,
1481 addr, KVM_VGIC_V2_DIST_SIZE);
1483 case KVM_VGIC_V2_ADDR_TYPE_CPU:
1484 r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base,
1485 addr, KVM_VGIC_V2_CPU_SIZE);
1491 mutex_unlock(&kvm->lock);