2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 #include <linux/irqchip/arm-gic-v3.h>
16 #include <linux/kvm.h>
17 #include <linux/kvm_host.h>
18 #include <kvm/arm_vgic.h>
19 #include <asm/kvm_mmu.h>
20 #include <asm/kvm_asm.h>
24 static bool group0_trap;
25 static bool group1_trap;
26 static bool common_trap;
28 void vgic_v3_set_npie(struct kvm_vcpu *vcpu)
30 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
32 cpuif->vgic_hcr |= ICH_HCR_NPIE;
35 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
37 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
39 cpuif->vgic_hcr |= ICH_HCR_UIE;
42 static bool lr_signals_eoi_mi(u64 lr_val)
44 return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) &&
45 !(lr_val & ICH_LR_HW);
48 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
50 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
51 struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3;
52 u32 model = vcpu->kvm->arch.vgic.vgic_model;
55 cpuif->vgic_hcr &= ~(ICH_HCR_UIE | ICH_HCR_NPIE);
57 for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
58 u64 val = cpuif->vgic_lr[lr];
62 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
63 intid = val & ICH_LR_VIRTUAL_ID_MASK;
65 intid = val & GICH_LR_VIRTUALID;
67 /* Notify fds when the guest EOI'ed a level-triggered IRQ */
68 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
69 kvm_notify_acked_irq(vcpu->kvm, 0,
70 intid - VGIC_NR_PRIVATE_IRQS);
72 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
73 if (!irq) /* An LPI could have been unmapped. */
76 spin_lock(&irq->irq_lock);
78 /* Always preserve the active bit */
79 irq->active = !!(val & ICH_LR_ACTIVE_BIT);
81 /* Edge is the only case where we preserve the pending bit */
82 if (irq->config == VGIC_CONFIG_EDGE &&
83 (val & ICH_LR_PENDING_BIT)) {
84 irq->pending_latch = true;
86 if (vgic_irq_is_sgi(intid) &&
87 model == KVM_DEV_TYPE_ARM_VGIC_V2) {
88 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
90 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
91 irq->source |= (1 << cpuid);
96 * Clear soft pending state when level irqs have been acked.
97 * Always regenerate the pending state.
99 if (irq->config == VGIC_CONFIG_LEVEL) {
100 if (!(val & ICH_LR_PENDING_BIT))
101 irq->pending_latch = false;
104 spin_unlock(&irq->irq_lock);
105 vgic_put_irq(vcpu->kvm, irq);
108 vgic_cpu->used_lrs = 0;
111 /* Requires the irq to be locked already */
112 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
114 u32 model = vcpu->kvm->arch.vgic.vgic_model;
115 u64 val = irq->intid;
117 if (irq_is_pending(irq)) {
118 val |= ICH_LR_PENDING_BIT;
120 if (irq->config == VGIC_CONFIG_EDGE)
121 irq->pending_latch = false;
123 if (vgic_irq_is_sgi(irq->intid) &&
124 model == KVM_DEV_TYPE_ARM_VGIC_V2) {
125 u32 src = ffs(irq->source);
128 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
129 irq->source &= ~(1 << (src - 1));
131 irq->pending_latch = true;
136 val |= ICH_LR_ACTIVE_BIT;
140 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
142 * Never set pending+active on a HW interrupt, as the
143 * pending state is kept at the physical distributor
146 if (irq->active && irq_is_pending(irq))
147 val &= ~ICH_LR_PENDING_BIT;
149 if (irq->config == VGIC_CONFIG_LEVEL)
154 * We currently only support Group1 interrupts, which is a
155 * known defect. This needs to be addressed at some point.
157 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
160 val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
162 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
165 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
167 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
170 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
172 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
173 u32 model = vcpu->kvm->arch.vgic.vgic_model;
176 if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
177 vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) &
178 ICH_VMCR_ACK_CTL_MASK;
179 vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) &
180 ICH_VMCR_FIQ_EN_MASK;
183 * When emulating GICv3 on GICv3 with SRE=1 on the
184 * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
186 vmcr = ICH_VMCR_FIQ_EN_MASK;
189 vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
190 vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
191 vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
192 vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
193 vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
194 vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
195 vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
197 cpu_if->vgic_vmcr = vmcr;
200 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
202 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
203 u32 model = vcpu->kvm->arch.vgic.vgic_model;
206 vmcr = cpu_if->vgic_vmcr;
208 if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
209 vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >>
210 ICH_VMCR_ACK_CTL_SHIFT;
211 vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >>
212 ICH_VMCR_FIQ_EN_SHIFT;
215 * When emulating GICv3 on GICv3 with SRE=1 on the
216 * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
222 vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
223 vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT;
224 vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
225 vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
226 vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
227 vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
228 vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
231 #define INITIAL_PENDBASER_VALUE \
232 (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) | \
233 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner) | \
234 GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
236 void vgic_v3_enable(struct kvm_vcpu *vcpu)
238 struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
241 * By forcing VMCR to zero, the GIC will restore the binary
242 * points to their reset values. Anything else resets to zero
245 vgic_v3->vgic_vmcr = 0;
246 vgic_v3->vgic_elrsr = ~0;
249 * If we are emulating a GICv3, we do it in an non-GICv2-compatible
250 * way, so we force SRE to 1 to demonstrate this to the guest.
251 * Also, we don't support any form of IRQ/FIQ bypass.
252 * This goes with the spec allowing the value to be RAO/WI.
254 if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
255 vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
258 vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
260 vgic_v3->vgic_sre = 0;
263 vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
264 ICH_VTR_ID_BITS_MASK) >>
265 ICH_VTR_ID_BITS_SHIFT;
266 vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
267 ICH_VTR_PRI_BITS_MASK) >>
268 ICH_VTR_PRI_BITS_SHIFT) + 1;
270 /* Get the show on the road... */
271 vgic_v3->vgic_hcr = ICH_HCR_EN;
273 vgic_v3->vgic_hcr |= ICH_HCR_TALL0;
275 vgic_v3->vgic_hcr |= ICH_HCR_TALL1;
277 vgic_v3->vgic_hcr |= ICH_HCR_TC;
280 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
282 struct kvm_vcpu *vcpu;
283 int byte_offset, bit_nr;
290 vcpu = irq->target_vcpu;
294 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
296 byte_offset = irq->intid / BITS_PER_BYTE;
297 bit_nr = irq->intid % BITS_PER_BYTE;
298 ptr = pendbase + byte_offset;
300 ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
304 status = val & (1 << bit_nr);
306 spin_lock(&irq->irq_lock);
307 if (irq->target_vcpu != vcpu) {
308 spin_unlock(&irq->irq_lock);
311 irq->pending_latch = status;
312 vgic_queue_irq_unlock(vcpu->kvm, irq);
315 /* clear consumed data */
316 val &= ~(1 << bit_nr);
317 ret = kvm_write_guest(kvm, ptr, &val, 1);
325 * vgic_its_save_pending_tables - Save the pending tables into guest RAM
326 * kvm lock and all vcpu lock must be held
328 int vgic_v3_save_pending_tables(struct kvm *kvm)
330 struct vgic_dist *dist = &kvm->arch.vgic;
331 int last_byte_offset = -1;
332 struct vgic_irq *irq;
336 list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
337 int byte_offset, bit_nr;
338 struct kvm_vcpu *vcpu;
342 vcpu = irq->target_vcpu;
346 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
348 byte_offset = irq->intid / BITS_PER_BYTE;
349 bit_nr = irq->intid % BITS_PER_BYTE;
350 ptr = pendbase + byte_offset;
352 if (byte_offset != last_byte_offset) {
353 ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
356 last_byte_offset = byte_offset;
359 stored = val & (1U << bit_nr);
360 if (stored == irq->pending_latch)
363 if (irq->pending_latch)
366 val &= ~(1 << bit_nr);
368 ret = kvm_write_guest(kvm, ptr, &val, 1);
376 * Check for overlapping regions and for regions crossing the end of memory
377 * for base addresses which have already been set.
379 bool vgic_v3_check_base(struct kvm *kvm)
381 struct vgic_dist *d = &kvm->arch.vgic;
382 gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;
384 redist_size *= atomic_read(&kvm->online_vcpus);
386 if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
387 d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
390 if (!IS_VGIC_ADDR_UNDEF(d->vgic_redist_base) &&
391 d->vgic_redist_base + redist_size < d->vgic_redist_base)
394 /* Both base addresses must be set to check if they overlap */
395 if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) ||
396 IS_VGIC_ADDR_UNDEF(d->vgic_redist_base))
399 if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
401 if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
407 int vgic_v3_map_resources(struct kvm *kvm)
410 struct vgic_dist *dist = &kvm->arch.vgic;
415 if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
416 IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
417 kvm_err("Need to set vgic distributor addresses first\n");
422 if (!vgic_v3_check_base(kvm)) {
423 kvm_err("VGIC redist and dist frames overlap\n");
429 * For a VGICv3 we require the userland to explicitly initialize
430 * the VGIC before we need to use it.
432 if (!vgic_initialized(kvm)) {
437 ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
439 kvm_err("Unable to register VGICv3 dist MMIO regions\n");
449 DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap);
451 static int __init early_group0_trap_cfg(char *buf)
453 return strtobool(buf, &group0_trap);
455 early_param("kvm-arm.vgic_v3_group0_trap", early_group0_trap_cfg);
457 static int __init early_group1_trap_cfg(char *buf)
459 return strtobool(buf, &group1_trap);
461 early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg);
463 static int __init early_common_trap_cfg(char *buf)
465 return strtobool(buf, &common_trap);
467 early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg);
470 * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
471 * @node: pointer to the DT node
473 * Returns 0 if a GICv3 has been found, returns an error code otherwise
475 int vgic_v3_probe(const struct gic_kvm_info *info)
477 u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
481 * The ListRegs field is 5 bits, but there is a architectural
482 * maximum of 16 list registers. Just ignore bit 4...
484 kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
485 kvm_vgic_global_state.can_emulate_gicv2 = false;
486 kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
488 if (!info->vcpu.start) {
489 kvm_info("GICv3: no GICV resource entry\n");
490 kvm_vgic_global_state.vcpu_base = 0;
491 } else if (!PAGE_ALIGNED(info->vcpu.start)) {
492 pr_warn("GICV physical address 0x%llx not page aligned\n",
493 (unsigned long long)info->vcpu.start);
494 kvm_vgic_global_state.vcpu_base = 0;
496 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
497 kvm_vgic_global_state.can_emulate_gicv2 = true;
498 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
500 kvm_err("Cannot register GICv2 KVM device.\n");
503 kvm_info("vgic-v2@%llx\n", info->vcpu.start);
505 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
507 kvm_err("Cannot register GICv3 KVM device.\n");
508 kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
512 if (kvm_vgic_global_state.vcpu_base == 0)
513 kvm_info("disabling GICv2 emulation\n");
516 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_30115)) {
522 if (group0_trap || group1_trap || common_trap) {
523 kvm_info("GICv3 sysreg trapping enabled ([%s%s%s], reduced performance)\n",
524 group0_trap ? "G0" : "",
525 group1_trap ? "G1" : "",
526 common_trap ? "C" : "");
527 static_branch_enable(&vgic_v3_cpuif_trap);
530 kvm_vgic_global_state.vctrl_base = NULL;
531 kvm_vgic_global_state.type = VGIC_V3;
532 kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
537 void vgic_v3_load(struct kvm_vcpu *vcpu)
539 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
542 * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen
543 * is dependent on ICC_SRE_EL1.SRE, and we have to perform the
544 * VMCR_EL2 save/restore in the world switch.
546 if (likely(cpu_if->vgic_sre))
547 kvm_call_hyp(__vgic_v3_write_vmcr, cpu_if->vgic_vmcr);
550 void vgic_v3_put(struct kvm_vcpu *vcpu)
552 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
554 if (likely(cpu_if->vgic_sre))
555 cpu_if->vgic_vmcr = kvm_call_hyp(__vgic_v3_read_vmcr);