virt/kvm/arm/vgic/vgic-v3.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program. If not, see <http://www.gnu.org/licenses/>.
  13  */
  14
  15 #include <linux/irqchip/arm-gic-v3.h>
  16 #include <linux/kvm.h>
  17 #include <linux/kvm_host.h>
  18 #include <kvm/arm_vgic.h>
  19 #include <asm/kvm_mmu.h>
  20 #include <asm/kvm_asm.h>
  21
  22 #include "vgic.h"
  23
  24 static bool group0_trap;
  25 static bool group1_trap;
  26 static bool common_trap;
  27
  28 void vgic_v3_set_npie(struct kvm_vcpu *vcpu)
  29 {
  30         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
  31
  32         cpuif->vgic_hcr |= ICH_HCR_NPIE;
  33 }
  34
  35 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
  36 {
  37         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
  38
  39         cpuif->vgic_hcr |= ICH_HCR_UIE;
  40 }
  41
  42 static bool lr_signals_eoi_mi(u64 lr_val)
  43 {
  44         return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) &&
  45                !(lr_val & ICH_LR_HW);
  46 }
  47
  48 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
  49 {
  50         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
  51         struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3;
  52         u32 model = vcpu->kvm->arch.vgic.vgic_model;
  53         int lr;
  54
  55         cpuif->vgic_hcr &= ~(ICH_HCR_UIE | ICH_HCR_NPIE);
  56
  57         for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
  58                 u64 val = cpuif->vgic_lr[lr];
  59                 u32 intid;
  60                 struct vgic_irq *irq;
  61
  62                 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
  63                         intid = val & ICH_LR_VIRTUAL_ID_MASK;
  64                 else
  65                         intid = val & GICH_LR_VIRTUALID;
  66
  67                 /* Notify fds when the guest EOI'ed a level-triggered IRQ */
  68                 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
  69                         kvm_notify_acked_irq(vcpu->kvm, 0,
  70                                              intid - VGIC_NR_PRIVATE_IRQS);
  71
  72                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
  73                 if (!irq)       /* An LPI could have been unmapped. */
  74                         continue;
  75
  76                 spin_lock(&irq->irq_lock);
  77
  78                 /* Always preserve the active bit */
  79                 irq->active = !!(val & ICH_LR_ACTIVE_BIT);
  80
  81                 /* Edge is the only case where we preserve the pending bit */
  82                 if (irq->config == VGIC_CONFIG_EDGE &&
  83                     (val & ICH_LR_PENDING_BIT)) {
  84                         irq->pending_latch = true;
  85
  86                         if (vgic_irq_is_sgi(intid) &&
  87                             model == KVM_DEV_TYPE_ARM_VGIC_V2) {
  88                                 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
  89
  90                                 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
  91                                 irq->source |= (1 << cpuid);
  92                         }
  93                 }
  94
  95                 /*
  96                  * Clear soft pending state when level irqs have been acked.
  97                  * Always regenerate the pending state.
  98                  */
  99                 if (irq->config == VGIC_CONFIG_LEVEL) {
 100                         if (!(val & ICH_LR_PENDING_BIT))
 101                                 irq->pending_latch = false;
 102                 }
 103
 104                 spin_unlock(&irq->irq_lock);
 105                 vgic_put_irq(vcpu->kvm, irq);
 106         }
 107
 108         vgic_cpu->used_lrs = 0;
 109 }
 110
 111 /* Requires the irq to be locked already */
 112 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
 113 {
 114         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 115         u64 val = irq->intid;
 116
 117         if (irq_is_pending(irq)) {
 118                 val |= ICH_LR_PENDING_BIT;
 119
 120                 if (irq->config == VGIC_CONFIG_EDGE)
 121                         irq->pending_latch = false;
 122
 123                 if (vgic_irq_is_sgi(irq->intid) &&
 124                     model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 125                         u32 src = ffs(irq->source);
 126
 127                         BUG_ON(!src);
 128                         val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 129                         irq->source &= ~(1 << (src - 1));
 130                         if (irq->source)
 131                                 irq->pending_latch = true;
 132                 }
 133         }
 134
 135         if (irq->active)
 136                 val |= ICH_LR_ACTIVE_BIT;
 137
 138         if (irq->hw) {
 139                 val |= ICH_LR_HW;
 140                 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
 141                 /*
 142                  * Never set pending+active on a HW interrupt, as the
 143                  * pending state is kept at the physical distributor
 144                  * level.
 145                  */
 146                 if (irq->active && irq_is_pending(irq))
 147                         val &= ~ICH_LR_PENDING_BIT;
 148         } else {
 149                 if (irq->config == VGIC_CONFIG_LEVEL)
 150                         val |= ICH_LR_EOI;
 151         }
 152
 153         /*
 154          * We currently only support Group1 interrupts, which is a
 155          * known defect. This needs to be addressed at some point.
 156          */
 157         if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
 158                 val |= ICH_LR_GROUP;
 159
 160         val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
 161
 162         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
 163 }
 164
 165 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
 166 {
 167         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
 168 }
 169
 170 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 171 {
 172         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 173         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 174         u32 vmcr;
 175
 176         if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 177                 vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) &
 178                         ICH_VMCR_ACK_CTL_MASK;
 179                 vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) &
 180                         ICH_VMCR_FIQ_EN_MASK;
 181         } else {
 182                 /*
 183                  * When emulating GICv3 on GICv3 with SRE=1 on the
 184                  * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
 185                  */
 186                 vmcr = ICH_VMCR_FIQ_EN_MASK;
 187         }
 188
 189         vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
 190         vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
 191         vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
 192         vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
 193         vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
 194         vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
 195         vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
 196
 197         cpu_if->vgic_vmcr = vmcr;
 198 }
 199
 200 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 201 {
 202         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 203         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 204         u32 vmcr;
 205
 206         vmcr = cpu_if->vgic_vmcr;
 207
 208         if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 209                 vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >>
 210                         ICH_VMCR_ACK_CTL_SHIFT;
 211                 vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >>
 212                         ICH_VMCR_FIQ_EN_SHIFT;
 213         } else {
 214                 /*
 215                  * When emulating GICv3 on GICv3 with SRE=1 on the
 216                  * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
 217                  */
 218                 vmcrp->fiqen = 1;
 219                 vmcrp->ackctl = 0;
 220         }
 221
 222         vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
 223         vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT;
 224         vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
 225         vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
 226         vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
 227         vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
 228         vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
 229 }
 230
 231 #define INITIAL_PENDBASER_VALUE                                           \
 232         (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb)            | \
 233         GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner)      | \
 234         GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
 235
 236 void vgic_v3_enable(struct kvm_vcpu *vcpu)
 237 {
 238         struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
 239
 240         /*
 241          * By forcing VMCR to zero, the GIC will restore the binary
 242          * points to their reset values. Anything else resets to zero
 243          * anyway.
 244          */
 245         vgic_v3->vgic_vmcr = 0;
 246         vgic_v3->vgic_elrsr = ~0;
 247
 248         /*
 249          * If we are emulating a GICv3, we do it in an non-GICv2-compatible
 250          * way, so we force SRE to 1 to demonstrate this to the guest.
 251          * Also, we don't support any form of IRQ/FIQ bypass.
 252          * This goes with the spec allowing the value to be RAO/WI.
 253          */
 254         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
 255                 vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
 256                                      ICC_SRE_EL1_DFB |
 257                                      ICC_SRE_EL1_SRE);
 258                 vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
 259         } else {
 260                 vgic_v3->vgic_sre = 0;
 261         }
 262
 263         vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
 264                                            ICH_VTR_ID_BITS_MASK) >>
 265                                            ICH_VTR_ID_BITS_SHIFT;
 266         vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
 267                                             ICH_VTR_PRI_BITS_MASK) >>
 268                                             ICH_VTR_PRI_BITS_SHIFT) + 1;
 269
 270         /* Get the show on the road... */
 271         vgic_v3->vgic_hcr = ICH_HCR_EN;
 272         if (group0_trap)
 273                 vgic_v3->vgic_hcr |= ICH_HCR_TALL0;
 274         if (group1_trap)
 275                 vgic_v3->vgic_hcr |= ICH_HCR_TALL1;
 276         if (common_trap)
 277                 vgic_v3->vgic_hcr |= ICH_HCR_TC;
 278 }
 279
 280 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
 281 {
 282         struct kvm_vcpu *vcpu;
 283         int byte_offset, bit_nr;
 284         gpa_t pendbase, ptr;
 285         bool status;
 286         u8 val;
 287         int ret;
 288
 289 retry:
 290         vcpu = irq->target_vcpu;
 291         if (!vcpu)
 292                 return 0;
 293
 294         pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
 295
 296         byte_offset = irq->intid / BITS_PER_BYTE;
 297         bit_nr = irq->intid % BITS_PER_BYTE;
 298         ptr = pendbase + byte_offset;
 299
 300         ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
 301         if (ret)
 302                 return ret;
 303
 304         status = val & (1 << bit_nr);
 305
 306         spin_lock(&irq->irq_lock);
 307         if (irq->target_vcpu != vcpu) {
 308                 spin_unlock(&irq->irq_lock);
 309                 goto retry;
 310         }
 311         irq->pending_latch = status;
 312         vgic_queue_irq_unlock(vcpu->kvm, irq);
 313
 314         if (status) {
 315                 /* clear consumed data */
 316                 val &= ~(1 << bit_nr);
 317                 ret = kvm_write_guest(kvm, ptr, &val, 1);
 318                 if (ret)
 319                         return ret;
 320         }
 321         return 0;
 322 }
 323
 324 /**
 325  * vgic_its_save_pending_tables - Save the pending tables into guest RAM
 326  * kvm lock and all vcpu lock must be held
 327  */
 328 int vgic_v3_save_pending_tables(struct kvm *kvm)
 329 {
 330         struct vgic_dist *dist = &kvm->arch.vgic;
 331         int last_byte_offset = -1;
 332         struct vgic_irq *irq;
 333         int ret;
 334         u8 val;
 335
 336         list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
 337                 int byte_offset, bit_nr;
 338                 struct kvm_vcpu *vcpu;
 339                 gpa_t pendbase, ptr;
 340                 bool stored;
 341
 342                 vcpu = irq->target_vcpu;
 343                 if (!vcpu)
 344                         continue;
 345
 346                 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
 347
 348                 byte_offset = irq->intid / BITS_PER_BYTE;
 349                 bit_nr = irq->intid % BITS_PER_BYTE;
 350                 ptr = pendbase + byte_offset;
 351
 352                 if (byte_offset != last_byte_offset) {
 353                         ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
 354                         if (ret)
 355                                 return ret;
 356                         last_byte_offset = byte_offset;
 357                 }
 358
 359                 stored = val & (1U << bit_nr);
 360                 if (stored == irq->pending_latch)
 361                         continue;
 362
 363                 if (irq->pending_latch)
 364                         val |= 1 << bit_nr;
 365                 else
 366                         val &= ~(1 << bit_nr);
 367
 368                 ret = kvm_write_guest(kvm, ptr, &val, 1);
 369                 if (ret)
 370                         return ret;
 371         }
 372         return 0;
 373 }
 374
 375 /*
 376  * Check for overlapping regions and for regions crossing the end of memory
 377  * for base addresses which have already been set.
 378  */
 379 bool vgic_v3_check_base(struct kvm *kvm)
 380 {
 381         struct vgic_dist *d = &kvm->arch.vgic;
 382         gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;
 383
 384         redist_size *= atomic_read(&kvm->online_vcpus);
 385
 386         if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
 387             d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
 388                 return false;
 389
 390         if (!IS_VGIC_ADDR_UNDEF(d->vgic_redist_base) &&
 391             d->vgic_redist_base + redist_size < d->vgic_redist_base)
 392                 return false;
 393
 394         /* Both base addresses must be set to check if they overlap */
 395         if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) ||
 396             IS_VGIC_ADDR_UNDEF(d->vgic_redist_base))
 397                 return true;
 398
 399         if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
 400                 return true;
 401         if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
 402                 return true;
 403
 404         return false;
 405 }
 406
 407 int vgic_v3_map_resources(struct kvm *kvm)
 408 {
 409         int ret = 0;
 410         struct vgic_dist *dist = &kvm->arch.vgic;
 411
 412         if (vgic_ready(kvm))
 413                 goto out;
 414
 415         if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
 416             IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
 417                 kvm_err("Need to set vgic distributor addresses first\n");
 418                 ret = -ENXIO;
 419                 goto out;
 420         }
 421
 422         if (!vgic_v3_check_base(kvm)) {
 423                 kvm_err("VGIC redist and dist frames overlap\n");
 424                 ret = -EINVAL;
 425                 goto out;
 426         }
 427
 428         /*
 429          * For a VGICv3 we require the userland to explicitly initialize
 430          * the VGIC before we need to use it.
 431          */
 432         if (!vgic_initialized(kvm)) {
 433                 ret = -EBUSY;
 434                 goto out;
 435         }
 436
 437         ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
 438         if (ret) {
 439                 kvm_err("Unable to register VGICv3 dist MMIO regions\n");
 440                 goto out;
 441         }
 442
 443         dist->ready = true;
 444
 445 out:
 446         return ret;
 447 }
 448
 449 DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap);
 450
 451 static int __init early_group0_trap_cfg(char *buf)
 452 {
 453         return strtobool(buf, &group0_trap);
 454 }
 455 early_param("kvm-arm.vgic_v3_group0_trap", early_group0_trap_cfg);
 456
 457 static int __init early_group1_trap_cfg(char *buf)
 458 {
 459         return strtobool(buf, &group1_trap);
 460 }
 461 early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg);
 462
 463 static int __init early_common_trap_cfg(char *buf)
 464 {
 465         return strtobool(buf, &common_trap);
 466 }
 467 early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg);
 468
 469 /**
 470  * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
 471  * @node:       pointer to the DT node
 472  *
 473  * Returns 0 if a GICv3 has been found, returns an error code otherwise
 474  */
 475 int vgic_v3_probe(const struct gic_kvm_info *info)
 476 {
 477         u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
 478         int ret;
 479
 480         /*
 481          * The ListRegs field is 5 bits, but there is a architectural
 482          * maximum of 16 list registers. Just ignore bit 4...
 483          */
 484         kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
 485         kvm_vgic_global_state.can_emulate_gicv2 = false;
 486         kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
 487
 488         if (!info->vcpu.start) {
 489                 kvm_info("GICv3: no GICV resource entry\n");
 490                 kvm_vgic_global_state.vcpu_base = 0;
 491         } else if (!PAGE_ALIGNED(info->vcpu.start)) {
 492                 pr_warn("GICV physical address 0x%llx not page aligned\n",
 493                         (unsigned long long)info->vcpu.start);
 494                 kvm_vgic_global_state.vcpu_base = 0;
 495         } else {
 496                 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
 497                 kvm_vgic_global_state.can_emulate_gicv2 = true;
 498                 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
 499                 if (ret) {
 500                         kvm_err("Cannot register GICv2 KVM device.\n");
 501                         return ret;
 502                 }
 503                 kvm_info("vgic-v2@%llx\n", info->vcpu.start);
 504         }
 505         ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
 506         if (ret) {
 507                 kvm_err("Cannot register GICv3 KVM device.\n");
 508                 kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
 509                 return ret;
 510         }
 511
 512         if (kvm_vgic_global_state.vcpu_base == 0)
 513                 kvm_info("disabling GICv2 emulation\n");
 514
 515 #ifdef CONFIG_ARM64
 516         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_30115)) {
 517                 group0_trap = true;
 518                 group1_trap = true;
 519         }
 520 #endif
 521
 522         if (group0_trap || group1_trap || common_trap) {
 523                 kvm_info("GICv3 sysreg trapping enabled ([%s%s%s], reduced performance)\n",
 524                          group0_trap ? "G0" : "",
 525                          group1_trap ? "G1" : "",
 526                          common_trap ? "C"  : "");
 527                 static_branch_enable(&vgic_v3_cpuif_trap);
 528         }
 529
 530         kvm_vgic_global_state.vctrl_base = NULL;
 531         kvm_vgic_global_state.type = VGIC_V3;
 532         kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
 533
 534         return 0;
 535 }
 536
 537 void vgic_v3_load(struct kvm_vcpu *vcpu)
 538 {
 539         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 540
 541         /*
 542          * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen
 543          * is dependent on ICC_SRE_EL1.SRE, and we have to perform the
 544          * VMCR_EL2 save/restore in the world switch.
 545          */
 546         if (likely(cpu_if->vgic_sre))
 547                 kvm_call_hyp(__vgic_v3_write_vmcr, cpu_if->vgic_vmcr);
 548 }
 549
 550 void vgic_v3_put(struct kvm_vcpu *vcpu)
 551 {
 552         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 553
 554         if (likely(cpu_if->vgic_sre))
 555                 cpu_if->vgic_vmcr = kvm_call_hyp(__vgic_v3_read_vmcr);
 556 }