virt/kvm/arm/vgic/vgic-v2.c

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/irqchip/arm-gic.h>
  18 #include <linux/kvm.h>
  19 #include <linux/kvm_host.h>
  20 #include <kvm/arm_vgic.h>
  21 #include <asm/kvm_mmu.h>
  22
  23 #include "vgic.h"
  24
  25 static inline void vgic_v2_write_lr(int lr, u32 val)
  26 {
  27         void __iomem *base = kvm_vgic_global_state.vctrl_base;
  28
  29         writel_relaxed(val, base + GICH_LR0 + (lr * 4));
  30 }
  31
  32 void vgic_v2_init_lrs(void)
  33 {
  34         int i;
  35
  36         for (i = 0; i < kvm_vgic_global_state.nr_lr; i++)
  37                 vgic_v2_write_lr(i, 0);
  38 }
  39
  40 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
  41 {
  42         struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
  43
  44         cpuif->vgic_hcr |= GICH_HCR_UIE;
  45 }
  46
  47 static bool lr_signals_eoi_mi(u32 lr_val)
  48 {
  49         return !(lr_val & GICH_LR_STATE) && (lr_val & GICH_LR_EOI) &&
  50                !(lr_val & GICH_LR_HW);
  51 }
  52
  53 /*
  54  * transfer the content of the LRs back into the corresponding ap_list:
  55  * - active bit is transferred as is
  56  * - pending bit is
  57  *   - transferred as is in case of edge sensitive IRQs
  58  *   - set to the line-level (resample time) for level sensitive IRQs
  59  */
  60 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
  61 {
  62         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
  63         struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
  64         int lr;
  65         unsigned long flags;
  66
  67         cpuif->vgic_hcr &= ~GICH_HCR_UIE;
  68
  69         for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
  70                 u32 val = cpuif->vgic_lr[lr];
  71                 u32 intid = val & GICH_LR_VIRTUALID;
  72                 struct vgic_irq *irq;
  73
  74                 /* Notify fds when the guest EOI'ed a level-triggered SPI */
  75                 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
  76                         kvm_notify_acked_irq(vcpu->kvm, 0,
  77                                              intid - VGIC_NR_PRIVATE_IRQS);
  78
  79                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
  80
  81                 spin_lock_irqsave(&irq->irq_lock, flags);
  82
  83                 /* Always preserve the active bit */
  84                 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
  85
  86                 /* Edge is the only case where we preserve the pending bit */
  87                 if (irq->config == VGIC_CONFIG_EDGE &&
  88                     (val & GICH_LR_PENDING_BIT)) {
  89                         irq->pending_latch = true;
  90
  91                         if (vgic_irq_is_sgi(intid)) {
  92                                 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
  93
  94                                 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
  95                                 irq->source |= (1 << cpuid);
  96                         }
  97                 }
  98
  99                 /*
 100                  * Clear soft pending state when level irqs have been acked.
 101                  * Always regenerate the pending state.
 102                  */
 103                 if (irq->config == VGIC_CONFIG_LEVEL) {
 104                         if (!(val & GICH_LR_PENDING_BIT))
 105                                 irq->pending_latch = false;
 106                 }
 107
 108                 /*
 109                  * Level-triggered mapped IRQs are special because we only
 110                  * observe rising edges as input to the VGIC.
 111                  *
 112                  * If the guest never acked the interrupt we have to sample
 113                  * the physical line and set the line level, because the
 114                  * device state could have changed or we simply need to
 115                  * process the still pending interrupt later.
 116                  *
 117                  * If this causes us to lower the level, we have to also clear
 118                  * the physical active state, since we will otherwise never be
 119                  * told when the interrupt becomes asserted again.
 120                  */
 121                 if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT)) {
 122                         irq->line_level = vgic_get_phys_line_level(irq);
 123
 124                         if (!irq->line_level)
 125                                 vgic_irq_set_phys_active(irq, false);
 126                 }
 127
 128                 spin_unlock_irqrestore(&irq->irq_lock, flags);
 129                 vgic_put_irq(vcpu->kvm, irq);
 130         }
 131
 132         vgic_cpu->used_lrs = 0;
 133 }
 134
 135 /*
 136  * Populates the particular LR with the state of a given IRQ:
 137  * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
 138  * - for a level sensitive IRQ the pending state value is unchanged;
 139  *   it is dictated directly by the input level
 140  *
 141  * If @irq describes an SGI with multiple sources, we choose the
 142  * lowest-numbered source VCPU and clear that bit in the source bitmap.
 143  *
 144  * The irq_lock must be held by the caller.
 145  */
 146 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
 147 {
 148         u32 val = irq->intid;
 149
 150         if (irq_is_pending(irq)) {
 151                 val |= GICH_LR_PENDING_BIT;
 152
 153                 if (irq->config == VGIC_CONFIG_EDGE)
 154                         irq->pending_latch = false;
 155
 156                 if (vgic_irq_is_sgi(irq->intid)) {
 157                         u32 src = ffs(irq->source);
 158
 159                         BUG_ON(!src);
 160                         val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 161                         irq->source &= ~(1 << (src - 1));
 162                         if (irq->source)
 163                                 irq->pending_latch = true;
 164                 }
 165         }
 166
 167         if (irq->active)
 168                 val |= GICH_LR_ACTIVE_BIT;
 169
 170         if (irq->hw) {
 171                 val |= GICH_LR_HW;
 172                 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
 173                 /*
 174                  * Never set pending+active on a HW interrupt, as the
 175                  * pending state is kept at the physical distributor
 176                  * level.
 177                  */
 178                 if (irq->active && irq_is_pending(irq))
 179                         val &= ~GICH_LR_PENDING_BIT;
 180         } else {
 181                 if (irq->config == VGIC_CONFIG_LEVEL)
 182                         val |= GICH_LR_EOI;
 183         }
 184
 185         /*
 186          * Level-triggered mapped IRQs are special because we only observe
 187          * rising edges as input to the VGIC.  We therefore lower the line
 188          * level here, so that we can take new virtual IRQs.  See
 189          * vgic_v2_fold_lr_state for more info.
 190          */
 191         if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT))
 192                 irq->line_level = false;
 193
 194         /* The GICv2 LR only holds five bits of priority. */
 195         val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
 196
 197         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
 198 }
 199
 200 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
 201 {
 202         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
 203 }
 204
 205 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 206 {
 207         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 208         u32 vmcr;
 209
 210         vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) &
 211                 GICH_VMCR_ENABLE_GRP0_MASK;
 212         vmcr |= (vmcrp->grpen1 << GICH_VMCR_ENABLE_GRP1_SHIFT) &
 213                 GICH_VMCR_ENABLE_GRP1_MASK;
 214         vmcr |= (vmcrp->ackctl << GICH_VMCR_ACK_CTL_SHIFT) &
 215                 GICH_VMCR_ACK_CTL_MASK;
 216         vmcr |= (vmcrp->fiqen << GICH_VMCR_FIQ_EN_SHIFT) &
 217                 GICH_VMCR_FIQ_EN_MASK;
 218         vmcr |= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) &
 219                 GICH_VMCR_CBPR_MASK;
 220         vmcr |= (vmcrp->eoim << GICH_VMCR_EOI_MODE_SHIFT) &
 221                 GICH_VMCR_EOI_MODE_MASK;
 222         vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
 223                 GICH_VMCR_ALIAS_BINPOINT_MASK;
 224         vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
 225                 GICH_VMCR_BINPOINT_MASK;
 226         vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) <<
 227                  GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
 228
 229         cpu_if->vgic_vmcr = vmcr;
 230 }
 231
 232 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 233 {
 234         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 235         u32 vmcr;
 236
 237         vmcr = cpu_if->vgic_vmcr;
 238
 239         vmcrp->grpen0 = (vmcr & GICH_VMCR_ENABLE_GRP0_MASK) >>
 240                 GICH_VMCR_ENABLE_GRP0_SHIFT;
 241         vmcrp->grpen1 = (vmcr & GICH_VMCR_ENABLE_GRP1_MASK) >>
 242                 GICH_VMCR_ENABLE_GRP1_SHIFT;
 243         vmcrp->ackctl = (vmcr & GICH_VMCR_ACK_CTL_MASK) >>
 244                 GICH_VMCR_ACK_CTL_SHIFT;
 245         vmcrp->fiqen = (vmcr & GICH_VMCR_FIQ_EN_MASK) >>
 246                 GICH_VMCR_FIQ_EN_SHIFT;
 247         vmcrp->cbpr = (vmcr & GICH_VMCR_CBPR_MASK) >>
 248                 GICH_VMCR_CBPR_SHIFT;
 249         vmcrp->eoim = (vmcr & GICH_VMCR_EOI_MODE_MASK) >>
 250                 GICH_VMCR_EOI_MODE_SHIFT;
 251
 252         vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
 253                         GICH_VMCR_ALIAS_BINPOINT_SHIFT;
 254         vmcrp->bpr  = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
 255                         GICH_VMCR_BINPOINT_SHIFT;
 256         vmcrp->pmr  = ((vmcr & GICH_VMCR_PRIMASK_MASK) >>
 257                         GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT;
 258 }
 259
 260 void vgic_v2_enable(struct kvm_vcpu *vcpu)
 261 {
 262         /*
 263          * By forcing VMCR to zero, the GIC will restore the binary
 264          * points to their reset values. Anything else resets to zero
 265          * anyway.
 266          */
 267         vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
 268         vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;
 269
 270         /* Get the show on the road... */
 271         vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
 272 }
 273
 274 /* check for overlapping regions and for regions crossing the end of memory */
 275 static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
 276 {
 277         if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
 278                 return false;
 279         if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
 280                 return false;
 281
 282         if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
 283                 return true;
 284         if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
 285                 return true;
 286
 287         return false;
 288 }
 289
 290 int vgic_v2_map_resources(struct kvm *kvm)
 291 {
 292         struct vgic_dist *dist = &kvm->arch.vgic;
 293         int ret = 0;
 294
 295         if (vgic_ready(kvm))
 296                 goto out;
 297
 298         if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
 299             IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
 300                 kvm_err("Need to set vgic cpu and dist addresses first\n");
 301                 ret = -ENXIO;
 302                 goto out;
 303         }
 304
 305         if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
 306                 kvm_err("VGIC CPU and dist frames overlap\n");
 307                 ret = -EINVAL;
 308                 goto out;
 309         }
 310
 311         /*
 312          * Initialize the vgic if this hasn't already been done on demand by
 313          * accessing the vgic state from userspace.
 314          */
 315         ret = vgic_init(kvm);
 316         if (ret) {
 317                 kvm_err("Unable to initialize VGIC dynamic data structures\n");
 318                 goto out;
 319         }
 320
 321         ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
 322         if (ret) {
 323                 kvm_err("Unable to register VGIC MMIO regions\n");
 324                 goto out;
 325         }
 326
 327         if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
 328                 ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
 329                                             kvm_vgic_global_state.vcpu_base,
 330                                             KVM_VGIC_V2_CPU_SIZE, true);
 331                 if (ret) {
 332                         kvm_err("Unable to remap VGIC CPU to VCPU\n");
 333                         goto out;
 334                 }
 335         }
 336
 337         dist->ready = true;
 338
 339 out:
 340         return ret;
 341 }
 342
 343 DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);
 344
 345 /**
 346  * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
 347  * @node:       pointer to the DT node
 348  *
 349  * Returns 0 if a GICv2 has been found, returns an error code otherwise
 350  */
 351 int vgic_v2_probe(const struct gic_kvm_info *info)
 352 {
 353         int ret;
 354         u32 vtr;
 355
 356         if (!info->vctrl.start) {
 357                 kvm_err("GICH not present in the firmware table\n");
 358                 return -ENXIO;
 359         }
 360
 361         if (!PAGE_ALIGNED(info->vcpu.start) ||
 362             !PAGE_ALIGNED(resource_size(&info->vcpu))) {
 363                 kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");
 364                 kvm_vgic_global_state.vcpu_base_va = ioremap(info->vcpu.start,
 365                                                              resource_size(&info->vcpu));
 366                 if (!kvm_vgic_global_state.vcpu_base_va) {
 367                         kvm_err("Cannot ioremap GICV\n");
 368                         return -ENOMEM;
 369                 }
 370
 371                 ret = create_hyp_io_mappings(kvm_vgic_global_state.vcpu_base_va,
 372                                              kvm_vgic_global_state.vcpu_base_va + resource_size(&info->vcpu),
 373                                              info->vcpu.start);
 374                 if (ret) {
 375                         kvm_err("Cannot map GICV into hyp\n");
 376                         goto out;
 377                 }
 378
 379                 static_branch_enable(&vgic_v2_cpuif_trap);
 380         }
 381
 382         kvm_vgic_global_state.vctrl_base = ioremap(info->vctrl.start,
 383                                                    resource_size(&info->vctrl));
 384         if (!kvm_vgic_global_state.vctrl_base) {
 385                 kvm_err("Cannot ioremap GICH\n");
 386                 ret = -ENOMEM;
 387                 goto out;
 388         }
 389
 390         vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
 391         kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
 392
 393         ret = create_hyp_io_mappings(kvm_vgic_global_state.vctrl_base,
 394                                      kvm_vgic_global_state.vctrl_base +
 395                                          resource_size(&info->vctrl),
 396                                      info->vctrl.start);
 397         if (ret) {
 398                 kvm_err("Cannot map VCTRL into hyp\n");
 399                 goto out;
 400         }
 401
 402         ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
 403         if (ret) {
 404                 kvm_err("Cannot register GICv2 KVM device\n");
 405                 goto out;
 406         }
 407
 408         kvm_vgic_global_state.can_emulate_gicv2 = true;
 409         kvm_vgic_global_state.vcpu_base = info->vcpu.start;
 410         kvm_vgic_global_state.type = VGIC_V2;
 411         kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
 412
 413         kvm_info("vgic-v2@%llx\n", info->vctrl.start);
 414
 415         return 0;
 416 out:
 417         if (kvm_vgic_global_state.vctrl_base)
 418                 iounmap(kvm_vgic_global_state.vctrl_base);
 419         if (kvm_vgic_global_state.vcpu_base_va)
 420                 iounmap(kvm_vgic_global_state.vcpu_base_va);
 421
 422         return ret;
 423 }
 424
 425 void vgic_v2_load(struct kvm_vcpu *vcpu)
 426 {
 427         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 428         struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
 429
 430         writel_relaxed(cpu_if->vgic_vmcr, vgic->vctrl_base + GICH_VMCR);
 431 }
 432
 433 void vgic_v2_put(struct kvm_vcpu *vcpu)
 434 {
 435         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 436         struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
 437
 438         cpu_if->vgic_vmcr = readl_relaxed(vgic->vctrl_base + GICH_VMCR);
 439 }