4 * Copyright (C) 2015,2016 ARM Ltd.
5 * Author: Andre Przywara <andre.przywara@arm.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/cpu.h>
21 #include <linux/kvm.h>
22 #include <linux/kvm_host.h>
23 #include <linux/interrupt.h>
24 #include <linux/list.h>
25 #include <linux/uaccess.h>
26 #include <linux/list_sort.h>
28 #include <linux/irqchip/arm-gic-v3.h>
30 #include <asm/kvm_emulate.h>
31 #include <asm/kvm_arm.h>
32 #include <asm/kvm_mmu.h>
35 #include "vgic-mmio.h"
37 static int vgic_its_save_tables_v0(struct vgic_its *its);
38 static int vgic_its_restore_tables_v0(struct vgic_its *its);
39 static int vgic_its_commit_v0(struct vgic_its *its);
40 static int update_lpi_config(struct kvm *kvm, struct vgic_irq *irq,
41 struct kvm_vcpu *filter_vcpu, bool needs_inv);
44 * Creates a new (reference to a) struct vgic_irq for a given LPI.
45 * If this LPI is already mapped on another ITS, we increase its refcount
46 * and return a pointer to the existing structure.
47 * If this is a "new" LPI, we allocate and initialize a new struct vgic_irq.
48 * This function returns a pointer to the _unlocked_ structure.
50 static struct vgic_irq *vgic_add_lpi(struct kvm *kvm, u32 intid,
51 struct kvm_vcpu *vcpu)
53 struct vgic_dist *dist = &kvm->arch.vgic;
54 struct vgic_irq *irq = vgic_get_irq(kvm, NULL, intid), *oldirq;
58 /* In this case there is no put, since we keep the reference. */
62 irq = kzalloc(sizeof(struct vgic_irq), GFP_KERNEL);
64 return ERR_PTR(-ENOMEM);
66 INIT_LIST_HEAD(&irq->lpi_list);
67 INIT_LIST_HEAD(&irq->ap_list);
68 spin_lock_init(&irq->irq_lock);
70 irq->config = VGIC_CONFIG_EDGE;
71 kref_init(&irq->refcount);
73 irq->target_vcpu = vcpu;
76 raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
79 * There could be a race with another vgic_add_lpi(), so we need to
80 * check that we don't add a second list entry with the same LPI.
82 list_for_each_entry(oldirq, &dist->lpi_list_head, lpi_list) {
83 if (oldirq->intid != intid)
86 /* Someone was faster with adding this LPI, lets use that. */
91 * This increases the refcount, the caller is expected to
92 * call vgic_put_irq() on the returned pointer once it's
93 * finished with the IRQ.
95 vgic_get_irq_kref(irq);
100 list_add_tail(&irq->lpi_list, &dist->lpi_list_head);
101 dist->lpi_list_count++;
104 raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
107 * We "cache" the configuration table entries in our struct vgic_irq's.
108 * However we only have those structs for mapped IRQs, so we read in
109 * the respective config data from memory here upon mapping the LPI.
111 ret = update_lpi_config(kvm, irq, NULL, false);
115 ret = vgic_v3_lpi_sync_pending_status(kvm, irq);
123 struct list_head dev_list;
125 /* the head for the list of ITTEs */
126 struct list_head itt_head;
127 u32 num_eventid_bits;
132 #define COLLECTION_NOT_MAPPED ((u32)~0)
134 struct its_collection {
135 struct list_head coll_list;
141 #define its_is_collection_mapped(coll) ((coll) && \
142 ((coll)->target_addr != COLLECTION_NOT_MAPPED))
145 struct list_head ite_list;
147 struct vgic_irq *irq;
148 struct its_collection *collection;
153 * struct vgic_its_abi - ITS abi ops and settings
154 * @cte_esz: collection table entry size
155 * @dte_esz: device table entry size
156 * @ite_esz: interrupt translation table entry size
157 * @save tables: save the ITS tables into guest RAM
158 * @restore_tables: restore the ITS internal structs from tables
159 * stored in guest RAM
160 * @commit: initialize the registers which expose the ABI settings,
161 * especially the entry sizes
163 struct vgic_its_abi {
167 int (*save_tables)(struct vgic_its *its);
168 int (*restore_tables)(struct vgic_its *its);
169 int (*commit)(struct vgic_its *its);
173 #define ESZ_MAX ABI_0_ESZ
175 static const struct vgic_its_abi its_table_abi_versions[] = {
177 .cte_esz = ABI_0_ESZ,
178 .dte_esz = ABI_0_ESZ,
179 .ite_esz = ABI_0_ESZ,
180 .save_tables = vgic_its_save_tables_v0,
181 .restore_tables = vgic_its_restore_tables_v0,
182 .commit = vgic_its_commit_v0,
186 #define NR_ITS_ABIS ARRAY_SIZE(its_table_abi_versions)
188 inline const struct vgic_its_abi *vgic_its_get_abi(struct vgic_its *its)
190 return &its_table_abi_versions[its->abi_rev];
193 static int vgic_its_set_abi(struct vgic_its *its, u32 rev)
195 const struct vgic_its_abi *abi;
198 abi = vgic_its_get_abi(its);
199 return abi->commit(its);
203 * Find and returns a device in the device table for an ITS.
204 * Must be called with the its_lock mutex held.
206 static struct its_device *find_its_device(struct vgic_its *its, u32 device_id)
208 struct its_device *device;
210 list_for_each_entry(device, &its->device_list, dev_list)
211 if (device_id == device->device_id)
218 * Find and returns an interrupt translation table entry (ITTE) for a given
219 * Device ID/Event ID pair on an ITS.
220 * Must be called with the its_lock mutex held.
222 static struct its_ite *find_ite(struct vgic_its *its, u32 device_id,
225 struct its_device *device;
228 device = find_its_device(its, device_id);
232 list_for_each_entry(ite, &device->itt_head, ite_list)
233 if (ite->event_id == event_id)
239 /* To be used as an iterator this macro misses the enclosing parentheses */
240 #define for_each_lpi_its(dev, ite, its) \
241 list_for_each_entry(dev, &(its)->device_list, dev_list) \
242 list_for_each_entry(ite, &(dev)->itt_head, ite_list)
245 * We only implement 48 bits of PA at the moment, although the ITS
246 * supports more. Let's be restrictive here.
248 #define BASER_ADDRESS(x) ((x) & GENMASK_ULL(47, 16))
249 #define CBASER_ADDRESS(x) ((x) & GENMASK_ULL(47, 12))
251 #define GIC_LPI_OFFSET 8192
253 #define VITS_TYPER_IDBITS 16
254 #define VITS_TYPER_DEVBITS 16
255 #define VITS_DTE_MAX_DEVID_OFFSET (BIT(14) - 1)
256 #define VITS_ITE_MAX_EVENTID_OFFSET (BIT(16) - 1)
259 * Finds and returns a collection in the ITS collection table.
260 * Must be called with the its_lock mutex held.
262 static struct its_collection *find_collection(struct vgic_its *its, int coll_id)
264 struct its_collection *collection;
266 list_for_each_entry(collection, &its->collection_list, coll_list) {
267 if (coll_id == collection->collection_id)
274 #define LPI_PROP_ENABLE_BIT(p) ((p) & LPI_PROP_ENABLED)
275 #define LPI_PROP_PRIORITY(p) ((p) & 0xfc)
278 * Reads the configuration data for a given LPI from guest memory and
279 * updates the fields in struct vgic_irq.
280 * If filter_vcpu is not NULL, applies only if the IRQ is targeting this
281 * VCPU. Unconditionally applies if filter_vcpu is NULL.
283 static int update_lpi_config(struct kvm *kvm, struct vgic_irq *irq,
284 struct kvm_vcpu *filter_vcpu, bool needs_inv)
286 u64 propbase = GICR_PROPBASER_ADDRESS(kvm->arch.vgic.propbaser);
291 ret = kvm_read_guest_lock(kvm, propbase + irq->intid - GIC_LPI_OFFSET,
297 spin_lock_irqsave(&irq->irq_lock, flags);
299 if (!filter_vcpu || filter_vcpu == irq->target_vcpu) {
300 irq->priority = LPI_PROP_PRIORITY(prop);
301 irq->enabled = LPI_PROP_ENABLE_BIT(prop);
304 vgic_queue_irq_unlock(kvm, irq, flags);
309 spin_unlock_irqrestore(&irq->irq_lock, flags);
312 return its_prop_update_vlpi(irq->host_irq, prop, needs_inv);
318 * Create a snapshot of the current LPIs targeting @vcpu, so that we can
319 * enumerate those LPIs without holding any lock.
320 * Returns their number and puts the kmalloc'ed array into intid_ptr.
322 int vgic_copy_lpi_list(struct kvm *kvm, struct kvm_vcpu *vcpu, u32 **intid_ptr)
324 struct vgic_dist *dist = &kvm->arch.vgic;
325 struct vgic_irq *irq;
328 int irq_count, i = 0;
331 * There is an obvious race between allocating the array and LPIs
332 * being mapped/unmapped. If we ended up here as a result of a
333 * command, we're safe (locks are held, preventing another
334 * command). If coming from another path (such as enabling LPIs),
335 * we must be careful not to overrun the array.
337 irq_count = READ_ONCE(dist->lpi_list_count);
338 intids = kmalloc_array(irq_count, sizeof(intids[0]), GFP_KERNEL);
342 raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
343 list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
346 /* We don't need to "get" the IRQ, as we hold the list lock. */
347 if (vcpu && irq->target_vcpu != vcpu)
349 intids[i++] = irq->intid;
351 raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
357 static int update_affinity(struct vgic_irq *irq, struct kvm_vcpu *vcpu)
362 spin_lock_irqsave(&irq->irq_lock, flags);
363 irq->target_vcpu = vcpu;
364 spin_unlock_irqrestore(&irq->irq_lock, flags);
367 struct its_vlpi_map map;
369 ret = its_get_vlpi(irq->host_irq, &map);
373 map.vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe;
375 ret = its_map_vlpi(irq->host_irq, &map);
382 * Promotes the ITS view of affinity of an ITTE (which redistributor this LPI
383 * is targeting) to the VGIC's view, which deals with target VCPUs.
384 * Needs to be called whenever either the collection for a LPIs has
385 * changed or the collection itself got retargeted.
387 static void update_affinity_ite(struct kvm *kvm, struct its_ite *ite)
389 struct kvm_vcpu *vcpu;
391 if (!its_is_collection_mapped(ite->collection))
394 vcpu = kvm_get_vcpu(kvm, ite->collection->target_addr);
395 update_affinity(ite->irq, vcpu);
399 * Updates the target VCPU for every LPI targeting this collection.
400 * Must be called with the its_lock mutex held.
402 static void update_affinity_collection(struct kvm *kvm, struct vgic_its *its,
403 struct its_collection *coll)
405 struct its_device *device;
408 for_each_lpi_its(device, ite, its) {
409 if (!ite->collection || coll != ite->collection)
412 update_affinity_ite(kvm, ite);
416 static u32 max_lpis_propbaser(u64 propbaser)
418 int nr_idbits = (propbaser & 0x1f) + 1;
420 return 1U << min(nr_idbits, INTERRUPT_ID_BITS_ITS);
424 * Sync the pending table pending bit of LPIs targeting @vcpu
425 * with our own data structures. This relies on the LPI being
428 static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu)
430 gpa_t pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
431 struct vgic_irq *irq;
432 int last_byte_offset = -1;
439 nr_irqs = vgic_copy_lpi_list(vcpu->kvm, vcpu, &intids);
443 for (i = 0; i < nr_irqs; i++) {
444 int byte_offset, bit_nr;
446 byte_offset = intids[i] / BITS_PER_BYTE;
447 bit_nr = intids[i] % BITS_PER_BYTE;
450 * For contiguously allocated LPIs chances are we just read
451 * this very same byte in the last iteration. Reuse that.
453 if (byte_offset != last_byte_offset) {
454 ret = kvm_read_guest_lock(vcpu->kvm,
455 pendbase + byte_offset,
461 last_byte_offset = byte_offset;
464 irq = vgic_get_irq(vcpu->kvm, NULL, intids[i]);
465 spin_lock_irqsave(&irq->irq_lock, flags);
466 irq->pending_latch = pendmask & (1U << bit_nr);
467 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
468 vgic_put_irq(vcpu->kvm, irq);
476 static unsigned long vgic_mmio_read_its_typer(struct kvm *kvm,
477 struct vgic_its *its,
478 gpa_t addr, unsigned int len)
480 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
481 u64 reg = GITS_TYPER_PLPIS;
484 * We use linear CPU numbers for redistributor addressing,
485 * so GITS_TYPER.PTA is 0.
486 * Also we force all PROPBASER registers to be the same, so
487 * CommonLPIAff is 0 as well.
488 * To avoid memory waste in the guest, we keep the number of IDBits and
489 * DevBits low - as least for the time being.
491 reg |= GIC_ENCODE_SZ(VITS_TYPER_DEVBITS, 5) << GITS_TYPER_DEVBITS_SHIFT;
492 reg |= GIC_ENCODE_SZ(VITS_TYPER_IDBITS, 5) << GITS_TYPER_IDBITS_SHIFT;
493 reg |= GIC_ENCODE_SZ(abi->ite_esz, 4) << GITS_TYPER_ITT_ENTRY_SIZE_SHIFT;
495 return extract_bytes(reg, addr & 7, len);
498 static unsigned long vgic_mmio_read_its_iidr(struct kvm *kvm,
499 struct vgic_its *its,
500 gpa_t addr, unsigned int len)
504 val = (its->abi_rev << GITS_IIDR_REV_SHIFT) & GITS_IIDR_REV_MASK;
505 val |= (PRODUCT_ID_KVM << GITS_IIDR_PRODUCTID_SHIFT) | IMPLEMENTER_ARM;
509 static int vgic_mmio_uaccess_write_its_iidr(struct kvm *kvm,
510 struct vgic_its *its,
511 gpa_t addr, unsigned int len,
514 u32 rev = GITS_IIDR_REV(val);
516 if (rev >= NR_ITS_ABIS)
518 return vgic_its_set_abi(its, rev);
521 static unsigned long vgic_mmio_read_its_idregs(struct kvm *kvm,
522 struct vgic_its *its,
523 gpa_t addr, unsigned int len)
525 switch (addr & 0xffff) {
527 return 0x92; /* part number, bits[7:0] */
529 return 0xb4; /* part number, bits[11:8] */
531 return GIC_PIDR2_ARCH_GICv3 | 0x0b;
533 return 0x40; /* This is a 64K software visible page */
534 /* The following are the ID registers for (any) GIC. */
548 int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its,
549 u32 devid, u32 eventid, struct vgic_irq **irq)
551 struct kvm_vcpu *vcpu;
557 ite = find_ite(its, devid, eventid);
558 if (!ite || !its_is_collection_mapped(ite->collection))
559 return E_ITS_INT_UNMAPPED_INTERRUPT;
561 vcpu = kvm_get_vcpu(kvm, ite->collection->target_addr);
563 return E_ITS_INT_UNMAPPED_INTERRUPT;
565 if (!vcpu->arch.vgic_cpu.lpis_enabled)
572 struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi)
575 struct kvm_io_device *kvm_io_dev;
576 struct vgic_io_device *iodev;
578 if (!vgic_has_its(kvm))
579 return ERR_PTR(-ENODEV);
581 if (!(msi->flags & KVM_MSI_VALID_DEVID))
582 return ERR_PTR(-EINVAL);
584 address = (u64)msi->address_hi << 32 | msi->address_lo;
586 kvm_io_dev = kvm_io_bus_get_dev(kvm, KVM_MMIO_BUS, address);
588 return ERR_PTR(-EINVAL);
590 if (kvm_io_dev->ops != &kvm_io_gic_ops)
591 return ERR_PTR(-EINVAL);
593 iodev = container_of(kvm_io_dev, struct vgic_io_device, dev);
594 if (iodev->iodev_type != IODEV_ITS)
595 return ERR_PTR(-EINVAL);
601 * Find the target VCPU and the LPI number for a given devid/eventid pair
602 * and make this IRQ pending, possibly injecting it.
603 * Must be called with the its_lock mutex held.
604 * Returns 0 on success, a positive error value for any ITS mapping
605 * related errors and negative error values for generic errors.
607 static int vgic_its_trigger_msi(struct kvm *kvm, struct vgic_its *its,
608 u32 devid, u32 eventid)
610 struct vgic_irq *irq = NULL;
614 err = vgic_its_resolve_lpi(kvm, its, devid, eventid, &irq);
619 return irq_set_irqchip_state(irq->host_irq,
620 IRQCHIP_STATE_PENDING, true);
622 spin_lock_irqsave(&irq->irq_lock, flags);
623 irq->pending_latch = true;
624 vgic_queue_irq_unlock(kvm, irq, flags);
630 * Queries the KVM IO bus framework to get the ITS pointer from the given
632 * We then call vgic_its_trigger_msi() with the decoded data.
633 * According to the KVM_SIGNAL_MSI API description returns 1 on success.
635 int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi)
637 struct vgic_its *its;
640 its = vgic_msi_to_its(kvm, msi);
644 mutex_lock(&its->its_lock);
645 ret = vgic_its_trigger_msi(kvm, its, msi->devid, msi->data);
646 mutex_unlock(&its->its_lock);
652 * KVM_SIGNAL_MSI demands a return value > 0 for success and 0
653 * if the guest has blocked the MSI. So we map any LPI mapping
654 * related error to that.
662 /* Requires the its_lock to be held. */
663 static void its_free_ite(struct kvm *kvm, struct its_ite *ite)
665 list_del(&ite->ite_list);
667 /* This put matches the get in vgic_add_lpi. */
670 WARN_ON(its_unmap_vlpi(ite->irq->host_irq));
672 vgic_put_irq(kvm, ite->irq);
678 static u64 its_cmd_mask_field(u64 *its_cmd, int word, int shift, int size)
680 return (le64_to_cpu(its_cmd[word]) >> shift) & (BIT_ULL(size) - 1);
683 #define its_cmd_get_command(cmd) its_cmd_mask_field(cmd, 0, 0, 8)
684 #define its_cmd_get_deviceid(cmd) its_cmd_mask_field(cmd, 0, 32, 32)
685 #define its_cmd_get_size(cmd) (its_cmd_mask_field(cmd, 1, 0, 5) + 1)
686 #define its_cmd_get_id(cmd) its_cmd_mask_field(cmd, 1, 0, 32)
687 #define its_cmd_get_physical_id(cmd) its_cmd_mask_field(cmd, 1, 32, 32)
688 #define its_cmd_get_collection(cmd) its_cmd_mask_field(cmd, 2, 0, 16)
689 #define its_cmd_get_ittaddr(cmd) (its_cmd_mask_field(cmd, 2, 8, 44) << 8)
690 #define its_cmd_get_target_addr(cmd) its_cmd_mask_field(cmd, 2, 16, 32)
691 #define its_cmd_get_validbit(cmd) its_cmd_mask_field(cmd, 2, 63, 1)
694 * The DISCARD command frees an Interrupt Translation Table Entry (ITTE).
695 * Must be called with the its_lock mutex held.
697 static int vgic_its_cmd_handle_discard(struct kvm *kvm, struct vgic_its *its,
700 u32 device_id = its_cmd_get_deviceid(its_cmd);
701 u32 event_id = its_cmd_get_id(its_cmd);
705 ite = find_ite(its, device_id, event_id);
706 if (ite && ite->collection) {
708 * Though the spec talks about removing the pending state, we
709 * don't bother here since we clear the ITTE anyway and the
710 * pending state is a property of the ITTE struct.
712 its_free_ite(kvm, ite);
716 return E_ITS_DISCARD_UNMAPPED_INTERRUPT;
720 * The MOVI command moves an ITTE to a different collection.
721 * Must be called with the its_lock mutex held.
723 static int vgic_its_cmd_handle_movi(struct kvm *kvm, struct vgic_its *its,
726 u32 device_id = its_cmd_get_deviceid(its_cmd);
727 u32 event_id = its_cmd_get_id(its_cmd);
728 u32 coll_id = its_cmd_get_collection(its_cmd);
729 struct kvm_vcpu *vcpu;
731 struct its_collection *collection;
733 ite = find_ite(its, device_id, event_id);
735 return E_ITS_MOVI_UNMAPPED_INTERRUPT;
737 if (!its_is_collection_mapped(ite->collection))
738 return E_ITS_MOVI_UNMAPPED_COLLECTION;
740 collection = find_collection(its, coll_id);
741 if (!its_is_collection_mapped(collection))
742 return E_ITS_MOVI_UNMAPPED_COLLECTION;
744 ite->collection = collection;
745 vcpu = kvm_get_vcpu(kvm, collection->target_addr);
747 return update_affinity(ite->irq, vcpu);
751 * Check whether an ID can be stored into the corresponding guest table.
752 * For a direct table this is pretty easy, but gets a bit nasty for
753 * indirect tables. We check whether the resulting guest physical address
754 * is actually valid (covered by a memslot and guest accessible).
755 * For this we have to read the respective first level entry.
757 static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id,
760 int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
761 u64 indirect_ptr, type = GITS_BASER_TYPE(baser);
762 int esz = GITS_BASER_ENTRY_SIZE(baser);
768 case GITS_BASER_TYPE_DEVICE:
769 if (id >= BIT_ULL(VITS_TYPER_DEVBITS))
772 case GITS_BASER_TYPE_COLLECTION:
773 /* as GITS_TYPER.CIL == 0, ITS supports 16-bit collection ID */
774 if (id >= BIT_ULL(16))
781 if (!(baser & GITS_BASER_INDIRECT)) {
784 if (id >= (l1_tbl_size / esz))
787 addr = BASER_ADDRESS(baser) + id * esz;
788 gfn = addr >> PAGE_SHIFT;
796 /* calculate and check the index into the 1st level */
797 index = id / (SZ_64K / esz);
798 if (index >= (l1_tbl_size / sizeof(u64)))
801 /* Each 1st level entry is represented by a 64-bit value. */
802 if (kvm_read_guest_lock(its->dev->kvm,
803 BASER_ADDRESS(baser) + index * sizeof(indirect_ptr),
804 &indirect_ptr, sizeof(indirect_ptr)))
807 indirect_ptr = le64_to_cpu(indirect_ptr);
809 /* check the valid bit of the first level entry */
810 if (!(indirect_ptr & BIT_ULL(63)))
814 * Mask the guest physical address and calculate the frame number.
815 * Any address beyond our supported 48 bits of PA will be caught
816 * by the actual check in the final step.
818 indirect_ptr &= GENMASK_ULL(51, 16);
820 /* Find the address of the actual entry */
821 index = id % (SZ_64K / esz);
822 indirect_ptr += index * esz;
823 gfn = indirect_ptr >> PAGE_SHIFT;
826 *eaddr = indirect_ptr;
829 idx = srcu_read_lock(&its->dev->kvm->srcu);
830 ret = kvm_is_visible_gfn(its->dev->kvm, gfn);
831 srcu_read_unlock(&its->dev->kvm->srcu, idx);
835 static int vgic_its_alloc_collection(struct vgic_its *its,
836 struct its_collection **colp,
839 struct its_collection *collection;
841 if (!vgic_its_check_id(its, its->baser_coll_table, coll_id, NULL))
842 return E_ITS_MAPC_COLLECTION_OOR;
844 collection = kzalloc(sizeof(*collection), GFP_KERNEL);
848 collection->collection_id = coll_id;
849 collection->target_addr = COLLECTION_NOT_MAPPED;
851 list_add_tail(&collection->coll_list, &its->collection_list);
857 static void vgic_its_free_collection(struct vgic_its *its, u32 coll_id)
859 struct its_collection *collection;
860 struct its_device *device;
864 * Clearing the mapping for that collection ID removes the
865 * entry from the list. If there wasn't any before, we can
868 collection = find_collection(its, coll_id);
872 for_each_lpi_its(device, ite, its)
873 if (ite->collection &&
874 ite->collection->collection_id == coll_id)
875 ite->collection = NULL;
877 list_del(&collection->coll_list);
881 /* Must be called with its_lock mutex held */
882 static struct its_ite *vgic_its_alloc_ite(struct its_device *device,
883 struct its_collection *collection,
888 ite = kzalloc(sizeof(*ite), GFP_KERNEL);
890 return ERR_PTR(-ENOMEM);
892 ite->event_id = event_id;
893 ite->collection = collection;
895 list_add_tail(&ite->ite_list, &device->itt_head);
900 * The MAPTI and MAPI commands map LPIs to ITTEs.
901 * Must be called with its_lock mutex held.
903 static int vgic_its_cmd_handle_mapi(struct kvm *kvm, struct vgic_its *its,
906 u32 device_id = its_cmd_get_deviceid(its_cmd);
907 u32 event_id = its_cmd_get_id(its_cmd);
908 u32 coll_id = its_cmd_get_collection(its_cmd);
910 struct kvm_vcpu *vcpu = NULL;
911 struct its_device *device;
912 struct its_collection *collection, *new_coll = NULL;
913 struct vgic_irq *irq;
916 device = find_its_device(its, device_id);
918 return E_ITS_MAPTI_UNMAPPED_DEVICE;
920 if (event_id >= BIT_ULL(device->num_eventid_bits))
921 return E_ITS_MAPTI_ID_OOR;
923 if (its_cmd_get_command(its_cmd) == GITS_CMD_MAPTI)
924 lpi_nr = its_cmd_get_physical_id(its_cmd);
927 if (lpi_nr < GIC_LPI_OFFSET ||
928 lpi_nr >= max_lpis_propbaser(kvm->arch.vgic.propbaser))
929 return E_ITS_MAPTI_PHYSICALID_OOR;
931 /* If there is an existing mapping, behavior is UNPREDICTABLE. */
932 if (find_ite(its, device_id, event_id))
935 collection = find_collection(its, coll_id);
937 int ret = vgic_its_alloc_collection(its, &collection, coll_id);
940 new_coll = collection;
943 ite = vgic_its_alloc_ite(device, collection, event_id);
946 vgic_its_free_collection(its, coll_id);
950 if (its_is_collection_mapped(collection))
951 vcpu = kvm_get_vcpu(kvm, collection->target_addr);
953 irq = vgic_add_lpi(kvm, lpi_nr, vcpu);
956 vgic_its_free_collection(its, coll_id);
957 its_free_ite(kvm, ite);
965 /* Requires the its_lock to be held. */
966 static void vgic_its_free_device(struct kvm *kvm, struct its_device *device)
968 struct its_ite *ite, *temp;
971 * The spec says that unmapping a device with still valid
972 * ITTEs associated is UNPREDICTABLE. We remove all ITTEs,
973 * since we cannot leave the memory unreferenced.
975 list_for_each_entry_safe(ite, temp, &device->itt_head, ite_list)
976 its_free_ite(kvm, ite);
978 list_del(&device->dev_list);
982 /* its lock must be held */
983 static void vgic_its_free_device_list(struct kvm *kvm, struct vgic_its *its)
985 struct its_device *cur, *temp;
987 list_for_each_entry_safe(cur, temp, &its->device_list, dev_list)
988 vgic_its_free_device(kvm, cur);
991 /* its lock must be held */
992 static void vgic_its_free_collection_list(struct kvm *kvm, struct vgic_its *its)
994 struct its_collection *cur, *temp;
996 list_for_each_entry_safe(cur, temp, &its->collection_list, coll_list)
997 vgic_its_free_collection(its, cur->collection_id);
1000 /* Must be called with its_lock mutex held */
1001 static struct its_device *vgic_its_alloc_device(struct vgic_its *its,
1002 u32 device_id, gpa_t itt_addr,
1003 u8 num_eventid_bits)
1005 struct its_device *device;
1007 device = kzalloc(sizeof(*device), GFP_KERNEL);
1009 return ERR_PTR(-ENOMEM);
1011 device->device_id = device_id;
1012 device->itt_addr = itt_addr;
1013 device->num_eventid_bits = num_eventid_bits;
1014 INIT_LIST_HEAD(&device->itt_head);
1016 list_add_tail(&device->dev_list, &its->device_list);
1021 * MAPD maps or unmaps a device ID to Interrupt Translation Tables (ITTs).
1022 * Must be called with the its_lock mutex held.
1024 static int vgic_its_cmd_handle_mapd(struct kvm *kvm, struct vgic_its *its,
1027 u32 device_id = its_cmd_get_deviceid(its_cmd);
1028 bool valid = its_cmd_get_validbit(its_cmd);
1029 u8 num_eventid_bits = its_cmd_get_size(its_cmd);
1030 gpa_t itt_addr = its_cmd_get_ittaddr(its_cmd);
1031 struct its_device *device;
1033 if (!vgic_its_check_id(its, its->baser_device_table, device_id, NULL))
1034 return E_ITS_MAPD_DEVICE_OOR;
1036 if (valid && num_eventid_bits > VITS_TYPER_IDBITS)
1037 return E_ITS_MAPD_ITTSIZE_OOR;
1039 device = find_its_device(its, device_id);
1042 * The spec says that calling MAPD on an already mapped device
1043 * invalidates all cached data for this device. We implement this
1044 * by removing the mapping and re-establishing it.
1047 vgic_its_free_device(kvm, device);
1050 * The spec does not say whether unmapping a not-mapped device
1051 * is an error, so we are done in any case.
1056 device = vgic_its_alloc_device(its, device_id, itt_addr,
1059 return PTR_ERR_OR_ZERO(device);
1063 * The MAPC command maps collection IDs to redistributors.
1064 * Must be called with the its_lock mutex held.
1066 static int vgic_its_cmd_handle_mapc(struct kvm *kvm, struct vgic_its *its,
1071 struct its_collection *collection;
1074 valid = its_cmd_get_validbit(its_cmd);
1075 coll_id = its_cmd_get_collection(its_cmd);
1076 target_addr = its_cmd_get_target_addr(its_cmd);
1078 if (target_addr >= atomic_read(&kvm->online_vcpus))
1079 return E_ITS_MAPC_PROCNUM_OOR;
1082 vgic_its_free_collection(its, coll_id);
1084 collection = find_collection(its, coll_id);
1089 ret = vgic_its_alloc_collection(its, &collection,
1093 collection->target_addr = target_addr;
1095 collection->target_addr = target_addr;
1096 update_affinity_collection(kvm, its, collection);
1104 * The CLEAR command removes the pending state for a particular LPI.
1105 * Must be called with the its_lock mutex held.
1107 static int vgic_its_cmd_handle_clear(struct kvm *kvm, struct vgic_its *its,
1110 u32 device_id = its_cmd_get_deviceid(its_cmd);
1111 u32 event_id = its_cmd_get_id(its_cmd);
1112 struct its_ite *ite;
1115 ite = find_ite(its, device_id, event_id);
1117 return E_ITS_CLEAR_UNMAPPED_INTERRUPT;
1119 ite->irq->pending_latch = false;
1122 return irq_set_irqchip_state(ite->irq->host_irq,
1123 IRQCHIP_STATE_PENDING, false);
1129 * The INV command syncs the configuration bits from the memory table.
1130 * Must be called with the its_lock mutex held.
1132 static int vgic_its_cmd_handle_inv(struct kvm *kvm, struct vgic_its *its,
1135 u32 device_id = its_cmd_get_deviceid(its_cmd);
1136 u32 event_id = its_cmd_get_id(its_cmd);
1137 struct its_ite *ite;
1140 ite = find_ite(its, device_id, event_id);
1142 return E_ITS_INV_UNMAPPED_INTERRUPT;
1144 return update_lpi_config(kvm, ite->irq, NULL, true);
1148 * The INVALL command requests flushing of all IRQ data in this collection.
1149 * Find the VCPU mapped to that collection, then iterate over the VM's list
1150 * of mapped LPIs and update the configuration for each IRQ which targets
1151 * the specified vcpu. The configuration will be read from the in-memory
1152 * configuration table.
1153 * Must be called with the its_lock mutex held.
1155 static int vgic_its_cmd_handle_invall(struct kvm *kvm, struct vgic_its *its,
1158 u32 coll_id = its_cmd_get_collection(its_cmd);
1159 struct its_collection *collection;
1160 struct kvm_vcpu *vcpu;
1161 struct vgic_irq *irq;
1165 collection = find_collection(its, coll_id);
1166 if (!its_is_collection_mapped(collection))
1167 return E_ITS_INVALL_UNMAPPED_COLLECTION;
1169 vcpu = kvm_get_vcpu(kvm, collection->target_addr);
1171 irq_count = vgic_copy_lpi_list(kvm, vcpu, &intids);
1175 for (i = 0; i < irq_count; i++) {
1176 irq = vgic_get_irq(kvm, NULL, intids[i]);
1179 update_lpi_config(kvm, irq, vcpu, false);
1180 vgic_put_irq(kvm, irq);
1185 if (vcpu->arch.vgic_cpu.vgic_v3.its_vpe.its_vm)
1186 its_invall_vpe(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe);
1192 * The MOVALL command moves the pending state of all IRQs targeting one
1193 * redistributor to another. We don't hold the pending state in the VCPUs,
1194 * but in the IRQs instead, so there is really not much to do for us here.
1195 * However the spec says that no IRQ must target the old redistributor
1196 * afterwards, so we make sure that no LPI is using the associated target_vcpu.
1197 * This command affects all LPIs in the system that target that redistributor.
1199 static int vgic_its_cmd_handle_movall(struct kvm *kvm, struct vgic_its *its,
1202 u32 target1_addr = its_cmd_get_target_addr(its_cmd);
1203 u32 target2_addr = its_cmd_mask_field(its_cmd, 3, 16, 32);
1204 struct kvm_vcpu *vcpu1, *vcpu2;
1205 struct vgic_irq *irq;
1209 if (target1_addr >= atomic_read(&kvm->online_vcpus) ||
1210 target2_addr >= atomic_read(&kvm->online_vcpus))
1211 return E_ITS_MOVALL_PROCNUM_OOR;
1213 if (target1_addr == target2_addr)
1216 vcpu1 = kvm_get_vcpu(kvm, target1_addr);
1217 vcpu2 = kvm_get_vcpu(kvm, target2_addr);
1219 irq_count = vgic_copy_lpi_list(kvm, vcpu1, &intids);
1223 for (i = 0; i < irq_count; i++) {
1224 irq = vgic_get_irq(kvm, NULL, intids[i]);
1226 update_affinity(irq, vcpu2);
1228 vgic_put_irq(kvm, irq);
1236 * The INT command injects the LPI associated with that DevID/EvID pair.
1237 * Must be called with the its_lock mutex held.
1239 static int vgic_its_cmd_handle_int(struct kvm *kvm, struct vgic_its *its,
1242 u32 msi_data = its_cmd_get_id(its_cmd);
1243 u64 msi_devid = its_cmd_get_deviceid(its_cmd);
1245 return vgic_its_trigger_msi(kvm, its, msi_devid, msi_data);
1249 * This function is called with the its_cmd lock held, but the ITS data
1250 * structure lock dropped.
1252 static int vgic_its_handle_command(struct kvm *kvm, struct vgic_its *its,
1257 mutex_lock(&its->its_lock);
1258 switch (its_cmd_get_command(its_cmd)) {
1260 ret = vgic_its_cmd_handle_mapd(kvm, its, its_cmd);
1263 ret = vgic_its_cmd_handle_mapc(kvm, its, its_cmd);
1266 ret = vgic_its_cmd_handle_mapi(kvm, its, its_cmd);
1268 case GITS_CMD_MAPTI:
1269 ret = vgic_its_cmd_handle_mapi(kvm, its, its_cmd);
1272 ret = vgic_its_cmd_handle_movi(kvm, its, its_cmd);
1274 case GITS_CMD_DISCARD:
1275 ret = vgic_its_cmd_handle_discard(kvm, its, its_cmd);
1277 case GITS_CMD_CLEAR:
1278 ret = vgic_its_cmd_handle_clear(kvm, its, its_cmd);
1280 case GITS_CMD_MOVALL:
1281 ret = vgic_its_cmd_handle_movall(kvm, its, its_cmd);
1284 ret = vgic_its_cmd_handle_int(kvm, its, its_cmd);
1287 ret = vgic_its_cmd_handle_inv(kvm, its, its_cmd);
1289 case GITS_CMD_INVALL:
1290 ret = vgic_its_cmd_handle_invall(kvm, its, its_cmd);
1293 /* we ignore this command: we are in sync all of the time */
1297 mutex_unlock(&its->its_lock);
1302 static u64 vgic_sanitise_its_baser(u64 reg)
1304 reg = vgic_sanitise_field(reg, GITS_BASER_SHAREABILITY_MASK,
1305 GITS_BASER_SHAREABILITY_SHIFT,
1306 vgic_sanitise_shareability);
1307 reg = vgic_sanitise_field(reg, GITS_BASER_INNER_CACHEABILITY_MASK,
1308 GITS_BASER_INNER_CACHEABILITY_SHIFT,
1309 vgic_sanitise_inner_cacheability);
1310 reg = vgic_sanitise_field(reg, GITS_BASER_OUTER_CACHEABILITY_MASK,
1311 GITS_BASER_OUTER_CACHEABILITY_SHIFT,
1312 vgic_sanitise_outer_cacheability);
1314 /* Bits 15:12 contain bits 51:48 of the PA, which we don't support. */
1315 reg &= ~GENMASK_ULL(15, 12);
1317 /* We support only one (ITS) page size: 64K */
1318 reg = (reg & ~GITS_BASER_PAGE_SIZE_MASK) | GITS_BASER_PAGE_SIZE_64K;
1323 static u64 vgic_sanitise_its_cbaser(u64 reg)
1325 reg = vgic_sanitise_field(reg, GITS_CBASER_SHAREABILITY_MASK,
1326 GITS_CBASER_SHAREABILITY_SHIFT,
1327 vgic_sanitise_shareability);
1328 reg = vgic_sanitise_field(reg, GITS_CBASER_INNER_CACHEABILITY_MASK,
1329 GITS_CBASER_INNER_CACHEABILITY_SHIFT,
1330 vgic_sanitise_inner_cacheability);
1331 reg = vgic_sanitise_field(reg, GITS_CBASER_OUTER_CACHEABILITY_MASK,
1332 GITS_CBASER_OUTER_CACHEABILITY_SHIFT,
1333 vgic_sanitise_outer_cacheability);
1336 * Sanitise the physical address to be 64k aligned.
1337 * Also limit the physical addresses to 48 bits.
1339 reg &= ~(GENMASK_ULL(51, 48) | GENMASK_ULL(15, 12));
1344 static unsigned long vgic_mmio_read_its_cbaser(struct kvm *kvm,
1345 struct vgic_its *its,
1346 gpa_t addr, unsigned int len)
1348 return extract_bytes(its->cbaser, addr & 7, len);
1351 static void vgic_mmio_write_its_cbaser(struct kvm *kvm, struct vgic_its *its,
1352 gpa_t addr, unsigned int len,
1355 /* When GITS_CTLR.Enable is 1, this register is RO. */
1359 mutex_lock(&its->cmd_lock);
1360 its->cbaser = update_64bit_reg(its->cbaser, addr & 7, len, val);
1361 its->cbaser = vgic_sanitise_its_cbaser(its->cbaser);
1364 * CWRITER is architecturally UNKNOWN on reset, but we need to reset
1365 * it to CREADR to make sure we start with an empty command buffer.
1367 its->cwriter = its->creadr;
1368 mutex_unlock(&its->cmd_lock);
1371 #define ITS_CMD_BUFFER_SIZE(baser) ((((baser) & 0xff) + 1) << 12)
1372 #define ITS_CMD_SIZE 32
1373 #define ITS_CMD_OFFSET(reg) ((reg) & GENMASK(19, 5))
1375 /* Must be called with the cmd_lock held. */
1376 static void vgic_its_process_commands(struct kvm *kvm, struct vgic_its *its)
1381 /* Commands are only processed when the ITS is enabled. */
1385 cbaser = CBASER_ADDRESS(its->cbaser);
1387 while (its->cwriter != its->creadr) {
1388 int ret = kvm_read_guest_lock(kvm, cbaser + its->creadr,
1389 cmd_buf, ITS_CMD_SIZE);
1391 * If kvm_read_guest() fails, this could be due to the guest
1392 * programming a bogus value in CBASER or something else going
1393 * wrong from which we cannot easily recover.
1394 * According to section 6.3.2 in the GICv3 spec we can just
1395 * ignore that command then.
1398 vgic_its_handle_command(kvm, its, cmd_buf);
1400 its->creadr += ITS_CMD_SIZE;
1401 if (its->creadr == ITS_CMD_BUFFER_SIZE(its->cbaser))
1407 * By writing to CWRITER the guest announces new commands to be processed.
1408 * To avoid any races in the first place, we take the its_cmd lock, which
1409 * protects our ring buffer variables, so that there is only one user
1410 * per ITS handling commands at a given time.
1412 static void vgic_mmio_write_its_cwriter(struct kvm *kvm, struct vgic_its *its,
1413 gpa_t addr, unsigned int len,
1421 mutex_lock(&its->cmd_lock);
1423 reg = update_64bit_reg(its->cwriter, addr & 7, len, val);
1424 reg = ITS_CMD_OFFSET(reg);
1425 if (reg >= ITS_CMD_BUFFER_SIZE(its->cbaser)) {
1426 mutex_unlock(&its->cmd_lock);
1431 vgic_its_process_commands(kvm, its);
1433 mutex_unlock(&its->cmd_lock);
1436 static unsigned long vgic_mmio_read_its_cwriter(struct kvm *kvm,
1437 struct vgic_its *its,
1438 gpa_t addr, unsigned int len)
1440 return extract_bytes(its->cwriter, addr & 0x7, len);
1443 static unsigned long vgic_mmio_read_its_creadr(struct kvm *kvm,
1444 struct vgic_its *its,
1445 gpa_t addr, unsigned int len)
1447 return extract_bytes(its->creadr, addr & 0x7, len);
1450 static int vgic_mmio_uaccess_write_its_creadr(struct kvm *kvm,
1451 struct vgic_its *its,
1452 gpa_t addr, unsigned int len,
1458 mutex_lock(&its->cmd_lock);
1465 cmd_offset = ITS_CMD_OFFSET(val);
1466 if (cmd_offset >= ITS_CMD_BUFFER_SIZE(its->cbaser)) {
1471 its->creadr = cmd_offset;
1473 mutex_unlock(&its->cmd_lock);
1477 #define BASER_INDEX(addr) (((addr) / sizeof(u64)) & 0x7)
1478 static unsigned long vgic_mmio_read_its_baser(struct kvm *kvm,
1479 struct vgic_its *its,
1480 gpa_t addr, unsigned int len)
1484 switch (BASER_INDEX(addr)) {
1486 reg = its->baser_device_table;
1489 reg = its->baser_coll_table;
1496 return extract_bytes(reg, addr & 7, len);
1499 #define GITS_BASER_RO_MASK (GENMASK_ULL(52, 48) | GENMASK_ULL(58, 56))
1500 static void vgic_mmio_write_its_baser(struct kvm *kvm,
1501 struct vgic_its *its,
1502 gpa_t addr, unsigned int len,
1505 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
1506 u64 entry_size, table_type;
1507 u64 reg, *regptr, clearbits = 0;
1509 /* When GITS_CTLR.Enable is 1, we ignore write accesses. */
1513 switch (BASER_INDEX(addr)) {
1515 regptr = &its->baser_device_table;
1516 entry_size = abi->dte_esz;
1517 table_type = GITS_BASER_TYPE_DEVICE;
1520 regptr = &its->baser_coll_table;
1521 entry_size = abi->cte_esz;
1522 table_type = GITS_BASER_TYPE_COLLECTION;
1523 clearbits = GITS_BASER_INDIRECT;
1529 reg = update_64bit_reg(*regptr, addr & 7, len, val);
1530 reg &= ~GITS_BASER_RO_MASK;
1533 reg |= (entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT;
1534 reg |= table_type << GITS_BASER_TYPE_SHIFT;
1535 reg = vgic_sanitise_its_baser(reg);
1539 if (!(reg & GITS_BASER_VALID)) {
1540 /* Take the its_lock to prevent a race with a save/restore */
1541 mutex_lock(&its->its_lock);
1542 switch (table_type) {
1543 case GITS_BASER_TYPE_DEVICE:
1544 vgic_its_free_device_list(kvm, its);
1546 case GITS_BASER_TYPE_COLLECTION:
1547 vgic_its_free_collection_list(kvm, its);
1550 mutex_unlock(&its->its_lock);
1554 static unsigned long vgic_mmio_read_its_ctlr(struct kvm *vcpu,
1555 struct vgic_its *its,
1556 gpa_t addr, unsigned int len)
1560 mutex_lock(&its->cmd_lock);
1561 if (its->creadr == its->cwriter)
1562 reg |= GITS_CTLR_QUIESCENT;
1564 reg |= GITS_CTLR_ENABLE;
1565 mutex_unlock(&its->cmd_lock);
1570 static void vgic_mmio_write_its_ctlr(struct kvm *kvm, struct vgic_its *its,
1571 gpa_t addr, unsigned int len,
1574 mutex_lock(&its->cmd_lock);
1577 * It is UNPREDICTABLE to enable the ITS if any of the CBASER or
1578 * device/collection BASER are invalid
1580 if (!its->enabled && (val & GITS_CTLR_ENABLE) &&
1581 (!(its->baser_device_table & GITS_BASER_VALID) ||
1582 !(its->baser_coll_table & GITS_BASER_VALID) ||
1583 !(its->cbaser & GITS_CBASER_VALID)))
1586 its->enabled = !!(val & GITS_CTLR_ENABLE);
1589 * Try to process any pending commands. This function bails out early
1590 * if the ITS is disabled or no commands have been queued.
1592 vgic_its_process_commands(kvm, its);
1595 mutex_unlock(&its->cmd_lock);
1598 #define REGISTER_ITS_DESC(off, rd, wr, length, acc) \
1600 .reg_offset = off, \
1602 .access_flags = acc, \
1607 #define REGISTER_ITS_DESC_UACCESS(off, rd, wr, uwr, length, acc)\
1609 .reg_offset = off, \
1611 .access_flags = acc, \
1614 .uaccess_its_write = uwr, \
1617 static void its_mmio_write_wi(struct kvm *kvm, struct vgic_its *its,
1618 gpa_t addr, unsigned int len, unsigned long val)
1623 static struct vgic_register_region its_registers[] = {
1624 REGISTER_ITS_DESC(GITS_CTLR,
1625 vgic_mmio_read_its_ctlr, vgic_mmio_write_its_ctlr, 4,
1627 REGISTER_ITS_DESC_UACCESS(GITS_IIDR,
1628 vgic_mmio_read_its_iidr, its_mmio_write_wi,
1629 vgic_mmio_uaccess_write_its_iidr, 4,
1631 REGISTER_ITS_DESC(GITS_TYPER,
1632 vgic_mmio_read_its_typer, its_mmio_write_wi, 8,
1633 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1634 REGISTER_ITS_DESC(GITS_CBASER,
1635 vgic_mmio_read_its_cbaser, vgic_mmio_write_its_cbaser, 8,
1636 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1637 REGISTER_ITS_DESC(GITS_CWRITER,
1638 vgic_mmio_read_its_cwriter, vgic_mmio_write_its_cwriter, 8,
1639 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1640 REGISTER_ITS_DESC_UACCESS(GITS_CREADR,
1641 vgic_mmio_read_its_creadr, its_mmio_write_wi,
1642 vgic_mmio_uaccess_write_its_creadr, 8,
1643 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1644 REGISTER_ITS_DESC(GITS_BASER,
1645 vgic_mmio_read_its_baser, vgic_mmio_write_its_baser, 0x40,
1646 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1647 REGISTER_ITS_DESC(GITS_IDREGS_BASE,
1648 vgic_mmio_read_its_idregs, its_mmio_write_wi, 0x30,
1652 /* This is called on setting the LPI enable bit in the redistributor. */
1653 void vgic_enable_lpis(struct kvm_vcpu *vcpu)
1655 if (!(vcpu->arch.vgic_cpu.pendbaser & GICR_PENDBASER_PTZ))
1656 its_sync_lpi_pending_table(vcpu);
1659 static int vgic_register_its_iodev(struct kvm *kvm, struct vgic_its *its,
1662 struct vgic_io_device *iodev = &its->iodev;
1665 mutex_lock(&kvm->slots_lock);
1666 if (!IS_VGIC_ADDR_UNDEF(its->vgic_its_base)) {
1671 its->vgic_its_base = addr;
1672 iodev->regions = its_registers;
1673 iodev->nr_regions = ARRAY_SIZE(its_registers);
1674 kvm_iodevice_init(&iodev->dev, &kvm_io_gic_ops);
1676 iodev->base_addr = its->vgic_its_base;
1677 iodev->iodev_type = IODEV_ITS;
1679 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, iodev->base_addr,
1680 KVM_VGIC_V3_ITS_SIZE, &iodev->dev);
1682 mutex_unlock(&kvm->slots_lock);
1687 #define INITIAL_BASER_VALUE \
1688 (GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb) | \
1689 GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, SameAsInner) | \
1690 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) | \
1691 GITS_BASER_PAGE_SIZE_64K)
1693 #define INITIAL_PROPBASER_VALUE \
1694 (GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb) | \
1695 GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, SameAsInner) | \
1696 GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable))
1698 static int vgic_its_create(struct kvm_device *dev, u32 type)
1700 struct vgic_its *its;
1702 if (type != KVM_DEV_TYPE_ARM_VGIC_ITS)
1705 its = kzalloc(sizeof(struct vgic_its), GFP_KERNEL);
1709 if (vgic_initialized(dev->kvm)) {
1710 int ret = vgic_v4_init(dev->kvm);
1717 mutex_init(&its->its_lock);
1718 mutex_init(&its->cmd_lock);
1720 its->vgic_its_base = VGIC_ADDR_UNDEF;
1722 INIT_LIST_HEAD(&its->device_list);
1723 INIT_LIST_HEAD(&its->collection_list);
1725 dev->kvm->arch.vgic.msis_require_devid = true;
1726 dev->kvm->arch.vgic.has_its = true;
1727 its->enabled = false;
1730 its->baser_device_table = INITIAL_BASER_VALUE |
1731 ((u64)GITS_BASER_TYPE_DEVICE << GITS_BASER_TYPE_SHIFT);
1732 its->baser_coll_table = INITIAL_BASER_VALUE |
1733 ((u64)GITS_BASER_TYPE_COLLECTION << GITS_BASER_TYPE_SHIFT);
1734 dev->kvm->arch.vgic.propbaser = INITIAL_PROPBASER_VALUE;
1738 return vgic_its_set_abi(its, NR_ITS_ABIS - 1);
1741 static void vgic_its_destroy(struct kvm_device *kvm_dev)
1743 struct kvm *kvm = kvm_dev->kvm;
1744 struct vgic_its *its = kvm_dev->private;
1746 mutex_lock(&its->its_lock);
1748 vgic_its_free_device_list(kvm, its);
1749 vgic_its_free_collection_list(kvm, its);
1751 mutex_unlock(&its->its_lock);
1753 kfree(kvm_dev);/* alloc by kvm_ioctl_create_device, free by .destroy */
1756 int vgic_its_has_attr_regs(struct kvm_device *dev,
1757 struct kvm_device_attr *attr)
1759 const struct vgic_register_region *region;
1760 gpa_t offset = attr->attr;
1763 align = (offset < GITS_TYPER) || (offset >= GITS_PIDR4) ? 0x3 : 0x7;
1768 region = vgic_find_mmio_region(its_registers,
1769 ARRAY_SIZE(its_registers),
1777 int vgic_its_attr_regs_access(struct kvm_device *dev,
1778 struct kvm_device_attr *attr,
1779 u64 *reg, bool is_write)
1781 const struct vgic_register_region *region;
1782 struct vgic_its *its;
1788 offset = attr->attr;
1791 * Although the spec supports upper/lower 32-bit accesses to
1792 * 64-bit ITS registers, the userspace ABI requires 64-bit
1793 * accesses to all 64-bit wide registers. We therefore only
1794 * support 32-bit accesses to GITS_CTLR, GITS_IIDR and GITS ID
1797 if ((offset < GITS_TYPER) || (offset >= GITS_PIDR4))
1805 mutex_lock(&dev->kvm->lock);
1807 if (IS_VGIC_ADDR_UNDEF(its->vgic_its_base)) {
1812 region = vgic_find_mmio_region(its_registers,
1813 ARRAY_SIZE(its_registers),
1820 if (!lock_all_vcpus(dev->kvm)) {
1825 addr = its->vgic_its_base + offset;
1827 len = region->access_flags & VGIC_ACCESS_64bit ? 8 : 4;
1830 if (region->uaccess_its_write)
1831 ret = region->uaccess_its_write(dev->kvm, its, addr,
1834 region->its_write(dev->kvm, its, addr, len, *reg);
1836 *reg = region->its_read(dev->kvm, its, addr, len);
1838 unlock_all_vcpus(dev->kvm);
1840 mutex_unlock(&dev->kvm->lock);
1844 static u32 compute_next_devid_offset(struct list_head *h,
1845 struct its_device *dev)
1847 struct its_device *next;
1850 if (list_is_last(&dev->dev_list, h))
1852 next = list_next_entry(dev, dev_list);
1853 next_offset = next->device_id - dev->device_id;
1855 return min_t(u32, next_offset, VITS_DTE_MAX_DEVID_OFFSET);
1858 static u32 compute_next_eventid_offset(struct list_head *h, struct its_ite *ite)
1860 struct its_ite *next;
1863 if (list_is_last(&ite->ite_list, h))
1865 next = list_next_entry(ite, ite_list);
1866 next_offset = next->event_id - ite->event_id;
1868 return min_t(u32, next_offset, VITS_ITE_MAX_EVENTID_OFFSET);
1872 * entry_fn_t - Callback called on a table entry restore path
1874 * @id: id of the entry
1875 * @entry: pointer to the entry
1876 * @opaque: pointer to an opaque data
1878 * Return: < 0 on error, 0 if last element was identified, id offset to next
1881 typedef int (*entry_fn_t)(struct vgic_its *its, u32 id, void *entry,
1885 * scan_its_table - Scan a contiguous table in guest RAM and applies a function
1889 * @base: base gpa of the table
1890 * @size: size of the table in bytes
1891 * @esz: entry size in bytes
1892 * @start_id: the ID of the first entry in the table
1893 * (non zero for 2d level tables)
1894 * @fn: function to apply on each entry
1896 * Return: < 0 on error, 0 if last element was identified, 1 otherwise
1897 * (the last element may not be found on second level tables)
1899 static int scan_its_table(struct vgic_its *its, gpa_t base, int size, u32 esz,
1900 int start_id, entry_fn_t fn, void *opaque)
1902 struct kvm *kvm = its->dev->kvm;
1903 unsigned long len = size;
1906 char entry[ESZ_MAX];
1909 memset(entry, 0, esz);
1915 ret = kvm_read_guest_lock(kvm, gpa, entry, esz);
1919 next_offset = fn(its, id, entry, opaque);
1920 if (next_offset <= 0)
1923 byte_offset = next_offset * esz;
1932 * vgic_its_save_ite - Save an interrupt translation entry at @gpa
1934 static int vgic_its_save_ite(struct vgic_its *its, struct its_device *dev,
1935 struct its_ite *ite, gpa_t gpa, int ite_esz)
1937 struct kvm *kvm = its->dev->kvm;
1941 next_offset = compute_next_eventid_offset(&dev->itt_head, ite);
1942 val = ((u64)next_offset << KVM_ITS_ITE_NEXT_SHIFT) |
1943 ((u64)ite->irq->intid << KVM_ITS_ITE_PINTID_SHIFT) |
1944 ite->collection->collection_id;
1945 val = cpu_to_le64(val);
1946 return kvm_write_guest_lock(kvm, gpa, &val, ite_esz);
1950 * vgic_its_restore_ite - restore an interrupt translation entry
1951 * @event_id: id used for indexing
1952 * @ptr: pointer to the ITE entry
1953 * @opaque: pointer to the its_device
1955 static int vgic_its_restore_ite(struct vgic_its *its, u32 event_id,
1956 void *ptr, void *opaque)
1958 struct its_device *dev = (struct its_device *)opaque;
1959 struct its_collection *collection;
1960 struct kvm *kvm = its->dev->kvm;
1961 struct kvm_vcpu *vcpu = NULL;
1963 u64 *p = (u64 *)ptr;
1964 struct vgic_irq *irq;
1965 u32 coll_id, lpi_id;
1966 struct its_ite *ite;
1971 val = le64_to_cpu(val);
1973 coll_id = val & KVM_ITS_ITE_ICID_MASK;
1974 lpi_id = (val & KVM_ITS_ITE_PINTID_MASK) >> KVM_ITS_ITE_PINTID_SHIFT;
1977 return 1; /* invalid entry, no choice but to scan next entry */
1979 if (lpi_id < VGIC_MIN_LPI)
1982 offset = val >> KVM_ITS_ITE_NEXT_SHIFT;
1983 if (event_id + offset >= BIT_ULL(dev->num_eventid_bits))
1986 collection = find_collection(its, coll_id);
1990 ite = vgic_its_alloc_ite(dev, collection, event_id);
1992 return PTR_ERR(ite);
1994 if (its_is_collection_mapped(collection))
1995 vcpu = kvm_get_vcpu(kvm, collection->target_addr);
1997 irq = vgic_add_lpi(kvm, lpi_id, vcpu);
1999 return PTR_ERR(irq);
2005 static int vgic_its_ite_cmp(void *priv, struct list_head *a,
2006 struct list_head *b)
2008 struct its_ite *itea = container_of(a, struct its_ite, ite_list);
2009 struct its_ite *iteb = container_of(b, struct its_ite, ite_list);
2011 if (itea->event_id < iteb->event_id)
2017 static int vgic_its_save_itt(struct vgic_its *its, struct its_device *device)
2019 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2020 gpa_t base = device->itt_addr;
2021 struct its_ite *ite;
2023 int ite_esz = abi->ite_esz;
2025 list_sort(NULL, &device->itt_head, vgic_its_ite_cmp);
2027 list_for_each_entry(ite, &device->itt_head, ite_list) {
2028 gpa_t gpa = base + ite->event_id * ite_esz;
2031 * If an LPI carries the HW bit, this means that this
2032 * interrupt is controlled by GICv4, and we do not
2033 * have direct access to that state. Let's simply fail
2034 * the save operation...
2039 ret = vgic_its_save_ite(its, device, ite, gpa, ite_esz);
2047 * vgic_its_restore_itt - restore the ITT of a device
2050 * @dev: device handle
2052 * Return 0 on success, < 0 on error
2054 static int vgic_its_restore_itt(struct vgic_its *its, struct its_device *dev)
2056 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2057 gpa_t base = dev->itt_addr;
2059 int ite_esz = abi->ite_esz;
2060 size_t max_size = BIT_ULL(dev->num_eventid_bits) * ite_esz;
2062 ret = scan_its_table(its, base, max_size, ite_esz, 0,
2063 vgic_its_restore_ite, dev);
2065 /* scan_its_table returns +1 if all ITEs are invalid */
2073 * vgic_its_save_dte - Save a device table entry at a given GPA
2079 static int vgic_its_save_dte(struct vgic_its *its, struct its_device *dev,
2080 gpa_t ptr, int dte_esz)
2082 struct kvm *kvm = its->dev->kvm;
2083 u64 val, itt_addr_field;
2086 itt_addr_field = dev->itt_addr >> 8;
2087 next_offset = compute_next_devid_offset(&its->device_list, dev);
2088 val = (1ULL << KVM_ITS_DTE_VALID_SHIFT |
2089 ((u64)next_offset << KVM_ITS_DTE_NEXT_SHIFT) |
2090 (itt_addr_field << KVM_ITS_DTE_ITTADDR_SHIFT) |
2091 (dev->num_eventid_bits - 1));
2092 val = cpu_to_le64(val);
2093 return kvm_write_guest_lock(kvm, ptr, &val, dte_esz);
2097 * vgic_its_restore_dte - restore a device table entry
2100 * @id: device id the DTE corresponds to
2101 * @ptr: kernel VA where the 8 byte DTE is located
2104 * Return: < 0 on error, 0 if the dte is the last one, id offset to the
2105 * next dte otherwise
2107 static int vgic_its_restore_dte(struct vgic_its *its, u32 id,
2108 void *ptr, void *opaque)
2110 struct its_device *dev;
2112 u8 num_eventid_bits;
2113 u64 entry = *(u64 *)ptr;
2118 entry = le64_to_cpu(entry);
2120 valid = entry >> KVM_ITS_DTE_VALID_SHIFT;
2121 num_eventid_bits = (entry & KVM_ITS_DTE_SIZE_MASK) + 1;
2122 itt_addr = ((entry & KVM_ITS_DTE_ITTADDR_MASK)
2123 >> KVM_ITS_DTE_ITTADDR_SHIFT) << 8;
2128 /* dte entry is valid */
2129 offset = (entry & KVM_ITS_DTE_NEXT_MASK) >> KVM_ITS_DTE_NEXT_SHIFT;
2131 dev = vgic_its_alloc_device(its, id, itt_addr, num_eventid_bits);
2133 return PTR_ERR(dev);
2135 ret = vgic_its_restore_itt(its, dev);
2137 vgic_its_free_device(its->dev->kvm, dev);
2144 static int vgic_its_device_cmp(void *priv, struct list_head *a,
2145 struct list_head *b)
2147 struct its_device *deva = container_of(a, struct its_device, dev_list);
2148 struct its_device *devb = container_of(b, struct its_device, dev_list);
2150 if (deva->device_id < devb->device_id)
2157 * vgic_its_save_device_tables - Save the device table and all ITT
2160 * L1/L2 handling is hidden by vgic_its_check_id() helper which directly
2161 * returns the GPA of the device entry
2163 static int vgic_its_save_device_tables(struct vgic_its *its)
2165 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2166 u64 baser = its->baser_device_table;
2167 struct its_device *dev;
2168 int dte_esz = abi->dte_esz;
2170 if (!(baser & GITS_BASER_VALID))
2173 list_sort(NULL, &its->device_list, vgic_its_device_cmp);
2175 list_for_each_entry(dev, &its->device_list, dev_list) {
2179 if (!vgic_its_check_id(its, baser,
2180 dev->device_id, &eaddr))
2183 ret = vgic_its_save_itt(its, dev);
2187 ret = vgic_its_save_dte(its, dev, eaddr, dte_esz);
2195 * handle_l1_dte - callback used for L1 device table entries (2 stage case)
2198 * @id: index of the entry in the L1 table
2202 * L1 table entries are scanned by steps of 1 entry
2203 * Return < 0 if error, 0 if last dte was found when scanning the L2
2204 * table, +1 otherwise (meaning next L1 entry must be scanned)
2206 static int handle_l1_dte(struct vgic_its *its, u32 id, void *addr,
2209 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2210 int l2_start_id = id * (SZ_64K / abi->dte_esz);
2211 u64 entry = *(u64 *)addr;
2212 int dte_esz = abi->dte_esz;
2216 entry = le64_to_cpu(entry);
2218 if (!(entry & KVM_ITS_L1E_VALID_MASK))
2221 gpa = entry & KVM_ITS_L1E_ADDR_MASK;
2223 ret = scan_its_table(its, gpa, SZ_64K, dte_esz,
2224 l2_start_id, vgic_its_restore_dte, NULL);
2230 * vgic_its_restore_device_tables - Restore the device table and all ITT
2231 * from guest RAM to internal data structs
2233 static int vgic_its_restore_device_tables(struct vgic_its *its)
2235 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2236 u64 baser = its->baser_device_table;
2238 int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
2241 if (!(baser & GITS_BASER_VALID))
2244 l1_gpa = BASER_ADDRESS(baser);
2246 if (baser & GITS_BASER_INDIRECT) {
2247 l1_esz = GITS_LVL1_ENTRY_SIZE;
2248 ret = scan_its_table(its, l1_gpa, l1_tbl_size, l1_esz, 0,
2249 handle_l1_dte, NULL);
2251 l1_esz = abi->dte_esz;
2252 ret = scan_its_table(its, l1_gpa, l1_tbl_size, l1_esz, 0,
2253 vgic_its_restore_dte, NULL);
2256 /* scan_its_table returns +1 if all entries are invalid */
2263 static int vgic_its_save_cte(struct vgic_its *its,
2264 struct its_collection *collection,
2269 val = (1ULL << KVM_ITS_CTE_VALID_SHIFT |
2270 ((u64)collection->target_addr << KVM_ITS_CTE_RDBASE_SHIFT) |
2271 collection->collection_id);
2272 val = cpu_to_le64(val);
2273 return kvm_write_guest_lock(its->dev->kvm, gpa, &val, esz);
2276 static int vgic_its_restore_cte(struct vgic_its *its, gpa_t gpa, int esz)
2278 struct its_collection *collection;
2279 struct kvm *kvm = its->dev->kvm;
2280 u32 target_addr, coll_id;
2284 BUG_ON(esz > sizeof(val));
2285 ret = kvm_read_guest_lock(kvm, gpa, &val, esz);
2288 val = le64_to_cpu(val);
2289 if (!(val & KVM_ITS_CTE_VALID_MASK))
2292 target_addr = (u32)(val >> KVM_ITS_CTE_RDBASE_SHIFT);
2293 coll_id = val & KVM_ITS_CTE_ICID_MASK;
2295 if (target_addr >= atomic_read(&kvm->online_vcpus))
2298 collection = find_collection(its, coll_id);
2301 ret = vgic_its_alloc_collection(its, &collection, coll_id);
2304 collection->target_addr = target_addr;
2309 * vgic_its_save_collection_table - Save the collection table into
2312 static int vgic_its_save_collection_table(struct vgic_its *its)
2314 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2315 u64 baser = its->baser_coll_table;
2316 gpa_t gpa = BASER_ADDRESS(baser);
2317 struct its_collection *collection;
2319 size_t max_size, filled = 0;
2320 int ret, cte_esz = abi->cte_esz;
2322 if (!(baser & GITS_BASER_VALID))
2325 max_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
2327 list_for_each_entry(collection, &its->collection_list, coll_list) {
2328 ret = vgic_its_save_cte(its, collection, gpa, cte_esz);
2335 if (filled == max_size)
2339 * table is not fully filled, add a last dummy element
2340 * with valid bit unset
2343 BUG_ON(cte_esz > sizeof(val));
2344 ret = kvm_write_guest_lock(its->dev->kvm, gpa, &val, cte_esz);
2349 * vgic_its_restore_collection_table - reads the collection table
2350 * in guest memory and restores the ITS internal state. Requires the
2351 * BASER registers to be restored before.
2353 static int vgic_its_restore_collection_table(struct vgic_its *its)
2355 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2356 u64 baser = its->baser_coll_table;
2357 int cte_esz = abi->cte_esz;
2358 size_t max_size, read = 0;
2362 if (!(baser & GITS_BASER_VALID))
2365 gpa = BASER_ADDRESS(baser);
2367 max_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
2369 while (read < max_size) {
2370 ret = vgic_its_restore_cte(its, gpa, cte_esz);
2384 * vgic_its_save_tables_v0 - Save the ITS tables into guest ARM
2385 * according to v0 ABI
2387 static int vgic_its_save_tables_v0(struct vgic_its *its)
2391 ret = vgic_its_save_device_tables(its);
2395 return vgic_its_save_collection_table(its);
2399 * vgic_its_restore_tables_v0 - Restore the ITS tables from guest RAM
2400 * to internal data structs according to V0 ABI
2403 static int vgic_its_restore_tables_v0(struct vgic_its *its)
2407 ret = vgic_its_restore_collection_table(its);
2411 return vgic_its_restore_device_tables(its);
2414 static int vgic_its_commit_v0(struct vgic_its *its)
2416 const struct vgic_its_abi *abi;
2418 abi = vgic_its_get_abi(its);
2419 its->baser_coll_table &= ~GITS_BASER_ENTRY_SIZE_MASK;
2420 its->baser_device_table &= ~GITS_BASER_ENTRY_SIZE_MASK;
2422 its->baser_coll_table |= (GIC_ENCODE_SZ(abi->cte_esz, 5)
2423 << GITS_BASER_ENTRY_SIZE_SHIFT);
2425 its->baser_device_table |= (GIC_ENCODE_SZ(abi->dte_esz, 5)
2426 << GITS_BASER_ENTRY_SIZE_SHIFT);
2430 static void vgic_its_reset(struct kvm *kvm, struct vgic_its *its)
2432 /* We need to keep the ABI specific field values */
2433 its->baser_coll_table &= ~GITS_BASER_VALID;
2434 its->baser_device_table &= ~GITS_BASER_VALID;
2439 vgic_its_free_device_list(kvm, its);
2440 vgic_its_free_collection_list(kvm, its);
2443 static int vgic_its_has_attr(struct kvm_device *dev,
2444 struct kvm_device_attr *attr)
2446 switch (attr->group) {
2447 case KVM_DEV_ARM_VGIC_GRP_ADDR:
2448 switch (attr->attr) {
2449 case KVM_VGIC_ITS_ADDR_TYPE:
2453 case KVM_DEV_ARM_VGIC_GRP_CTRL:
2454 switch (attr->attr) {
2455 case KVM_DEV_ARM_VGIC_CTRL_INIT:
2457 case KVM_DEV_ARM_ITS_CTRL_RESET:
2459 case KVM_DEV_ARM_ITS_SAVE_TABLES:
2461 case KVM_DEV_ARM_ITS_RESTORE_TABLES:
2465 case KVM_DEV_ARM_VGIC_GRP_ITS_REGS:
2466 return vgic_its_has_attr_regs(dev, attr);
2471 static int vgic_its_ctrl(struct kvm *kvm, struct vgic_its *its, u64 attr)
2473 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2476 if (attr == KVM_DEV_ARM_VGIC_CTRL_INIT) /* Nothing to do */
2479 mutex_lock(&kvm->lock);
2480 mutex_lock(&its->its_lock);
2482 if (!lock_all_vcpus(kvm)) {
2483 mutex_unlock(&its->its_lock);
2484 mutex_unlock(&kvm->lock);
2489 case KVM_DEV_ARM_ITS_CTRL_RESET:
2490 vgic_its_reset(kvm, its);
2492 case KVM_DEV_ARM_ITS_SAVE_TABLES:
2493 ret = abi->save_tables(its);
2495 case KVM_DEV_ARM_ITS_RESTORE_TABLES:
2496 ret = abi->restore_tables(its);
2500 unlock_all_vcpus(kvm);
2501 mutex_unlock(&its->its_lock);
2502 mutex_unlock(&kvm->lock);
2506 static int vgic_its_set_attr(struct kvm_device *dev,
2507 struct kvm_device_attr *attr)
2509 struct vgic_its *its = dev->private;
2512 switch (attr->group) {
2513 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2514 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2515 unsigned long type = (unsigned long)attr->attr;
2518 if (type != KVM_VGIC_ITS_ADDR_TYPE)
2521 if (copy_from_user(&addr, uaddr, sizeof(addr)))
2524 ret = vgic_check_ioaddr(dev->kvm, &its->vgic_its_base,
2529 return vgic_register_its_iodev(dev->kvm, its, addr);
2531 case KVM_DEV_ARM_VGIC_GRP_CTRL:
2532 return vgic_its_ctrl(dev->kvm, its, attr->attr);
2533 case KVM_DEV_ARM_VGIC_GRP_ITS_REGS: {
2534 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2537 if (get_user(reg, uaddr))
2540 return vgic_its_attr_regs_access(dev, attr, ®, true);
2546 static int vgic_its_get_attr(struct kvm_device *dev,
2547 struct kvm_device_attr *attr)
2549 switch (attr->group) {
2550 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2551 struct vgic_its *its = dev->private;
2552 u64 addr = its->vgic_its_base;
2553 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2554 unsigned long type = (unsigned long)attr->attr;
2556 if (type != KVM_VGIC_ITS_ADDR_TYPE)
2559 if (copy_to_user(uaddr, &addr, sizeof(addr)))
2563 case KVM_DEV_ARM_VGIC_GRP_ITS_REGS: {
2564 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2568 ret = vgic_its_attr_regs_access(dev, attr, ®, false);
2571 return put_user(reg, uaddr);
2580 static struct kvm_device_ops kvm_arm_vgic_its_ops = {
2581 .name = "kvm-arm-vgic-its",
2582 .create = vgic_its_create,
2583 .destroy = vgic_its_destroy,
2584 .set_attr = vgic_its_set_attr,
2585 .get_attr = vgic_its_get_attr,
2586 .has_attr = vgic_its_has_attr,
2589 int kvm_vgic_register_its_device(void)
2591 return kvm_register_device_ops(&kvm_arm_vgic_its_ops,
2592 KVM_DEV_TYPE_ARM_VGIC_ITS);