4 #include <linux/types.h>
5 #include <asm/ioctls.h>
8 * Machine Check support for x86
11 /* MCG_CAP register defines */
12 #define MCG_BANKCNT_MASK 0xff /* Number of Banks */
13 #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
14 #define MCG_EXT_P (1ULL<<9) /* Extended registers available */
15 #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
16 #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
17 #define MCG_EXT_CNT_SHIFT 16
18 #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
19 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
21 /* MCG_STATUS register defines */
22 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
23 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
24 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
26 /* MCi_STATUS register defines */
27 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
28 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
29 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
30 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
31 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
32 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
33 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
34 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
35 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
36 #define MCACOD 0xffff /* MCA Error Code */
38 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
39 #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
40 #define MCACOD_SCRUBMSK 0xfff0
41 #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
42 #define MCACOD_DATA 0x0134 /* Data Load */
43 #define MCACOD_INSTR 0x0150 /* Instruction Fetch */
45 /* MCi_MISC register defines */
46 #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
47 #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
48 #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
49 #define MCI_MISC_ADDR_LINEAR 1 /* linear address */
50 #define MCI_MISC_ADDR_PHYS 2 /* physical address */
51 #define MCI_MISC_ADDR_MEM 3 /* memory address */
52 #define MCI_MISC_ADDR_GENERIC 7 /* generic */
54 /* CTL2 register defines */
55 #define MCI_CTL2_CMCI_EN (1ULL << 30)
56 #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
58 #define MCJ_CTX_MASK 3
59 #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
60 #define MCJ_CTX_RANDOM 0 /* inject context: random */
61 #define MCJ_CTX_PROCESS 0x1 /* inject context: process */
62 #define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
63 #define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
64 #define MCJ_EXCEPTION 0x8 /* raise as exception */
65 #define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */
67 /* Fields are zero when not available */
74 __u64 tsc; /* cpu time stamp counter */
75 __u64 time; /* wall time_t when error was detected */
76 __u8 cpuvendor; /* cpu vendor as encoded in system.h */
77 __u8 inject_flags; /* software inject flags */
79 __u32 cpuid; /* CPUID 1 EAX */
80 __u8 cs; /* code segment */
81 __u8 bank; /* machine check bank */
82 __u8 cpu; /* cpu number; obsolete; use extcpu now */
83 __u8 finished; /* entry is valid */
84 __u32 extcpu; /* linux cpu number that detected the error */
85 __u32 socketid; /* CPU socket ID */
86 __u32 apicid; /* CPU initial apic ID */
87 __u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */
91 * This structure contains all data related to the MCE log. Also
92 * carries a signature to make it easier to find from external
93 * debugging tools. Each entry is only valid when its finished flag
97 #define MCE_LOG_LEN 32
100 char signature[12]; /* "MACHINECHECK" */
101 unsigned len; /* = MCE_LOG_LEN */
104 unsigned recordlen; /* length of struct mce */
105 struct mce entry[MCE_LOG_LEN];
108 #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
110 #define MCE_LOG_SIGNATURE "MACHINECHECK"
112 #define MCE_GET_RECORD_LEN _IOR('M', 1, int)
113 #define MCE_GET_LOG_LEN _IOR('M', 2, int)
114 #define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
116 /* Software defined banks */
117 #define MCE_EXTENDED_BANK 128
118 #define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
119 #define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1)
121 #endif /* _ASM_X86_MCE_H */