2 * User emulator execution
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "disas/disas.h"
22 #include "exec/exec-all.h"
24 #include "qemu/bitops.h"
25 #include "exec/cpu_ldst.h"
26 #include "translate-all.h"
38 #include <sys/ucontext.h>
41 //#define DEBUG_SIGNAL
43 static void exception_action(CPUState *cpu)
45 #if defined(TARGET_I386)
46 X86CPU *x86_cpu = X86_CPU(cpu);
47 CPUX86State *env1 = &x86_cpu->env;
49 raise_exception_err(env1, cpu->exception_index, env1->error_code);
55 /* exit the current TB from a signal handler. The host registers are
56 restored in a state compatible with the CPU emulator
58 static void cpu_exit_tb_from_sighandler(CPUState *cpu, sigset_t *old_set)
60 /* XXX: use siglongjmp ? */
61 sigprocmask(SIG_SETMASK, old_set, NULL);
62 cpu_loop_exit_noexc(cpu);
65 /* 'pc' is the host PC at which the exception was raised. 'address' is
66 the effective address of the memory exception. 'is_write' is 1 if a
67 write caused the exception and otherwise 0'. 'old_set' is the
68 signal set which should be restored */
69 static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
70 int is_write, sigset_t *old_set)
76 #if defined(DEBUG_SIGNAL)
77 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
78 pc, address, is_write, *(unsigned long *)old_set);
80 /* XXX: locking issue */
81 if (is_write && h2g_valid(address)) {
82 switch (page_unprotect(h2g(address), pc)) {
84 /* Fault not caused by a page marked unwritable to protect
85 * cached translations, must be the guest binary's problem
89 /* Fault caused by protection of cached translation; TBs
90 * invalidated, so resume execution
94 /* Fault caused by protection of cached translation, and the
95 * currently executing TB was modified and must be exited
98 cpu_exit_tb_from_sighandler(current_cpu, old_set);
99 g_assert_not_reached();
101 g_assert_not_reached();
105 /* Convert forcefully to guest address space, invalid addresses
106 are still valid segv ones */
107 address = h2g_nocheck(address);
110 cc = CPU_GET_CLASS(cpu);
111 /* see if it is an MMU fault */
112 g_assert(cc->handle_mmu_fault);
113 ret = cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX);
115 return 0; /* not an MMU fault */
118 return 1; /* the MMU fault was handled without causing real CPU fault */
120 /* now we have a real cpu fault */
121 cpu_restore_state(cpu, pc);
123 /* we restore the process signal mask as the sigreturn should
124 do it (XXX: use sigsetjmp) */
125 sigprocmask(SIG_SETMASK, old_set, NULL);
126 exception_action(cpu);
128 /* never comes here */
132 #if defined(__i386__)
134 #if defined(__APPLE__)
135 #include <sys/ucontext.h>
137 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext->ss.eip))
138 #define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
139 #define ERROR_sig(context) ((context)->uc_mcontext->es.err)
140 #define MASK_sig(context) ((context)->uc_sigmask)
141 #elif defined(__NetBSD__)
142 #include <ucontext.h>
144 #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
145 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
146 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
147 #define MASK_sig(context) ((context)->uc_sigmask)
148 #elif defined(__FreeBSD__) || defined(__DragonFly__)
149 #include <ucontext.h>
151 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
152 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
153 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
154 #define MASK_sig(context) ((context)->uc_sigmask)
155 #elif defined(__OpenBSD__)
156 #define EIP_sig(context) ((context)->sc_eip)
157 #define TRAP_sig(context) ((context)->sc_trapno)
158 #define ERROR_sig(context) ((context)->sc_err)
159 #define MASK_sig(context) ((context)->sc_mask)
161 #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
162 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
163 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
164 #define MASK_sig(context) ((context)->uc_sigmask)
167 int cpu_signal_handler(int host_signum, void *pinfo,
170 siginfo_t *info = pinfo;
171 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
172 ucontext_t *uc = puc;
173 #elif defined(__OpenBSD__)
174 struct sigcontext *uc = puc;
176 struct ucontext *uc = puc;
185 #define REG_TRAPNO TRAPNO
188 trapno = TRAP_sig(uc);
189 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
191 (ERROR_sig(uc) >> 1) & 1 : 0,
195 #elif defined(__x86_64__)
198 #define PC_sig(context) _UC_MACHINE_PC(context)
199 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
200 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
201 #define MASK_sig(context) ((context)->uc_sigmask)
202 #elif defined(__OpenBSD__)
203 #define PC_sig(context) ((context)->sc_rip)
204 #define TRAP_sig(context) ((context)->sc_trapno)
205 #define ERROR_sig(context) ((context)->sc_err)
206 #define MASK_sig(context) ((context)->sc_mask)
207 #elif defined(__FreeBSD__) || defined(__DragonFly__)
208 #include <ucontext.h>
210 #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
211 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
212 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
213 #define MASK_sig(context) ((context)->uc_sigmask)
215 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
216 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
217 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
218 #define MASK_sig(context) ((context)->uc_sigmask)
221 int cpu_signal_handler(int host_signum, void *pinfo,
224 siginfo_t *info = pinfo;
226 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
227 ucontext_t *uc = puc;
228 #elif defined(__OpenBSD__)
229 struct sigcontext *uc = puc;
231 struct ucontext *uc = puc;
235 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
236 TRAP_sig(uc) == 0xe ?
237 (ERROR_sig(uc) >> 1) & 1 : 0,
241 #elif defined(_ARCH_PPC)
243 /***********************************************************************
244 * signal context platform-specific definitions
248 /* All Registers access - only for local access */
249 #define REG_sig(reg_name, context) \
250 ((context)->uc_mcontext.regs->reg_name)
251 /* Gpr Registers access */
252 #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
253 /* Program counter */
254 #define IAR_sig(context) REG_sig(nip, context)
255 /* Machine State Register (Supervisor) */
256 #define MSR_sig(context) REG_sig(msr, context)
258 #define CTR_sig(context) REG_sig(ctr, context)
259 /* User's integer exception register */
260 #define XER_sig(context) REG_sig(xer, context)
262 #define LR_sig(context) REG_sig(link, context)
263 /* Condition register */
264 #define CR_sig(context) REG_sig(ccr, context)
266 /* Float Registers access */
267 #define FLOAT_sig(reg_num, context) \
268 (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
269 #define FPSCR_sig(context) \
270 (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
271 /* Exception Registers access */
272 #define DAR_sig(context) REG_sig(dar, context)
273 #define DSISR_sig(context) REG_sig(dsisr, context)
274 #define TRAP_sig(context) REG_sig(trap, context)
277 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
278 #include <ucontext.h>
279 #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
280 #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
281 #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
282 #define XER_sig(context) ((context)->uc_mcontext.mc_xer)
283 #define LR_sig(context) ((context)->uc_mcontext.mc_lr)
284 #define CR_sig(context) ((context)->uc_mcontext.mc_cr)
285 /* Exception Registers access */
286 #define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
287 #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
288 #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
289 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
292 #include <sys/ucontext.h>
293 typedef struct ucontext SIGCONTEXT;
294 /* All Registers access - only for local access */
295 #define REG_sig(reg_name, context) \
296 ((context)->uc_mcontext->ss.reg_name)
297 #define FLOATREG_sig(reg_name, context) \
298 ((context)->uc_mcontext->fs.reg_name)
299 #define EXCEPREG_sig(reg_name, context) \
300 ((context)->uc_mcontext->es.reg_name)
301 #define VECREG_sig(reg_name, context) \
302 ((context)->uc_mcontext->vs.reg_name)
303 /* Gpr Registers access */
304 #define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
305 /* Program counter */
306 #define IAR_sig(context) REG_sig(srr0, context)
307 /* Machine State Register (Supervisor) */
308 #define MSR_sig(context) REG_sig(srr1, context)
309 #define CTR_sig(context) REG_sig(ctr, context)
311 #define XER_sig(context) REG_sig(xer, context)
312 /* User's integer exception register */
313 #define LR_sig(context) REG_sig(lr, context)
314 /* Condition register */
315 #define CR_sig(context) REG_sig(cr, context)
316 /* Float Registers access */
317 #define FLOAT_sig(reg_num, context) \
318 FLOATREG_sig(fpregs[reg_num], context)
319 #define FPSCR_sig(context) \
320 ((double)FLOATREG_sig(fpscr, context))
321 /* Exception Registers access */
322 /* Fault registers for coredump */
323 #define DAR_sig(context) EXCEPREG_sig(dar, context)
324 #define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
325 /* number of powerpc exception taken */
326 #define TRAP_sig(context) EXCEPREG_sig(exception, context)
327 #endif /* __APPLE__ */
329 int cpu_signal_handler(int host_signum, void *pinfo,
332 siginfo_t *info = pinfo;
333 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
334 ucontext_t *uc = puc;
336 struct ucontext *uc = puc;
345 if (DSISR_sig(uc) & 0x00800000) {
349 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
353 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
354 is_write, &uc->uc_sigmask);
357 #elif defined(__alpha__)
359 int cpu_signal_handler(int host_signum, void *pinfo,
362 siginfo_t *info = pinfo;
363 struct ucontext *uc = puc;
364 uint32_t *pc = uc->uc_mcontext.sc_pc;
368 /* XXX: need kernel patch to get write flag faster */
369 switch (insn >> 26) {
372 case 0x0f: /* stq_u */
379 case 0x2e: /* stl_c */
380 case 0x2f: /* stq_c */
384 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
385 is_write, &uc->uc_sigmask);
387 #elif defined(__sparc__)
389 int cpu_signal_handler(int host_signum, void *pinfo,
392 siginfo_t *info = pinfo;
395 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
396 uint32_t *regs = (uint32_t *)(info + 1);
397 void *sigmask = (regs + 20);
398 /* XXX: is there a standard glibc define ? */
399 unsigned long pc = regs[1];
402 struct sigcontext *sc = puc;
403 unsigned long pc = sc->sigc_regs.tpc;
404 void *sigmask = (void *)sc->sigc_mask;
405 #elif defined(__OpenBSD__)
406 struct sigcontext *uc = puc;
407 unsigned long pc = uc->sc_pc;
408 void *sigmask = (void *)(long)uc->sc_mask;
409 #elif defined(__NetBSD__)
410 ucontext_t *uc = puc;
411 unsigned long pc = _UC_MACHINE_PC(uc);
412 void *sigmask = (void *)&uc->uc_sigmask;
416 /* XXX: need kernel patch to get write flag faster */
418 insn = *(uint32_t *)pc;
419 if ((insn >> 30) == 3) {
420 switch ((insn >> 19) & 0x3f) {
422 case 0x15: /* stba */
424 case 0x16: /* stha */
428 case 0x17: /* stda */
430 case 0x1e: /* stxa */
432 case 0x34: /* stfa */
433 case 0x27: /* stdf */
434 case 0x37: /* stdfa */
435 case 0x26: /* stqf */
436 case 0x36: /* stqfa */
437 case 0x25: /* stfsr */
438 case 0x3c: /* casa */
439 case 0x3e: /* casxa */
444 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
448 #elif defined(__arm__)
450 #if defined(__NetBSD__)
451 #include <ucontext.h>
454 int cpu_signal_handler(int host_signum, void *pinfo,
457 siginfo_t *info = pinfo;
458 #if defined(__NetBSD__)
459 ucontext_t *uc = puc;
461 struct ucontext *uc = puc;
466 #if defined(__NetBSD__)
467 pc = uc->uc_mcontext.__gregs[_REG_R15];
468 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
469 pc = uc->uc_mcontext.gregs[R15];
471 pc = uc->uc_mcontext.arm_pc;
474 /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
475 * later processor; on v5 we will always report this as a read).
477 is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
478 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
483 #elif defined(__aarch64__)
485 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
487 siginfo_t *info = pinfo;
488 struct ucontext *uc = puc;
489 uintptr_t pc = uc->uc_mcontext.pc;
490 uint32_t insn = *(uint32_t *)pc;
493 /* XXX: need kernel patch to get write flag faster. */
494 is_write = ( (insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */
495 || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */
496 || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
497 || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */
498 || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */
499 || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */
500 || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */
501 /* Ingore bits 10, 11 & 21, controlling indexing. */
502 || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
503 || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */
504 /* Ignore bits 23 & 24, controlling indexing. */
505 || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
507 return handle_cpu_signal(pc, (uintptr_t)info->si_addr,
508 is_write, &uc->uc_sigmask);
511 #elif defined(__mc68000)
513 int cpu_signal_handler(int host_signum, void *pinfo,
516 siginfo_t *info = pinfo;
517 struct ucontext *uc = puc;
521 pc = uc->uc_mcontext.gregs[16];
522 /* XXX: compute is_write */
524 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
529 #elif defined(__ia64)
532 /* This ought to be in <bits/siginfo.h>... */
533 # define __ISR_VALID 1
536 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
538 siginfo_t *info = pinfo;
539 struct ucontext *uc = puc;
543 ip = uc->uc_mcontext.sc_ip;
544 switch (host_signum) {
550 if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
551 /* ISR.W (write-access) is bit 33: */
552 is_write = (info->si_isr >> 33) & 1;
559 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
561 (sigset_t *)&uc->uc_sigmask);
564 #elif defined(__s390__)
566 int cpu_signal_handler(int host_signum, void *pinfo,
569 siginfo_t *info = pinfo;
570 struct ucontext *uc = puc;
575 pc = uc->uc_mcontext.psw.addr;
577 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
578 of the normal 2 arguments. The 3rd argument contains the "int_code"
579 from the hardware which does in fact contain the is_write value.
580 The rt signal handler, as far as I can tell, does not give this value
581 at all. Not that we could get to it from here even if it were. */
582 /* ??? This is not even close to complete, since it ignores all
583 of the read-modify-write instructions. */
584 pinsn = (uint16_t *)pc;
585 switch (pinsn[0] >> 8) {
591 case 0xc4: /* RIL format insns */
592 switch (pinsn[0] & 0xf) {
594 case 0xb: /* STGRL */
595 case 0x7: /* STHRL */
599 case 0xe3: /* RXY format insns */
600 switch (pinsn[2] & 0xff) {
603 case 0x72: /* STCY */
604 case 0x70: /* STHY */
605 case 0x8e: /* STPQ */
606 case 0x3f: /* STRVH */
607 case 0x3e: /* STRV */
608 case 0x2f: /* STRVG */
613 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
614 is_write, &uc->uc_sigmask);
617 #elif defined(__mips__)
619 int cpu_signal_handler(int host_signum, void *pinfo,
622 siginfo_t *info = pinfo;
623 struct ucontext *uc = puc;
624 greg_t pc = uc->uc_mcontext.pc;
627 /* XXX: compute is_write */
629 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
630 is_write, &uc->uc_sigmask);
633 #elif defined(__hppa__)
635 int cpu_signal_handler(int host_signum, void *pinfo,
638 siginfo_t *info = pinfo;
639 struct ucontext *uc = puc;
640 unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
641 uint32_t insn = *(uint32_t *)pc;
644 /* XXX: need kernel patch to get write flag faster. */
645 switch (insn >> 26) {
649 case 0x1b: /* STWM */
653 case 0x09: /* CSTWX, FSTWX, FSTWS */
654 case 0x0b: /* CSTDX, FSTDX, FSTDS */
655 /* Distinguish from coprocessor load ... */
656 is_write = (insn >> 9) & 1;
660 switch ((insn >> 6) & 15) {
664 case 0xe: /* STWAS */
665 case 0xc: /* STBYS */
671 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
672 is_write, &uc->uc_sigmask);
677 #error host CPU specific signal handler needed