1 #include <dbi_kprobes.h>
2 #include <asm/dbi_kprobes.h>
3 #include <asm/trampoline_arm.h>
5 #include <swap_uprobes.h>
6 #include <asm/swap_uprobes.h>
7 #include <dbi_insn_slots.h>
8 #include <dbi_kprobes_deps.h>
9 #include "trampoline_thumb.h"
12 #include <dbi_kdebug.h>
13 extern struct hlist_head uprobe_insn_pages;
16 #define flush_insns(addr, size) \
17 flush_icache_range((unsigned long)(addr), \
18 (unsigned long)(addr) + (size))
20 #define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
21 #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
23 static kprobe_opcode_t get_addr_b(kprobe_opcode_t insn, kprobe_opcode_t *addr)
25 // real position less then PC by 8
26 return (kprobe_opcode_t)((long)addr + 8 + branch_displacement(insn));
29 /* is instruction Thumb2 and NOT a branch, etc... */
30 static int is_thumb2(kprobe_opcode_t insn)
32 return ((insn & 0xf800) == 0xe800 ||
33 (insn & 0xf800) == 0xf000 ||
34 (insn & 0xf800) == 0xf800);
37 static int arch_copy_trampoline_arm_uprobe(struct kprobe *p, struct task_struct *task, int atomic)
39 kprobe_opcode_t insns[UPROBES_TRAMP_LEN];
41 kprobe_opcode_t insn[MAX_INSN_SIZE];
42 struct arch_specific_insn ainsn;
45 if ((unsigned long)p->addr & 0x01) {
46 printk("Error in %s at %d: attempt to register kprobe at an unaligned address\n", __FILE__, __LINE__);
51 ainsn.insn_arm = insn;
52 if (!arch_check_insn_arm(&ainsn)) {
58 if (ARM_INSN_MATCH(DPIS, insn[0]) || ARM_INSN_MATCH(LRO, insn[0]) ||
59 ARM_INSN_MATCH(SRO, insn[0])) {
61 if ((ARM_INSN_REG_RN(insn[0]) == 15) || (ARM_INSN_REG_RM(insn[0]) == 15) ||
62 (ARM_INSN_MATCH(SRO, insn[0]) && (ARM_INSN_REG_RD(insn[0]) == 15))) {
63 DBPRINTF("Unboostable insn %lx, DPIS/LRO/SRO\n", insn[0]);
68 } else if (ARM_INSN_MATCH(DPI, insn[0]) || ARM_INSN_MATCH(LIO, insn[0]) ||
69 ARM_INSN_MATCH (SIO, insn[0])) {
71 if ((ARM_INSN_REG_RN(insn[0]) == 15) || (ARM_INSN_MATCH(SIO, insn[0]) &&
72 (ARM_INSN_REG_RD(insn[0]) == 15))) {
74 DBPRINTF("Unboostable insn %lx/%p, DPI/LIO/SIO\n", insn[0], p);
78 } else if (ARM_INSN_MATCH(DPRS, insn[0])) {
80 if ((ARM_INSN_REG_RN(insn[0]) == 15) || (ARM_INSN_REG_RM(insn[0]) == 15) ||
81 (ARM_INSN_REG_RS(insn[0]) == 15)) {
83 DBPRINTF("Unboostable insn %lx, DPRS\n", insn[0]);
87 } else if (ARM_INSN_MATCH(SM, insn[0])) {
89 if (ARM_INSN_REG_MR (insn[0], 15))
91 DBPRINTF ("Unboostable insn %lx, SM\n", insn[0]);
96 // check instructions that can write result to SP andu uses PC
97 if (pc_dep && (ARM_INSN_REG_RD (ainsn.insn_arm[0]) == 13)) {
98 printk("Error in %s at %d: instruction check failed (arm)\n", __FILE__, __LINE__);
100 // TODO: move free to later phase
101 //free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_arm, 0);
105 if (unlikely(uregs && pc_dep)) {
106 memcpy(insns, pc_dep_insn_execbuf, sizeof(insns));
107 if (prep_pc_dep_insn_execbuf(insns, insn[0], uregs) != 0) {
108 printk("Error in %s at %d: failed to prepare exec buffer for insn %lx!",
109 __FILE__, __LINE__, insn[0]);
111 // TODO: move free to later phase
112 //free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_arm, 0);
116 insns[6] = (kprobe_opcode_t) (p->addr + 2);
118 memcpy(insns, gen_insn_execbuf, sizeof(insns));
119 insns[UPROBES_TRAMP_INSN_IDX] = insn[0];
122 insns[UPROBES_TRAMP_RET_BREAK_IDX] = BREAKPOINT_INSTRUCTION;
123 insns[7] = (kprobe_opcode_t) (p->addr + 1);
126 if(ARM_INSN_MATCH(B, ainsn.insn_arm[0])) {
127 memcpy(insns, pc_dep_insn_execbuf, sizeof(insns));
128 insns[UPROBES_TRAMP_RET_BREAK_IDX] = BREAKPOINT_INSTRUCTION;
129 insns[6] = (kprobe_opcode_t)(p->addr + 2);
130 insns[7] = get_addr_b(p->opcode, p->addr);
133 DBPRINTF("arch_prepare_uprobe: to %p - %lx %lx %lx %lx %lx %lx %lx %lx %lx",
134 p->ainsn.insn_arm, insns[0], insns[1], insns[2], insns[3], insns[4],
135 insns[5], insns[6], insns[7], insns[8]);
136 if (!write_proc_vm_atomic(task, (unsigned long)p->ainsn.insn_arm, insns, sizeof(insns))) {
137 panic("failed to write memory %p!\n", p->ainsn.insn_arm);
138 // Mr_Nobody: we have to panic, really??...
139 //free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_arm, 0);
146 static int arch_check_insn_thumb(struct arch_specific_insn *ainsn)
150 // check instructions that can change PC
151 if (THUMB_INSN_MATCH(UNDEF, ainsn->insn_thumb[0]) ||
152 THUMB_INSN_MATCH(SWI, ainsn->insn_thumb[0]) ||
153 THUMB_INSN_MATCH(BREAK, ainsn->insn_thumb[0]) ||
154 THUMB2_INSN_MATCH(BL, ainsn->insn_thumb[0]) ||
155 THUMB_INSN_MATCH(B1, ainsn->insn_thumb[0]) ||
156 THUMB_INSN_MATCH(B2, ainsn->insn_thumb[0]) ||
157 THUMB_INSN_MATCH(CBZ, ainsn->insn_thumb[0]) ||
158 THUMB2_INSN_MATCH(B1, ainsn->insn_thumb[0]) ||
159 THUMB2_INSN_MATCH(B2, ainsn->insn_thumb[0]) ||
160 THUMB2_INSN_MATCH(BLX1, ainsn->insn_thumb[0]) ||
161 THUMB_INSN_MATCH(BLX2, ainsn->insn_thumb[0]) ||
162 THUMB_INSN_MATCH(BX, ainsn->insn_thumb[0]) ||
163 THUMB2_INSN_MATCH(BXJ, ainsn->insn_thumb[0]) ||
164 (THUMB2_INSN_MATCH(ADR, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
165 (THUMB2_INSN_MATCH(LDRW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
166 (THUMB2_INSN_MATCH(LDRW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
167 (THUMB2_INSN_MATCH(LDRHW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
168 (THUMB2_INSN_MATCH(LDRHW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
169 (THUMB2_INSN_MATCH(LDRWL, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
170 THUMB2_INSN_MATCH(LDMIA, ainsn->insn_thumb[0]) ||
171 THUMB2_INSN_MATCH(LDMDB, ainsn->insn_thumb[0]) ||
172 (THUMB2_INSN_MATCH(DP, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
173 (THUMB2_INSN_MATCH(RSBW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
174 (THUMB2_INSN_MATCH(RORW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
175 (THUMB2_INSN_MATCH(ROR, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
176 (THUMB2_INSN_MATCH(LSLW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
177 (THUMB2_INSN_MATCH(LSLW2, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
178 (THUMB2_INSN_MATCH(LSRW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
179 (THUMB2_INSN_MATCH(LSRW2, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
180 /* skip PC, #-imm12 -> SP, #-imm8 and Tegra-hanging instructions */
181 (THUMB2_INSN_MATCH(STRW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
182 (THUMB2_INSN_MATCH(STRBW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
183 (THUMB2_INSN_MATCH(STRHW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
184 (THUMB2_INSN_MATCH(STRW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
185 (THUMB2_INSN_MATCH(STRHW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
186 (THUMB2_INSN_MATCH(LDRW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
187 (THUMB2_INSN_MATCH(LDRBW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
188 (THUMB2_INSN_MATCH(LDRHW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
189 /* skip STRDx/LDRDx Rt, Rt2, [Rd, ...] */
190 (THUMB2_INSN_MATCH(LDRD, ainsn->insn_thumb[0]) || THUMB2_INSN_MATCH(LDRD1, ainsn->insn_thumb[0]) || THUMB2_INSN_MATCH(STRD, ainsn->insn_thumb[0])) ) {
191 DBPRINTF("Bad insn arch_check_insn_thumb: %lx\n", ainsn->insn_thumb[0]);
198 static int prep_pc_dep_insn_execbuf_thumb(kprobe_opcode_t * insns, kprobe_opcode_t insn, int uregs)
200 unsigned char mreg = 0;
201 unsigned char reg = 0;
203 if (THUMB_INSN_MATCH(APC, insn) || THUMB_INSN_MATCH(LRO3, insn)) {
204 reg = ((insn & 0xffff) & uregs) >> 8;
206 if (THUMB_INSN_MATCH(MOV3, insn)) {
207 if (((((unsigned char) insn) & 0xff) >> 3) == 15) {
208 reg = (insn & 0xffff) & uregs;
213 if (THUMB2_INSN_MATCH(ADR, insn)) {
214 reg = ((insn >> 16) & uregs) >> 8;
219 if (THUMB2_INSN_MATCH(LDRW, insn) || THUMB2_INSN_MATCH(LDRW1, insn) ||
220 THUMB2_INSN_MATCH(LDRHW, insn) || THUMB2_INSN_MATCH(LDRHW1, insn) ||
221 THUMB2_INSN_MATCH(LDRWL, insn)) {
222 reg = ((insn >> 16) & uregs) >> 12;
227 // LDRB.W PC, [PC, #immed] => PLD [PC, #immed], so Rt == PC is skipped
228 if (THUMB2_INSN_MATCH(LDRBW, insn) || THUMB2_INSN_MATCH(LDRBW1, insn) ||
229 THUMB2_INSN_MATCH(LDREX, insn)) {
230 reg = ((insn >> 16) & uregs) >> 12;
232 if (THUMB2_INSN_MATCH(DP, insn)) {
233 reg = ((insn >> 16) & uregs) >> 12;
238 if (THUMB2_INSN_MATCH(RSBW, insn)) {
239 reg = ((insn >> 12) & uregs) >> 8;
244 if (THUMB2_INSN_MATCH(RORW, insn)) {
245 reg = ((insn >> 12) & uregs) >> 8;
250 if (THUMB2_INSN_MATCH(ROR, insn) || THUMB2_INSN_MATCH(LSLW1, insn) ||
251 THUMB2_INSN_MATCH(LSLW2, insn) || THUMB2_INSN_MATCH(LSRW1, insn) ||
252 THUMB2_INSN_MATCH(LSRW2, insn)) {
253 reg = ((insn >> 12) & uregs) >> 8;
258 if (THUMB2_INSN_MATCH(TEQ1, insn) || THUMB2_INSN_MATCH(TST1, insn)) {
261 if (THUMB2_INSN_MATCH(TEQ2, insn) || THUMB2_INSN_MATCH(TST2, insn)) {
262 reg = THUMB2_INSN_REG_RM(insn);
275 if ((THUMB2_INSN_MATCH(STRW, insn) || THUMB2_INSN_MATCH(STRBW, insn) ||
276 THUMB2_INSN_MATCH(STRD, insn) || THUMB2_INSN_MATCH(STRHT, insn) ||
277 THUMB2_INSN_MATCH(STRT, insn) || THUMB2_INSN_MATCH(STRHW1, insn) ||
278 THUMB2_INSN_MATCH(STRHW, insn)) && THUMB2_INSN_REG_RT(insn) == 15) {
279 reg = THUMB2_INSN_REG_RT(insn);
282 if (reg == 6 || reg == 7) {
283 *((unsigned short*)insns + 0) = (*((unsigned short*)insns + 0) & 0x00ff) | ((1 << mreg) | (1 << (mreg + 1)));
284 *((unsigned short*)insns + 1) = (*((unsigned short*)insns + 1) & 0xf8ff) | (mreg << 8);
285 *((unsigned short*)insns + 2) = (*((unsigned short*)insns + 2) & 0xfff8) | (mreg + 1);
286 *((unsigned short*)insns + 3) = (*((unsigned short*)insns + 3) & 0xffc7) | (mreg << 3);
287 *((unsigned short*)insns + 7) = (*((unsigned short*)insns + 7) & 0xf8ff) | (mreg << 8);
288 *((unsigned short*)insns + 8) = (*((unsigned short*)insns + 8) & 0xffc7) | (mreg << 3);
289 *((unsigned short*)insns + 9) = (*((unsigned short*)insns + 9) & 0xffc7) | ((mreg + 1) << 3);
290 *((unsigned short*)insns + 10) = (*((unsigned short*)insns + 10) & 0x00ff) | (( 1 << mreg) | (1 << (mreg + 1)));
293 if (THUMB_INSN_MATCH(APC, insn)) {
294 // ADD Rd, PC, #immed_8*4 -> ADD Rd, SP, #immed_8*4
295 *((unsigned short*)insns + 4) = ((insn & 0xffff) | 0x800); // ADD Rd, SP, #immed_8*4
297 if (THUMB_INSN_MATCH(LRO3, insn)) {
298 // LDR Rd, [PC, #immed_8*4] -> LDR Rd, [SP, #immed_8*4]
299 *((unsigned short*)insns + 4) = ((insn & 0xffff) + 0x5000); // LDR Rd, [SP, #immed_8*4]
301 if (THUMB_INSN_MATCH(MOV3, insn)) {
302 // MOV Rd, PC -> MOV Rd, SP
303 *((unsigned short*)insns + 4) = ((insn & 0xffff) ^ 0x10); // MOV Rd, SP
305 if (THUMB2_INSN_MATCH(ADR, insn)) {
306 // ADDW Rd, PC, #imm -> ADDW Rd, SP, #imm
307 insns[2] = (insn & 0xfffffff0) | 0x0d; // ADDW Rd, SP, #imm
309 if (THUMB2_INSN_MATCH(LDRW, insn) || THUMB2_INSN_MATCH(LDRBW, insn) ||
310 THUMB2_INSN_MATCH(LDRHW, insn)) {
311 // LDR.W Rt, [PC, #-<imm_12>] -> LDR.W Rt, [SP, #-<imm_8>]
312 // !!!!!!!!!!!!!!!!!!!!!!!!
313 // !!! imm_12 vs. imm_8 !!!
314 // !!!!!!!!!!!!!!!!!!!!!!!!
315 insns[2] = (insn & 0xf0fffff0) | 0x0c00000d; // LDR.W Rt, [SP, #-<imm_8>]
317 if (THUMB2_INSN_MATCH(LDRW1, insn) || THUMB2_INSN_MATCH(LDRBW1, insn) ||
318 THUMB2_INSN_MATCH(LDRHW1, insn) || THUMB2_INSN_MATCH(LDRD, insn) ||
319 THUMB2_INSN_MATCH(LDRD1, insn) || THUMB2_INSN_MATCH(LDREX, insn)) {
320 // LDRx.W Rt, [PC, #+<imm_12>] -> LDRx.W Rt, [SP, #+<imm_12>] (+/-imm_8 for LDRD Rt, Rt2, [PC, #<imm_8>]
321 insns[2] = (insn & 0xfffffff0) | 0xd; // LDRx.W Rt, [SP, #+<imm_12>]
323 if (THUMB2_INSN_MATCH(MUL, insn)) {
324 insns[2] = (insn & 0xfff0ffff) | 0x000d0000; // MUL Rd, Rn, SP
326 if (THUMB2_INSN_MATCH(DP, insn)) {
327 if (THUMB2_INSN_REG_RM(insn) == 15) {
328 insns[2] = (insn & 0xfff0ffff) | 0x000d0000; // DP Rd, Rn, PC
329 } else if (THUMB2_INSN_REG_RN(insn) == 15) {
330 insns[2] = (insn & 0xfffffff0) | 0xd; // DP Rd, PC, Rm
333 if (THUMB2_INSN_MATCH(LDRWL, insn)) {
334 // LDRx.W Rt, [PC, #<imm_12>] -> LDRx.W Rt, [SP, #+<imm_12>] (+/-imm_8 for LDRD Rt, Rt2, [PC, #<imm_8>]
335 insns[2] = (insn & 0xfffffff0) | 0xd; // LDRx.W Rt, [SP, #+<imm_12>]
337 if (THUMB2_INSN_MATCH(RSBW, insn)) {
338 insns[2] = (insn & 0xfffffff0) | 0xd; // RSB{S}.W Rd, PC, #<const> -> RSB{S}.W Rd, SP, #<const>
340 if (THUMB2_INSN_MATCH(RORW, insn) || THUMB2_INSN_MATCH(LSLW1, insn) || THUMB2_INSN_MATCH(LSRW1, insn)) {
341 if ((THUMB2_INSN_REG_RM(insn) == 15) && (THUMB2_INSN_REG_RN(insn) == 15)) {
342 insns[2] = (insn & 0xfffdfffd); // ROR.W Rd, PC, PC
343 } else if (THUMB2_INSN_REG_RM(insn) == 15) {
344 insns[2] = (insn & 0xfff0ffff) | 0xd0000; // ROR.W Rd, Rn, PC
345 } else if (THUMB2_INSN_REG_RN(insn) == 15) {
346 insns[2] = (insn & 0xfffffff0) | 0xd; // ROR.W Rd, PC, Rm
349 if (THUMB2_INSN_MATCH(ROR, insn) || THUMB2_INSN_MATCH(LSLW2, insn) || THUMB2_INSN_MATCH(LSRW2, insn)) {
350 insns[2] = (insn & 0xfff0ffff) | 0xd0000; // ROR{S} Rd, PC, #<const> -> ROR{S} Rd, SP, #<const>
364 if (THUMB2_INSN_MATCH(STRW, insn) || THUMB2_INSN_MATCH(STRBW, insn)) {
365 insns[2] = (insn & 0xfff0ffff) | 0x000d0000; // STRx.W Rt, [Rn, SP]
367 if (THUMB2_INSN_MATCH(STRD, insn) || THUMB2_INSN_MATCH(STRHT, insn) ||
368 THUMB2_INSN_MATCH(STRT, insn) || THUMB2_INSN_MATCH(STRHW1, insn)) {
369 if (THUMB2_INSN_REG_RN(insn) == 15) {
370 insns[2] = (insn & 0xfffffff0) | 0xd; // STRD/T/HT{.W} Rt, [SP, ...]
375 if (THUMB2_INSN_MATCH(STRHW, insn) && (THUMB2_INSN_REG_RN(insn) == 15)) {
376 if (THUMB2_INSN_REG_RN(insn) == 15) {
377 insns[2] = (insn & 0xf0fffff0) | 0x0c00000d; // STRH.W Rt, [SP, #-<imm_8>]
386 if ((reg == 15) && (THUMB2_INSN_MATCH(STRW, insn) ||
387 THUMB2_INSN_MATCH(STRBW, insn) ||
388 THUMB2_INSN_MATCH(STRD, insn) ||
389 THUMB2_INSN_MATCH(STRHT, insn) ||
390 THUMB2_INSN_MATCH(STRT, insn) ||
391 THUMB2_INSN_MATCH(STRHW1, insn) ||
392 THUMB2_INSN_MATCH(STRHW, insn) )) {
393 insns[2] = (insns[2] & 0x0fffffff) | 0xd0000000;
396 if (THUMB2_INSN_MATCH(TEQ1, insn) || THUMB2_INSN_MATCH(TST1, insn)) {
397 insns[2] = (insn & 0xfffffff0) | 0xd; // TEQ SP, #<const>
399 if (THUMB2_INSN_MATCH(TEQ2, insn) || THUMB2_INSN_MATCH(TST2, insn)) {
400 if ((THUMB2_INSN_REG_RN(insn) == 15) && (THUMB2_INSN_REG_RM(insn) == 15)) {
401 insns[2] = (insn & 0xfffdfffd); // TEQ/TST PC, PC
402 } else if (THUMB2_INSN_REG_RM(insn) == 15) {
403 insns[2] = (insn & 0xfff0ffff) | 0xd0000; // TEQ/TST Rn, PC
404 } else if (THUMB2_INSN_REG_RN(insn) == 15) {
405 insns[2] = (insn & 0xfffffff0) | 0xd; // TEQ/TST PC, Rm
413 static int arch_copy_trampoline_thumb_uprobe(struct kprobe *p, struct task_struct *task, int atomic)
417 kprobe_opcode_t insn[MAX_INSN_SIZE];
418 struct arch_specific_insn ainsn;
419 kprobe_opcode_t insns[UPROBES_TRAMP_LEN * 2];
422 if ((unsigned long)p->addr & 0x01) {
423 printk("Error in %s at %d: attempt to register kprobe at an unaligned address\n", __FILE__, __LINE__);
428 ainsn.insn_thumb = insn;
429 if (!arch_check_insn_thumb(&ainsn)) {
436 if (THUMB_INSN_MATCH(APC, insn[0]) || THUMB_INSN_MATCH(LRO3, insn[0])) {
437 uregs = 0x0700; // 8-10
439 } else if (THUMB_INSN_MATCH(MOV3, insn[0]) && (((((unsigned char)insn[0]) & 0xff) >> 3) == 15)) {
443 } else if THUMB2_INSN_MATCH(ADR, insn[0]) {
444 uregs = 0x0f00; // Rd 8-11
446 } else if (((THUMB2_INSN_MATCH(LDRW, insn[0]) || THUMB2_INSN_MATCH(LDRW1, insn[0]) ||
447 THUMB2_INSN_MATCH(LDRBW, insn[0]) || THUMB2_INSN_MATCH(LDRBW1, insn[0]) ||
448 THUMB2_INSN_MATCH(LDRHW, insn[0]) || THUMB2_INSN_MATCH(LDRHW1, insn[0]) ||
449 THUMB2_INSN_MATCH(LDRWL, insn[0])) && THUMB2_INSN_REG_RN(insn[0]) == 15) ||
450 THUMB2_INSN_MATCH(LDREX, insn[0]) ||
451 ((THUMB2_INSN_MATCH(STRW, insn[0]) || THUMB2_INSN_MATCH(STRBW, insn[0]) ||
452 THUMB2_INSN_MATCH(STRHW, insn[0]) || THUMB2_INSN_MATCH(STRHW1, insn[0])) &&
453 (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RT(insn[0]) == 15)) ||
454 ((THUMB2_INSN_MATCH(STRT, insn[0]) || THUMB2_INSN_MATCH(STRHT, insn[0])) &&
455 (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RT(insn[0]) == 15))) {
456 uregs = 0xf000; // Rt 12-15
458 } else if ((THUMB2_INSN_MATCH(LDRD, insn[0]) || THUMB2_INSN_MATCH(LDRD1, insn[0])) && (THUMB2_INSN_REG_RN(insn[0]) == 15)) {
459 uregs = 0xff00; // Rt 12-15, Rt2 8-11
461 } else if (THUMB2_INSN_MATCH(MUL, insn[0]) && THUMB2_INSN_REG_RM(insn[0]) == 15) {
464 } else if (THUMB2_INSN_MATCH(DP, insn[0]) && (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RM(insn[0]) == 15)) {
465 uregs = 0xf000; // Rd 12-15
467 } else if (THUMB2_INSN_MATCH(STRD, insn[0]) && ((THUMB2_INSN_REG_RN(insn[0]) == 15) || (THUMB2_INSN_REG_RT(insn[0]) == 15) || THUMB2_INSN_REG_RT2(insn[0]) == 15)) {
468 uregs = 0xff00; // Rt 12-15, Rt2 8-11
470 } else if (THUMB2_INSN_MATCH(RSBW, insn[0]) && THUMB2_INSN_REG_RN(insn[0]) == 15) {
471 uregs = 0x0f00; // Rd 8-11
473 } else if (THUMB2_INSN_MATCH (RORW, insn[0]) && (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RM(insn[0]) == 15)) {
476 } else if ((THUMB2_INSN_MATCH(ROR, insn[0]) || THUMB2_INSN_MATCH(LSLW2, insn[0]) || THUMB2_INSN_MATCH(LSRW2, insn[0])) && THUMB2_INSN_REG_RM(insn[0]) == 15) {
477 uregs = 0x0f00; // Rd 8-11
479 } else if ((THUMB2_INSN_MATCH(LSLW1, insn[0]) || THUMB2_INSN_MATCH(LSRW1, insn[0])) && (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RM(insn[0]) == 15)) {
480 uregs = 0x0f00; // Rd 8-11
482 } else if ((THUMB2_INSN_MATCH(TEQ1, insn[0]) || THUMB2_INSN_MATCH(TST1, insn[0])) && THUMB2_INSN_REG_RN(insn[0]) == 15) {
483 uregs = 0xf0000; //Rn 0-3 (16-19)
485 } else if ((THUMB2_INSN_MATCH(TEQ2, insn[0]) || THUMB2_INSN_MATCH(TST2, insn[0])) &&
486 (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RM(insn[0]) == 15)) {
487 uregs = 0xf0000; //Rn 0-3 (16-19)
491 if (unlikely(uregs && pc_dep)) {
492 memcpy(insns, pc_dep_insn_execbuf_thumb, 18 * 2);
493 if (prep_pc_dep_insn_execbuf_thumb(insns, insn[0], uregs) != 0) {
494 printk("Error in %s at %d: failed to prepare exec buffer for insn %lx!",
495 __FILE__, __LINE__, insn[0]);
497 //free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_thumb, 0);
501 addr = ((unsigned int)p->addr) + 4;
502 *((unsigned short*)insns + 13) = 0xdeff;
503 *((unsigned short*)insns + 14) = addr & 0x0000ffff;
504 *((unsigned short*)insns + 15) = addr >> 16;
505 if (!is_thumb2(insn[0])) {
506 addr = ((unsigned int)p->addr) + 2;
507 *((unsigned short*)insns + 16) = (addr & 0x0000ffff) | 0x1;
508 *((unsigned short*)insns + 17) = addr >> 16;
510 addr = ((unsigned int)p->addr) + 4;
511 *((unsigned short*)insns + 16) = (addr & 0x0000ffff) | 0x1;
512 *((unsigned short*)insns + 17) = addr >> 16;
515 memcpy(insns, gen_insn_execbuf_thumb, 18 * 2);
516 *((unsigned short*)insns + 13) = 0xdeff;
517 if (!is_thumb2(insn[0])) {
518 addr = ((unsigned int)p->addr) + 2;
519 *((unsigned short*)insns + 2) = insn[0];
520 *((unsigned short*)insns + 16) = (addr & 0x0000ffff) | 0x1;
521 *((unsigned short*)insns + 17) = addr >> 16;
523 addr = ((unsigned int)p->addr) + 4;
525 *((unsigned short*)insns + 16) = (addr & 0x0000ffff) | 0x1;
526 *((unsigned short*)insns + 17) = addr >> 16;
530 if (!write_proc_vm_atomic (task, (unsigned long)p->ainsn.insn_thumb, insns, 18 * 2)) {
531 panic("failed to write memory %p!\n", p->ainsn.insn_thumb);
532 // Mr_Nobody: we have to panic, really??...
533 //free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_thumb, 0);
540 int arch_prepare_uprobe(struct uprobe *up, int atomic)
543 struct kprobe *p = &up->kp;
544 struct task_struct *task = up->task;
545 kprobe_opcode_t insn[MAX_INSN_SIZE];
547 if ((unsigned long)p->addr & 0x01) {
548 printk("Error in %s at %d: attempt to register kprobe at an unaligned address\n", __FILE__, __LINE__);
552 if (!read_proc_vm_atomic(task, (unsigned long)p->addr, &insn, MAX_INSN_SIZE * sizeof(kprobe_opcode_t))) {
553 panic("Failed to read memory task[tgid=%u, comm=%s] %p!\n", task->tgid, task->comm, p->addr);
557 p->ainsn.insn_arm = get_insn_slot(task, &uprobe_insn_pages, atomic);
558 if (!p->ainsn.insn_arm) {
559 printk("Error in %s at %d: kprobe slot allocation error (arm)\n", __FILE__, __LINE__);
563 ret = arch_copy_trampoline_arm_uprobe(p, task, 1);
565 free_insn_slot(&uprobe_insn_pages, task, p->ainsn.insn_arm);
569 p->ainsn.insn_thumb = get_insn_slot(task, &uprobe_insn_pages, atomic);
570 if (!p->ainsn.insn_thumb) {
571 printk("Error in %s at %d: kprobe slot allocation error (thumb)\n", __FILE__, __LINE__);
575 ret = arch_copy_trampoline_thumb_uprobe(p, task, 1);
577 free_insn_slot(&uprobe_insn_pages, task, p->ainsn.insn_arm);
578 free_insn_slot(&uprobe_insn_pages, task, p->ainsn.insn_thumb);
582 if ((p->safe_arm == -1) && (p->safe_thumb == -1)) {
583 printk("Error in %s at %d: failed arch_copy_trampoline_*_uprobe() (both) [tgid=%u, addr=%lx, data=%lx]\n",
584 __FILE__, __LINE__, task->tgid, (unsigned long)p->addr, (unsigned long)p->opcode);
585 if (!write_proc_vm_atomic(task, (unsigned long)p->addr, &p->opcode, sizeof(p->opcode))) {
586 panic("Failed to write memory %p!\n", p->addr);
589 free_insn_slot(&uprobe_insn_pages, task, p->ainsn.insn_arm);
590 free_insn_slot(&uprobe_insn_pages, task, p->ainsn.insn_thumb);
598 void arch_prepare_uretprobe_hl(struct uretprobe_instance *ri,
599 struct pt_regs *regs)
601 ri->ret_addr = (kprobe_opcode_t *)regs->ARM_lr;
602 ri->sp = (kprobe_opcode_t *)regs->ARM_sp;
604 /* Set flag of current mode */
605 ri->sp = (kprobe_opcode_t *)((long)ri->sp | !!thumb_mode(regs));
607 if (thumb_mode(regs)) {
608 regs->ARM_lr = (unsigned long)(ri->rp->up.kp.ainsn.insn) + 0x1b;
610 regs->ARM_lr = (unsigned long)(ri->rp->up.kp.ainsn.insn + UPROBES_TRAMP_RET_BREAK_IDX);
614 int setjmp_upre_handler(struct kprobe *p, struct pt_regs *regs)
616 struct uprobe *up = container_of(p, struct uprobe, kp);
617 struct ujprobe *jp = container_of(up, struct ujprobe, up);
619 kprobe_pre_entry_handler_t pre_entry = (kprobe_pre_entry_handler_t)jp->pre_entry;
620 entry_point_t entry = (entry_point_t)jp->entry;
623 p->ss_addr = (kprobe_opcode_t *)pre_entry(jp->priv_arg, regs);
627 entry(regs->ARM_r0, regs->ARM_r1, regs->ARM_r2,
628 regs->ARM_r3, regs->ARM_r4, regs->ARM_r5);
630 dbi_arch_uprobe_return();
636 unsigned long arch_get_trampoline_addr(struct kprobe *p, struct pt_regs *regs)
638 return thumb_mode(regs) ?
639 (unsigned long)(p->ainsn.insn) + 0x1b :
640 (unsigned long)(p->ainsn.insn + UPROBES_TRAMP_RET_BREAK_IDX);
643 void arch_set_orig_ret_addr(unsigned long orig_ret_addr, struct pt_regs *regs)
645 regs->ARM_lr = orig_ret_addr;
646 regs->ARM_pc = orig_ret_addr;
648 if (thumb_mode(regs) && !(regs->ARM_lr & 0x01)) {
649 regs->ARM_cpsr &= 0xFFFFFFDF;
650 } else if (user_mode(regs) && (regs->ARM_lr & 0x01)) {
651 regs->ARM_cpsr |= 0x20;
655 static int check_validity_insn(struct kprobe *p, struct pt_regs *regs)
659 if (unlikely(thumb_mode(regs))) {
660 if (p->safe_thumb == -1) {
664 p->ainsn.insn = p->ainsn.insn_thumb;
665 list_for_each_entry_rcu(kp, &p->list, list) {
666 kp->ainsn.insn = p->ainsn.insn_thumb;
669 if (p->safe_arm == -1) {
673 p->ainsn.insn = p->ainsn.insn_arm;
674 list_for_each_entry_rcu(kp, &p->list, list) {
675 kp->ainsn.insn = p->ainsn.insn_arm;
682 printk("Error in %s at %d: we are in arm mode (!) and check "
683 "instruction was fail (%0lX instruction at %p address)!\n",
684 __FILE__, __LINE__, p->opcode, p->addr);
686 /* Test case when we do our actions on already running application */
687 disarm_uprobe(kp2up(p));
691 static void restore_opcode_for_thumb(struct kprobe *p, struct pt_regs *regs)
693 if (thumb_mode(regs) && !is_thumb2(p->opcode)) {
694 u16 tmp = p->opcode >> 16;
695 write_proc_vm_atomic(current,
696 (unsigned long)((u16*)p->addr + 1), &tmp, 2);
697 flush_insns(p->addr, 4);
701 static int uprobe_handler(struct pt_regs *regs)
703 kprobe_opcode_t *addr = (kprobe_opcode_t *)(regs->ARM_pc);
704 struct task_struct *task = current;
705 pid_t tgid = task->tgid;
708 p = get_ukprobe(addr, tgid);
711 p = get_ukprobe_by_insn_slot(addr, tgid, regs);
713 printk("no_uprobe\n");
717 trampoline_uprobe_handler(p, regs);
718 } else if (check_validity_insn(p, regs) != 0) {
719 printk("no_uprobe live\n");
721 restore_opcode_for_thumb(p, regs);
723 if (!p->pre_handler || !p->pre_handler(p, regs)) {
724 prepare_singlestep(p, regs);
731 int uprobe_trap_handler(struct pt_regs *regs, unsigned int instr)
735 local_irq_save(flags);
738 ret = uprobe_handler(regs);
739 preempt_enable_no_resched();
741 local_irq_restore(flags);
745 /* userspace probes hook (arm) */
746 static struct undef_hook undef_hook_for_us_arm = {
747 .instr_mask = 0xffffffff,
748 .instr_val = BREAKPOINT_INSTRUCTION,
749 .cpsr_mask = MODE_MASK,
750 .cpsr_val = USR_MODE,
751 .fn = uprobe_trap_handler
754 /* userspace probes hook (thumb) */
755 static struct undef_hook undef_hook_for_us_thumb = {
756 .instr_mask = 0xffffffff,
757 .instr_val = BREAKPOINT_INSTRUCTION & 0x0000ffff,
758 .cpsr_mask = MODE_MASK,
759 .cpsr_val = USR_MODE,
760 .fn = uprobe_trap_handler
763 int swap_arch_init_uprobes(void)
765 swap_register_undef_hook(&undef_hook_for_us_arm);
766 swap_register_undef_hook(&undef_hook_for_us_thumb);
771 void swap_arch_exit_uprobes(void)
773 swap_unregister_undef_hook(&undef_hook_for_us_thumb);
774 swap_unregister_undef_hook(&undef_hook_for_us_arm);