tools/testing/selftests/kvm/riscv/get-reg-list.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Check for KVM_GET_REG_LIST regressions.
   4  *
   5  * Copyright (c) 2023 Intel Corporation
   6  *
   7  */
   8 #include <stdio.h>
   9 #include "kvm_util.h"
  10 #include "test_util.h"
  11 #include "processor.h"
  12
  13 #define REG_MASK (KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK)
  14
  15 bool filter_reg(__u64 reg)
  16 {
  17         /*
  18          * Some ISA extensions are optional and not present on all host,
  19          * but they can't be disabled through ISA_EXT registers when present.
  20          * So, to make life easy, just filtering out these kind of registers.
  21          */
  22         switch (reg & ~REG_MASK) {
  23         case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC:
  24         case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL:
  25         case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
  26         case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBB:
  27         case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA:
  28         case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBA:
  29         case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBS:
  30         case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR:
  31         case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR:
  32         case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI:
  33         case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM:
  34                 return true;
  35         default:
  36                 break;
  37         }
  38
  39         return false;
  40 }
  41
  42 bool check_reject_set(int err)
  43 {
  44         return err == EINVAL;
  45 }
  46
  47 static inline bool vcpu_has_ext(struct kvm_vcpu *vcpu, int ext)
  48 {
  49         int ret;
  50         unsigned long value;
  51
  52         ret = __vcpu_get_reg(vcpu, RISCV_ISA_EXT_REG(ext), &value);
  53         if (ret) {
  54                 printf("Failed to get ext %d", ext);
  55                 return false;
  56         }
  57
  58         return !!value;
  59 }
  60
  61 void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c)
  62 {
  63         struct vcpu_reg_sublist *s;
  64
  65         /*
  66          * Disable all extensions which were enabled by default
  67          * if they were available in the risc-v host.
  68          */
  69         for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++)
  70                 __vcpu_set_reg(vcpu, RISCV_ISA_EXT_REG(i), 0);
  71
  72         for_each_sublist(c, s) {
  73                 if (!s->feature)
  74                         continue;
  75
  76                 /* Try to enable the desired extension */
  77                 __vcpu_set_reg(vcpu, RISCV_ISA_EXT_REG(s->feature), 1);
  78
  79                 /* Double check whether the desired extension was enabled */
  80                 __TEST_REQUIRE(vcpu_has_ext(vcpu, s->feature),
  81                                "%s not available, skipping tests\n", s->name);
  82         }
  83 }
  84
  85 static const char *config_id_to_str(__u64 id)
  86 {
  87         /* reg_off is the offset into struct kvm_riscv_config */
  88         __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG);
  89
  90         switch (reg_off) {
  91         case KVM_REG_RISCV_CONFIG_REG(isa):
  92                 return "KVM_REG_RISCV_CONFIG_REG(isa)";
  93         case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
  94                 return "KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)";
  95         case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
  96                 return "KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)";
  97         case KVM_REG_RISCV_CONFIG_REG(mvendorid):
  98                 return "KVM_REG_RISCV_CONFIG_REG(mvendorid)";
  99         case KVM_REG_RISCV_CONFIG_REG(marchid):
 100                 return "KVM_REG_RISCV_CONFIG_REG(marchid)";
 101         case KVM_REG_RISCV_CONFIG_REG(mimpid):
 102                 return "KVM_REG_RISCV_CONFIG_REG(mimpid)";
 103         case KVM_REG_RISCV_CONFIG_REG(satp_mode):
 104                 return "KVM_REG_RISCV_CONFIG_REG(satp_mode)";
 105         }
 106
 107         /*
 108          * Config regs would grow regularly with new pseudo reg added, so
 109          * just show raw id to indicate a new pseudo config reg.
 110          */
 111         return strdup_printf("KVM_REG_RISCV_CONFIG_REG(%lld) /* UNKNOWN */", reg_off);
 112 }
 113
 114 static const char *core_id_to_str(const char *prefix, __u64 id)
 115 {
 116         /* reg_off is the offset into struct kvm_riscv_core */
 117         __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CORE);
 118
 119         switch (reg_off) {
 120         case KVM_REG_RISCV_CORE_REG(regs.pc):
 121                 return "KVM_REG_RISCV_CORE_REG(regs.pc)";
 122         case KVM_REG_RISCV_CORE_REG(regs.ra):
 123                 return "KVM_REG_RISCV_CORE_REG(regs.ra)";
 124         case KVM_REG_RISCV_CORE_REG(regs.sp):
 125                 return "KVM_REG_RISCV_CORE_REG(regs.sp)";
 126         case KVM_REG_RISCV_CORE_REG(regs.gp):
 127                 return "KVM_REG_RISCV_CORE_REG(regs.gp)";
 128         case KVM_REG_RISCV_CORE_REG(regs.tp):
 129                 return "KVM_REG_RISCV_CORE_REG(regs.tp)";
 130         case KVM_REG_RISCV_CORE_REG(regs.t0) ... KVM_REG_RISCV_CORE_REG(regs.t2):
 131                 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.t%lld)",
 132                            reg_off - KVM_REG_RISCV_CORE_REG(regs.t0));
 133         case KVM_REG_RISCV_CORE_REG(regs.s0) ... KVM_REG_RISCV_CORE_REG(regs.s1):
 134                 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.s%lld)",
 135                            reg_off - KVM_REG_RISCV_CORE_REG(regs.s0));
 136         case KVM_REG_RISCV_CORE_REG(regs.a0) ... KVM_REG_RISCV_CORE_REG(regs.a7):
 137                 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.a%lld)",
 138                            reg_off - KVM_REG_RISCV_CORE_REG(regs.a0));
 139         case KVM_REG_RISCV_CORE_REG(regs.s2) ... KVM_REG_RISCV_CORE_REG(regs.s11):
 140                 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.s%lld)",
 141                            reg_off - KVM_REG_RISCV_CORE_REG(regs.s2) + 2);
 142         case KVM_REG_RISCV_CORE_REG(regs.t3) ... KVM_REG_RISCV_CORE_REG(regs.t6):
 143                 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.t%lld)",
 144                            reg_off - KVM_REG_RISCV_CORE_REG(regs.t3) + 3);
 145         case KVM_REG_RISCV_CORE_REG(mode):
 146                 return "KVM_REG_RISCV_CORE_REG(mode)";
 147         }
 148
 149         TEST_FAIL("%s: Unknown core reg id: 0x%llx", prefix, id);
 150         return NULL;
 151 }
 152
 153 #define RISCV_CSR_GENERAL(csr) \
 154         "KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")"
 155 #define RISCV_CSR_AIA(csr) \
 156         "KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")"
 157
 158 static const char *general_csr_id_to_str(__u64 reg_off)
 159 {
 160         /* reg_off is the offset into struct kvm_riscv_csr */
 161         switch (reg_off) {
 162         case KVM_REG_RISCV_CSR_REG(sstatus):
 163                 return RISCV_CSR_GENERAL(sstatus);
 164         case KVM_REG_RISCV_CSR_REG(sie):
 165                 return RISCV_CSR_GENERAL(sie);
 166         case KVM_REG_RISCV_CSR_REG(stvec):
 167                 return RISCV_CSR_GENERAL(stvec);
 168         case KVM_REG_RISCV_CSR_REG(sscratch):
 169                 return RISCV_CSR_GENERAL(sscratch);
 170         case KVM_REG_RISCV_CSR_REG(sepc):
 171                 return RISCV_CSR_GENERAL(sepc);
 172         case KVM_REG_RISCV_CSR_REG(scause):
 173                 return RISCV_CSR_GENERAL(scause);
 174         case KVM_REG_RISCV_CSR_REG(stval):
 175                 return RISCV_CSR_GENERAL(stval);
 176         case KVM_REG_RISCV_CSR_REG(sip):
 177                 return RISCV_CSR_GENERAL(sip);
 178         case KVM_REG_RISCV_CSR_REG(satp):
 179                 return RISCV_CSR_GENERAL(satp);
 180         case KVM_REG_RISCV_CSR_REG(scounteren):
 181                 return RISCV_CSR_GENERAL(scounteren);
 182         }
 183
 184         TEST_FAIL("Unknown general csr reg: 0x%llx", reg_off);
 185         return NULL;
 186 }
 187
 188 static const char *aia_csr_id_to_str(__u64 reg_off)
 189 {
 190         /* reg_off is the offset into struct kvm_riscv_aia_csr */
 191         switch (reg_off) {
 192         case KVM_REG_RISCV_CSR_AIA_REG(siselect):
 193                 return RISCV_CSR_AIA(siselect);
 194         case KVM_REG_RISCV_CSR_AIA_REG(iprio1):
 195                 return RISCV_CSR_AIA(iprio1);
 196         case KVM_REG_RISCV_CSR_AIA_REG(iprio2):
 197                 return RISCV_CSR_AIA(iprio2);
 198         case KVM_REG_RISCV_CSR_AIA_REG(sieh):
 199                 return RISCV_CSR_AIA(sieh);
 200         case KVM_REG_RISCV_CSR_AIA_REG(siph):
 201                 return RISCV_CSR_AIA(siph);
 202         case KVM_REG_RISCV_CSR_AIA_REG(iprio1h):
 203                 return RISCV_CSR_AIA(iprio1h);
 204         case KVM_REG_RISCV_CSR_AIA_REG(iprio2h):
 205                 return RISCV_CSR_AIA(iprio2h);
 206         }
 207
 208         TEST_FAIL("Unknown aia csr reg: 0x%llx", reg_off);
 209         return NULL;
 210 }
 211
 212 static const char *csr_id_to_str(const char *prefix, __u64 id)
 213 {
 214         __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR);
 215         __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;
 216
 217         reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;
 218
 219         switch (reg_subtype) {
 220         case KVM_REG_RISCV_CSR_GENERAL:
 221                 return general_csr_id_to_str(reg_off);
 222         case KVM_REG_RISCV_CSR_AIA:
 223                 return aia_csr_id_to_str(reg_off);
 224         }
 225
 226         TEST_FAIL("%s: Unknown csr subtype: 0x%llx", prefix, reg_subtype);
 227         return NULL;
 228 }
 229
 230 static const char *timer_id_to_str(const char *prefix, __u64 id)
 231 {
 232         /* reg_off is the offset into struct kvm_riscv_timer */
 233         __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_TIMER);
 234
 235         switch (reg_off) {
 236         case KVM_REG_RISCV_TIMER_REG(frequency):
 237                 return "KVM_REG_RISCV_TIMER_REG(frequency)";
 238         case KVM_REG_RISCV_TIMER_REG(time):
 239                 return "KVM_REG_RISCV_TIMER_REG(time)";
 240         case KVM_REG_RISCV_TIMER_REG(compare):
 241                 return "KVM_REG_RISCV_TIMER_REG(compare)";
 242         case KVM_REG_RISCV_TIMER_REG(state):
 243                 return "KVM_REG_RISCV_TIMER_REG(state)";
 244         }
 245
 246         TEST_FAIL("%s: Unknown timer reg id: 0x%llx", prefix, id);
 247         return NULL;
 248 }
 249
 250 static const char *fp_f_id_to_str(const char *prefix, __u64 id)
 251 {
 252         /* reg_off is the offset into struct __riscv_f_ext_state */
 253         __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_F);
 254
 255         switch (reg_off) {
 256         case KVM_REG_RISCV_FP_F_REG(f[0]) ...
 257              KVM_REG_RISCV_FP_F_REG(f[31]):
 258                 return strdup_printf("KVM_REG_RISCV_FP_F_REG(f[%lld])", reg_off);
 259         case KVM_REG_RISCV_FP_F_REG(fcsr):
 260                 return "KVM_REG_RISCV_FP_F_REG(fcsr)";
 261         }
 262
 263         TEST_FAIL("%s: Unknown fp_f reg id: 0x%llx", prefix, id);
 264         return NULL;
 265 }
 266
 267 static const char *fp_d_id_to_str(const char *prefix, __u64 id)
 268 {
 269         /* reg_off is the offset into struct __riscv_d_ext_state */
 270         __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_D);
 271
 272         switch (reg_off) {
 273         case KVM_REG_RISCV_FP_D_REG(f[0]) ...
 274              KVM_REG_RISCV_FP_D_REG(f[31]):
 275                 return strdup_printf("KVM_REG_RISCV_FP_D_REG(f[%lld])", reg_off);
 276         case KVM_REG_RISCV_FP_D_REG(fcsr):
 277                 return "KVM_REG_RISCV_FP_D_REG(fcsr)";
 278         }
 279
 280         TEST_FAIL("%s: Unknown fp_d reg id: 0x%llx", prefix, id);
 281         return NULL;
 282 }
 283
 284 static const char *isa_ext_id_to_str(__u64 id)
 285 {
 286         /* reg_off is the offset into unsigned long kvm_isa_ext_arr[] */
 287         __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT);
 288
 289         static const char * const kvm_isa_ext_reg_name[] = {
 290                 "KVM_RISCV_ISA_EXT_A",
 291                 "KVM_RISCV_ISA_EXT_C",
 292                 "KVM_RISCV_ISA_EXT_D",
 293                 "KVM_RISCV_ISA_EXT_F",
 294                 "KVM_RISCV_ISA_EXT_H",
 295                 "KVM_RISCV_ISA_EXT_I",
 296                 "KVM_RISCV_ISA_EXT_M",
 297                 "KVM_RISCV_ISA_EXT_SVPBMT",
 298                 "KVM_RISCV_ISA_EXT_SSTC",
 299                 "KVM_RISCV_ISA_EXT_SVINVAL",
 300                 "KVM_RISCV_ISA_EXT_ZIHINTPAUSE",
 301                 "KVM_RISCV_ISA_EXT_ZICBOM",
 302                 "KVM_RISCV_ISA_EXT_ZICBOZ",
 303                 "KVM_RISCV_ISA_EXT_ZBB",
 304                 "KVM_RISCV_ISA_EXT_SSAIA",
 305                 "KVM_RISCV_ISA_EXT_V",
 306                 "KVM_RISCV_ISA_EXT_SVNAPOT",
 307                 "KVM_RISCV_ISA_EXT_ZBA",
 308                 "KVM_RISCV_ISA_EXT_ZBS",
 309                 "KVM_RISCV_ISA_EXT_ZICNTR",
 310                 "KVM_RISCV_ISA_EXT_ZICSR",
 311                 "KVM_RISCV_ISA_EXT_ZIFENCEI",
 312                 "KVM_RISCV_ISA_EXT_ZIHPM",
 313         };
 314
 315         if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) {
 316                 /*
 317                  * isa_ext regs would grow regularly with new isa extension added, so
 318                  * just show "reg" to indicate a new extension.
 319                  */
 320                 return strdup_printf("%lld /* UNKNOWN */", reg_off);
 321         }
 322
 323         return kvm_isa_ext_reg_name[reg_off];
 324 }
 325
 326 static const char *sbi_ext_single_id_to_str(__u64 reg_off)
 327 {
 328         /* reg_off is KVM_RISCV_SBI_EXT_ID */
 329         static const char * const kvm_sbi_ext_reg_name[] = {
 330                 "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01",
 331                 "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME",
 332                 "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI",
 333                 "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE",
 334                 "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST",
 335                 "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM",
 336                 "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_PMU",
 337                 "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL",
 338                 "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR",
 339         };
 340
 341         if (reg_off >= ARRAY_SIZE(kvm_sbi_ext_reg_name)) {
 342                 /*
 343                  * sbi_ext regs would grow regularly with new sbi extension added, so
 344                  * just show "reg" to indicate a new extension.
 345                  */
 346                 return strdup_printf("KVM_REG_RISCV_SBI_SINGLE | %lld /* UNKNOWN */", reg_off);
 347         }
 348
 349         return kvm_sbi_ext_reg_name[reg_off];
 350 }
 351
 352 static const char *sbi_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off)
 353 {
 354         if (reg_off > KVM_REG_RISCV_SBI_MULTI_REG_LAST) {
 355                 /*
 356                  * sbi_ext regs would grow regularly with new sbi extension added, so
 357                  * just show "reg" to indicate a new extension.
 358                  */
 359                 return strdup_printf("%lld /* UNKNOWN */", reg_off);
 360         }
 361
 362         switch (reg_subtype) {
 363         case KVM_REG_RISCV_SBI_MULTI_EN:
 364                 return strdup_printf("KVM_REG_RISCV_SBI_MULTI_EN | %lld", reg_off);
 365         case KVM_REG_RISCV_SBI_MULTI_DIS:
 366                 return strdup_printf("KVM_REG_RISCV_SBI_MULTI_DIS | %lld", reg_off);
 367         }
 368
 369         return NULL;
 370 }
 371
 372 static const char *sbi_ext_id_to_str(const char *prefix, __u64 id)
 373 {
 374         __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_EXT);
 375         __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;
 376
 377         reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;
 378
 379         switch (reg_subtype) {
 380         case KVM_REG_RISCV_SBI_SINGLE:
 381                 return sbi_ext_single_id_to_str(reg_off);
 382         case KVM_REG_RISCV_SBI_MULTI_EN:
 383         case KVM_REG_RISCV_SBI_MULTI_DIS:
 384                 return sbi_ext_multi_id_to_str(reg_subtype, reg_off);
 385         }
 386
 387         TEST_FAIL("%s: Unknown sbi ext subtype: 0x%llx", prefix, reg_subtype);
 388         return NULL;
 389 }
 390
 391 void print_reg(const char *prefix, __u64 id)
 392 {
 393         const char *reg_size = NULL;
 394
 395         TEST_ASSERT((id & KVM_REG_ARCH_MASK) == KVM_REG_RISCV,
 396                     "%s: KVM_REG_RISCV missing in reg id: 0x%llx", prefix, id);
 397
 398         switch (id & KVM_REG_SIZE_MASK) {
 399         case KVM_REG_SIZE_U32:
 400                 reg_size = "KVM_REG_SIZE_U32";
 401                 break;
 402         case KVM_REG_SIZE_U64:
 403                 reg_size = "KVM_REG_SIZE_U64";
 404                 break;
 405         case KVM_REG_SIZE_U128:
 406                 reg_size = "KVM_REG_SIZE_U128";
 407                 break;
 408         default:
 409                 TEST_FAIL("%s: Unexpected reg size: 0x%llx in reg id: 0x%llx",
 410                           prefix, (id & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT, id);
 411         }
 412
 413         switch (id & KVM_REG_RISCV_TYPE_MASK) {
 414         case KVM_REG_RISCV_CONFIG:
 415                 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CONFIG | %s,\n",
 416                                 reg_size, config_id_to_str(id));
 417                 break;
 418         case KVM_REG_RISCV_CORE:
 419                 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CORE | %s,\n",
 420                                 reg_size, core_id_to_str(prefix, id));
 421                 break;
 422         case KVM_REG_RISCV_CSR:
 423                 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CSR | %s,\n",
 424                                 reg_size, csr_id_to_str(prefix, id));
 425                 break;
 426         case KVM_REG_RISCV_TIMER:
 427                 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_TIMER | %s,\n",
 428                                 reg_size, timer_id_to_str(prefix, id));
 429                 break;
 430         case KVM_REG_RISCV_FP_F:
 431                 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_FP_F | %s,\n",
 432                                 reg_size, fp_f_id_to_str(prefix, id));
 433                 break;
 434         case KVM_REG_RISCV_FP_D:
 435                 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_FP_D | %s,\n",
 436                                 reg_size, fp_d_id_to_str(prefix, id));
 437                 break;
 438         case KVM_REG_RISCV_ISA_EXT:
 439                 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_ISA_EXT | %s,\n",
 440                                 reg_size, isa_ext_id_to_str(id));
 441                 break;
 442         case KVM_REG_RISCV_SBI_EXT:
 443                 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_SBI_EXT | %s,\n",
 444                                 reg_size, sbi_ext_id_to_str(prefix, id));
 445                 break;
 446         default:
 447                 TEST_FAIL("%s: Unexpected reg type: 0x%llx in reg id: 0x%llx", prefix,
 448                                 (id & KVM_REG_RISCV_TYPE_MASK) >> KVM_REG_RISCV_TYPE_SHIFT, id);
 449         }
 450 }
 451
 452 /*
 453  * The current blessed list was primed with the output of kernel version
 454  * v6.5-rc3 and then later updated with new registers.
 455  */
 456 static __u64 base_regs[] = {
 457         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(isa),
 458         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mvendorid),
 459         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(marchid),
 460         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mimpid),
 461         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(satp_mode),
 462         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.pc),
 463         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.ra),
 464         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.sp),
 465         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.gp),
 466         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.tp),
 467         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t0),
 468         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t1),
 469         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t2),
 470         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s0),
 471         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s1),
 472         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a0),
 473         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a1),
 474         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a2),
 475         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a3),
 476         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a4),
 477         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a5),
 478         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a6),
 479         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a7),
 480         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s2),
 481         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s3),
 482         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s4),
 483         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s5),
 484         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s6),
 485         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s7),
 486         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s8),
 487         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s9),
 488         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s10),
 489         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s11),
 490         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t3),
 491         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t4),
 492         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t5),
 493         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t6),
 494         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(mode),
 495         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sstatus),
 496         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sie),
 497         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(stvec),
 498         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sscratch),
 499         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sepc),
 500         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scause),
 501         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(stval),
 502         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sip),
 503         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(satp),
 504         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scounteren),
 505         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(frequency),
 506         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(time),
 507         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare),
 508         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state),
 509         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_A,
 510         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_C,
 511         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I,
 512         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M,
 513         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01,
 514         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME,
 515         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI,
 516         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE,
 517         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST,
 518         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM,
 519         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_PMU,
 520         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL,
 521         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR,
 522         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_MULTI_EN | 0,
 523         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_MULTI_DIS | 0,
 524 };
 525
 526 /*
 527  * The skips_set list registers that should skip set test.
 528  *  - KVM_REG_RISCV_TIMER_REG(state): set would fail if it was not initialized properly.
 529  */
 530 static __u64 base_skips_set[] = {
 531         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state),
 532 };
 533
 534 static __u64 h_regs[] = {
 535         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_H,
 536 };
 537
 538 static __u64 zicbom_regs[] = {
 539         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size),
 540         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM,
 541 };
 542
 543 static __u64 zicboz_regs[] = {
 544         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size),
 545         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ,
 546 };
 547
 548 static __u64 svpbmt_regs[] = {
 549         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVPBMT,
 550 };
 551
 552 static __u64 sstc_regs[] = {
 553         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC,
 554 };
 555
 556 static __u64 svinval_regs[] = {
 557         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL,
 558 };
 559
 560 static __u64 zihintpause_regs[] = {
 561         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
 562 };
 563
 564 static __u64 zba_regs[] = {
 565         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBA,
 566 };
 567
 568 static __u64 zbb_regs[] = {
 569         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBB,
 570 };
 571
 572 static __u64 zbs_regs[] = {
 573         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBS,
 574 };
 575
 576 static __u64 zicntr_regs[] = {
 577         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR,
 578 };
 579
 580 static __u64 zicsr_regs[] = {
 581         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR,
 582 };
 583
 584 static __u64 zifencei_regs[] = {
 585         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI,
 586 };
 587
 588 static __u64 zihpm_regs[] = {
 589         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM,
 590 };
 591
 592 static __u64 aia_regs[] = {
 593         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect),
 594         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1),
 595         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2),
 596         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh),
 597         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph),
 598         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h),
 599         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h),
 600         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA,
 601 };
 602
 603 static __u64 fp_f_regs[] = {
 604         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[0]),
 605         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[1]),
 606         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[2]),
 607         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[3]),
 608         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[4]),
 609         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[5]),
 610         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[6]),
 611         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[7]),
 612         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[8]),
 613         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[9]),
 614         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[10]),
 615         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[11]),
 616         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[12]),
 617         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[13]),
 618         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[14]),
 619         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[15]),
 620         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[16]),
 621         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[17]),
 622         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[18]),
 623         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[19]),
 624         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[20]),
 625         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[21]),
 626         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[22]),
 627         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[23]),
 628         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[24]),
 629         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[25]),
 630         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[26]),
 631         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[27]),
 632         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[28]),
 633         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[29]),
 634         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[30]),
 635         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[31]),
 636         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(fcsr),
 637         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_F,
 638 };
 639
 640 static __u64 fp_d_regs[] = {
 641         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[0]),
 642         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[1]),
 643         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[2]),
 644         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[3]),
 645         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[4]),
 646         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[5]),
 647         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[6]),
 648         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[7]),
 649         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[8]),
 650         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[9]),
 651         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[10]),
 652         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[11]),
 653         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[12]),
 654         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[13]),
 655         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[14]),
 656         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[15]),
 657         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[16]),
 658         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[17]),
 659         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[18]),
 660         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[19]),
 661         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[20]),
 662         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[21]),
 663         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[22]),
 664         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[23]),
 665         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[24]),
 666         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[25]),
 667         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[26]),
 668         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[27]),
 669         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[28]),
 670         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[29]),
 671         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[30]),
 672         KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[31]),
 673         KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(fcsr),
 674         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_D,
 675 };
 676
 677 #define BASE_SUBLIST \
 678         {"base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), \
 679          .skips_set = base_skips_set, .skips_set_n = ARRAY_SIZE(base_skips_set),}
 680 #define H_REGS_SUBLIST \
 681         {"h", .feature = KVM_RISCV_ISA_EXT_H, .regs = h_regs, .regs_n = ARRAY_SIZE(h_regs),}
 682 #define ZICBOM_REGS_SUBLIST \
 683         {"zicbom", .feature = KVM_RISCV_ISA_EXT_ZICBOM, .regs = zicbom_regs, .regs_n = ARRAY_SIZE(zicbom_regs),}
 684 #define ZICBOZ_REGS_SUBLIST \
 685         {"zicboz", .feature = KVM_RISCV_ISA_EXT_ZICBOZ, .regs = zicboz_regs, .regs_n = ARRAY_SIZE(zicboz_regs),}
 686 #define SVPBMT_REGS_SUBLIST \
 687         {"svpbmt", .feature = KVM_RISCV_ISA_EXT_SVPBMT, .regs = svpbmt_regs, .regs_n = ARRAY_SIZE(svpbmt_regs),}
 688 #define SSTC_REGS_SUBLIST \
 689         {"sstc", .feature = KVM_RISCV_ISA_EXT_SSTC, .regs = sstc_regs, .regs_n = ARRAY_SIZE(sstc_regs),}
 690 #define SVINVAL_REGS_SUBLIST \
 691         {"svinval", .feature = KVM_RISCV_ISA_EXT_SVINVAL, .regs = svinval_regs, .regs_n = ARRAY_SIZE(svinval_regs),}
 692 #define ZIHINTPAUSE_REGS_SUBLIST \
 693         {"zihintpause", .feature = KVM_RISCV_ISA_EXT_ZIHINTPAUSE, .regs = zihintpause_regs, .regs_n = ARRAY_SIZE(zihintpause_regs),}
 694 #define ZBA_REGS_SUBLIST \
 695         {"zba", .feature = KVM_RISCV_ISA_EXT_ZBA, .regs = zba_regs, .regs_n = ARRAY_SIZE(zba_regs),}
 696 #define ZBB_REGS_SUBLIST \
 697         {"zbb", .feature = KVM_RISCV_ISA_EXT_ZBB, .regs = zbb_regs, .regs_n = ARRAY_SIZE(zbb_regs),}
 698 #define ZBS_REGS_SUBLIST \
 699         {"zbs", .feature = KVM_RISCV_ISA_EXT_ZBS, .regs = zbs_regs, .regs_n = ARRAY_SIZE(zbs_regs),}
 700 #define ZICNTR_REGS_SUBLIST \
 701         {"zicntr", .feature = KVM_RISCV_ISA_EXT_ZICNTR, .regs = zicntr_regs, .regs_n = ARRAY_SIZE(zicntr_regs),}
 702 #define ZICSR_REGS_SUBLIST \
 703         {"zicsr", .feature = KVM_RISCV_ISA_EXT_ZICSR, .regs = zicsr_regs, .regs_n = ARRAY_SIZE(zicsr_regs),}
 704 #define ZIFENCEI_REGS_SUBLIST \
 705         {"zifencei", .feature = KVM_RISCV_ISA_EXT_ZIFENCEI, .regs = zifencei_regs, .regs_n = ARRAY_SIZE(zifencei_regs),}
 706 #define ZIHPM_REGS_SUBLIST \
 707         {"zihpm", .feature = KVM_RISCV_ISA_EXT_ZIHPM, .regs = zihpm_regs, .regs_n = ARRAY_SIZE(zihpm_regs),}
 708 #define AIA_REGS_SUBLIST \
 709         {"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),}
 710 #define FP_F_REGS_SUBLIST \
 711         {"fp_f", .feature = KVM_RISCV_ISA_EXT_F, .regs = fp_f_regs, \
 712                 .regs_n = ARRAY_SIZE(fp_f_regs),}
 713 #define FP_D_REGS_SUBLIST \
 714         {"fp_d", .feature = KVM_RISCV_ISA_EXT_D, .regs = fp_d_regs, \
 715                 .regs_n = ARRAY_SIZE(fp_d_regs),}
 716
 717 static struct vcpu_reg_list h_config = {
 718         .sublists = {
 719         BASE_SUBLIST,
 720         H_REGS_SUBLIST,
 721         {0},
 722         },
 723 };
 724
 725 static struct vcpu_reg_list zicbom_config = {
 726         .sublists = {
 727         BASE_SUBLIST,
 728         ZICBOM_REGS_SUBLIST,
 729         {0},
 730         },
 731 };
 732
 733 static struct vcpu_reg_list zicboz_config = {
 734         .sublists = {
 735         BASE_SUBLIST,
 736         ZICBOZ_REGS_SUBLIST,
 737         {0},
 738         },
 739 };
 740
 741 static struct vcpu_reg_list svpbmt_config = {
 742         .sublists = {
 743         BASE_SUBLIST,
 744         SVPBMT_REGS_SUBLIST,
 745         {0},
 746         },
 747 };
 748
 749 static struct vcpu_reg_list sstc_config = {
 750         .sublists = {
 751         BASE_SUBLIST,
 752         SSTC_REGS_SUBLIST,
 753         {0},
 754         },
 755 };
 756
 757 static struct vcpu_reg_list svinval_config = {
 758         .sublists = {
 759         BASE_SUBLIST,
 760         SVINVAL_REGS_SUBLIST,
 761         {0},
 762         },
 763 };
 764
 765 static struct vcpu_reg_list zihintpause_config = {
 766         .sublists = {
 767         BASE_SUBLIST,
 768         ZIHINTPAUSE_REGS_SUBLIST,
 769         {0},
 770         },
 771 };
 772
 773 static struct vcpu_reg_list zba_config = {
 774         .sublists = {
 775         BASE_SUBLIST,
 776         ZBA_REGS_SUBLIST,
 777         {0},
 778         },
 779 };
 780
 781 static struct vcpu_reg_list zbb_config = {
 782         .sublists = {
 783         BASE_SUBLIST,
 784         ZBB_REGS_SUBLIST,
 785         {0},
 786         },
 787 };
 788
 789 static struct vcpu_reg_list zbs_config = {
 790         .sublists = {
 791         BASE_SUBLIST,
 792         ZBS_REGS_SUBLIST,
 793         {0},
 794         },
 795 };
 796
 797 static struct vcpu_reg_list zicntr_config = {
 798         .sublists = {
 799         BASE_SUBLIST,
 800         ZICNTR_REGS_SUBLIST,
 801         {0},
 802         },
 803 };
 804
 805 static struct vcpu_reg_list zicsr_config = {
 806         .sublists = {
 807         BASE_SUBLIST,
 808         ZICSR_REGS_SUBLIST,
 809         {0},
 810         },
 811 };
 812
 813 static struct vcpu_reg_list zifencei_config = {
 814         .sublists = {
 815         BASE_SUBLIST,
 816         ZIFENCEI_REGS_SUBLIST,
 817         {0},
 818         },
 819 };
 820
 821 static struct vcpu_reg_list zihpm_config = {
 822         .sublists = {
 823         BASE_SUBLIST,
 824         ZIHPM_REGS_SUBLIST,
 825         {0},
 826         },
 827 };
 828
 829 static struct vcpu_reg_list aia_config = {
 830         .sublists = {
 831         BASE_SUBLIST,
 832         AIA_REGS_SUBLIST,
 833         {0},
 834         },
 835 };
 836
 837 static struct vcpu_reg_list fp_f_config = {
 838         .sublists = {
 839         BASE_SUBLIST,
 840         FP_F_REGS_SUBLIST,
 841         {0},
 842         },
 843 };
 844
 845 static struct vcpu_reg_list fp_d_config = {
 846         .sublists = {
 847         BASE_SUBLIST,
 848         FP_D_REGS_SUBLIST,
 849         {0},
 850         },
 851 };
 852
 853 struct vcpu_reg_list *vcpu_configs[] = {
 854         &h_config,
 855         &zicbom_config,
 856         &zicboz_config,
 857         &svpbmt_config,
 858         &sstc_config,
 859         &svinval_config,
 860         &zihintpause_config,
 861         &zba_config,
 862         &zbb_config,
 863         &zbs_config,
 864         &zicntr_config,
 865         &zicsr_config,
 866         &zifencei_config,
 867         &zihpm_config,
 868         &aia_config,
 869         &fp_f_config,
 870         &fp_d_config,
 871 };
 872 int vcpu_configs_n = ARRAY_SIZE(vcpu_configs);