1 /* SPDX-License-Identifier: GPL-2.0 */
3 * tools/testing/selftests/kvm/include/x86_64/svm.h
4 * This is a copy of arch/x86/include/asm/svm.h
8 #ifndef SELFTEST_KVM_SVM_H
9 #define SELFTEST_KVM_SVM_H
17 INTERCEPT_SELECTIVE_CR0,
41 INTERCEPT_TASK_SWITCH,
42 INTERCEPT_FERR_FREEZE,
61 struct hv_enlightenments {
62 struct __packed hv_enlightenments_control {
63 u32 nested_flush_hypercall:1;
65 u32 enlightened_npt_tlb: 1;
67 } __packed hv_enlightenments_control;
70 u64 partition_assist_page;
75 * Hyper-V uses the software reserved clean bit in VMCB
77 #define HV_VMCB_NESTED_ENLIGHTENMENTS (1U << 31)
79 struct __attribute__ ((__packed__)) vmcb_control_area {
82 u32 intercept_exceptions;
85 u16 pause_filter_thresh;
86 u16 pause_filter_count;
102 u32 exit_int_info_err;
115 u64 avic_backing_page; /* Offset 0xe0 */
116 u8 reserved_6[8]; /* Offset 0xe8 */
117 u64 avic_logical_id; /* Offset 0xf0 */
118 u64 avic_physical_id; /* Offset 0xf8 */
120 u64 vmsa_pa; /* Used for an SEV-ES guest */
123 * Offset 0x3e0, 32 bytes reserved
124 * for use by hypervisor/software.
127 struct hv_enlightenments hv_enlightenments;
133 #define TLB_CONTROL_DO_NOTHING 0
134 #define TLB_CONTROL_FLUSH_ALL_ASID 1
135 #define TLB_CONTROL_FLUSH_ASID 3
136 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
138 #define V_TPR_MASK 0x0f
140 #define V_IRQ_SHIFT 8
141 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
143 #define V_GIF_SHIFT 9
144 #define V_GIF_MASK (1 << V_GIF_SHIFT)
146 #define V_INTR_PRIO_SHIFT 16
147 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
149 #define V_IGN_TPR_SHIFT 20
150 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
152 #define V_INTR_MASKING_SHIFT 24
153 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
155 #define V_GIF_ENABLE_SHIFT 25
156 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
158 #define AVIC_ENABLE_SHIFT 31
159 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
161 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
162 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
164 #define SVM_INTERRUPT_SHADOW_MASK 1
166 #define SVM_IOIO_STR_SHIFT 2
167 #define SVM_IOIO_REP_SHIFT 3
168 #define SVM_IOIO_SIZE_SHIFT 4
169 #define SVM_IOIO_ASIZE_SHIFT 7
171 #define SVM_IOIO_TYPE_MASK 1
172 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
173 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
174 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
175 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
177 #define SVM_VM_CR_VALID_MASK 0x001fULL
178 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
179 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
181 #define SVM_NESTED_CTL_NP_ENABLE BIT(0)
182 #define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
184 struct __attribute__ ((__packed__)) vmcb_seg {
191 struct __attribute__ ((__packed__)) vmcb_save_area {
198 struct vmcb_seg gdtr;
199 struct vmcb_seg ldtr;
200 struct vmcb_seg idtr;
236 struct __attribute__ ((__packed__)) vmcb {
237 struct vmcb_control_area control;
238 struct vmcb_save_area save;
241 #define SVM_VM_CR_SVM_DISABLE 4
243 #define SVM_SELECTOR_S_SHIFT 4
244 #define SVM_SELECTOR_DPL_SHIFT 5
245 #define SVM_SELECTOR_P_SHIFT 7
246 #define SVM_SELECTOR_AVL_SHIFT 8
247 #define SVM_SELECTOR_L_SHIFT 9
248 #define SVM_SELECTOR_DB_SHIFT 10
249 #define SVM_SELECTOR_G_SHIFT 11
251 #define SVM_SELECTOR_TYPE_MASK (0xf)
252 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
253 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
254 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
255 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
256 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
257 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
258 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
260 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
261 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
262 #define SVM_SELECTOR_CODE_MASK (1 << 3)
264 #define INTERCEPT_CR0_READ 0
265 #define INTERCEPT_CR3_READ 3
266 #define INTERCEPT_CR4_READ 4
267 #define INTERCEPT_CR8_READ 8
268 #define INTERCEPT_CR0_WRITE (16 + 0)
269 #define INTERCEPT_CR3_WRITE (16 + 3)
270 #define INTERCEPT_CR4_WRITE (16 + 4)
271 #define INTERCEPT_CR8_WRITE (16 + 8)
273 #define INTERCEPT_DR0_READ 0
274 #define INTERCEPT_DR1_READ 1
275 #define INTERCEPT_DR2_READ 2
276 #define INTERCEPT_DR3_READ 3
277 #define INTERCEPT_DR4_READ 4
278 #define INTERCEPT_DR5_READ 5
279 #define INTERCEPT_DR6_READ 6
280 #define INTERCEPT_DR7_READ 7
281 #define INTERCEPT_DR0_WRITE (16 + 0)
282 #define INTERCEPT_DR1_WRITE (16 + 1)
283 #define INTERCEPT_DR2_WRITE (16 + 2)
284 #define INTERCEPT_DR3_WRITE (16 + 3)
285 #define INTERCEPT_DR4_WRITE (16 + 4)
286 #define INTERCEPT_DR5_WRITE (16 + 5)
287 #define INTERCEPT_DR6_WRITE (16 + 6)
288 #define INTERCEPT_DR7_WRITE (16 + 7)
290 #define SVM_EVTINJ_VEC_MASK 0xff
292 #define SVM_EVTINJ_TYPE_SHIFT 8
293 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
295 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
296 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
297 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
298 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
300 #define SVM_EVTINJ_VALID (1 << 31)
301 #define SVM_EVTINJ_VALID_ERR (1 << 11)
303 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
304 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
306 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
307 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
308 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
309 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
311 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
312 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
314 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
315 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
316 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
318 #define SVM_EXITINFO_REG_MASK 0x0F
320 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
322 #endif /* SELFTEST_KVM_SVM_H */