tools/testing/selftests/kvm/include/x86_64/processor.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * tools/testing/selftests/kvm/include/x86_64/processor.h
   4  *
   5  * Copyright (C) 2018, Google LLC.
   6  */
   7
   8 #ifndef SELFTEST_KVM_PROCESSOR_H
   9 #define SELFTEST_KVM_PROCESSOR_H
  10
  11 #include <assert.h>
  12 #include <stdint.h>
  13 #include <syscall.h>
  14
  15 #include <asm/msr-index.h>
  16 #include <asm/prctl.h>
  17
  18 #include <linux/stringify.h>
  19
  20 #include "../kvm_util.h"
  21
  22 extern bool host_cpu_is_intel;
  23 extern bool host_cpu_is_amd;
  24
  25 #define NMI_VECTOR              0x02
  26
  27 #define X86_EFLAGS_FIXED         (1u << 1)
  28
  29 #define X86_CR4_VME             (1ul << 0)
  30 #define X86_CR4_PVI             (1ul << 1)
  31 #define X86_CR4_TSD             (1ul << 2)
  32 #define X86_CR4_DE              (1ul << 3)
  33 #define X86_CR4_PSE             (1ul << 4)
  34 #define X86_CR4_PAE             (1ul << 5)
  35 #define X86_CR4_MCE             (1ul << 6)
  36 #define X86_CR4_PGE             (1ul << 7)
  37 #define X86_CR4_PCE             (1ul << 8)
  38 #define X86_CR4_OSFXSR          (1ul << 9)
  39 #define X86_CR4_OSXMMEXCPT      (1ul << 10)
  40 #define X86_CR4_UMIP            (1ul << 11)
  41 #define X86_CR4_LA57            (1ul << 12)
  42 #define X86_CR4_VMXE            (1ul << 13)
  43 #define X86_CR4_SMXE            (1ul << 14)
  44 #define X86_CR4_FSGSBASE        (1ul << 16)
  45 #define X86_CR4_PCIDE           (1ul << 17)
  46 #define X86_CR4_OSXSAVE         (1ul << 18)
  47 #define X86_CR4_SMEP            (1ul << 20)
  48 #define X86_CR4_SMAP            (1ul << 21)
  49 #define X86_CR4_PKE             (1ul << 22)
  50
  51 struct xstate_header {
  52         u64                             xstate_bv;
  53         u64                             xcomp_bv;
  54         u64                             reserved[6];
  55 } __attribute__((packed));
  56
  57 struct xstate {
  58         u8                              i387[512];
  59         struct xstate_header            header;
  60         u8                              extended_state_area[0];
  61 } __attribute__ ((packed, aligned (64)));
  62
  63 #define XFEATURE_MASK_FP                BIT_ULL(0)
  64 #define XFEATURE_MASK_SSE               BIT_ULL(1)
  65 #define XFEATURE_MASK_YMM               BIT_ULL(2)
  66 #define XFEATURE_MASK_BNDREGS           BIT_ULL(3)
  67 #define XFEATURE_MASK_BNDCSR            BIT_ULL(4)
  68 #define XFEATURE_MASK_OPMASK            BIT_ULL(5)
  69 #define XFEATURE_MASK_ZMM_Hi256         BIT_ULL(6)
  70 #define XFEATURE_MASK_Hi16_ZMM          BIT_ULL(7)
  71 #define XFEATURE_MASK_XTILE_CFG         BIT_ULL(17)
  72 #define XFEATURE_MASK_XTILE_DATA        BIT_ULL(18)
  73
  74 #define XFEATURE_MASK_AVX512            (XFEATURE_MASK_OPMASK | \
  75                                          XFEATURE_MASK_ZMM_Hi256 | \
  76                                          XFEATURE_MASK_Hi16_ZMM)
  77 #define XFEATURE_MASK_XTILE             (XFEATURE_MASK_XTILE_DATA | \
  78                                          XFEATURE_MASK_XTILE_CFG)
  79
  80 /* Note, these are ordered alphabetically to match kvm_cpuid_entry2.  Eww. */
  81 enum cpuid_output_regs {
  82         KVM_CPUID_EAX,
  83         KVM_CPUID_EBX,
  84         KVM_CPUID_ECX,
  85         KVM_CPUID_EDX
  86 };
  87
  88 /*
  89  * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be
  90  * passed by value with no overhead.
  91  */
  92 struct kvm_x86_cpu_feature {
  93         u32     function;
  94         u16     index;
  95         u8      reg;
  96         u8      bit;
  97 };
  98 #define KVM_X86_CPU_FEATURE(fn, idx, gpr, __bit)                                \
  99 ({                                                                              \
 100         struct kvm_x86_cpu_feature feature = {                                  \
 101                 .function = fn,                                                 \
 102                 .index = idx,                                                   \
 103                 .reg = KVM_CPUID_##gpr,                                         \
 104                 .bit = __bit,                                                   \
 105         };                                                                      \
 106                                                                                 \
 107         kvm_static_assert((fn & 0xc0000000) == 0 ||                             \
 108                           (fn & 0xc0000000) == 0x40000000 ||                    \
 109                           (fn & 0xc0000000) == 0x80000000 ||                    \
 110                           (fn & 0xc0000000) == 0xc0000000);                     \
 111         kvm_static_assert(idx < BIT(sizeof(feature.index) * BITS_PER_BYTE));    \
 112         feature;                                                                \
 113 })
 114
 115 /*
 116  * Basic Leafs, a.k.a. Intel defined
 117  */
 118 #define X86_FEATURE_MWAIT               KVM_X86_CPU_FEATURE(0x1, 0, ECX, 3)
 119 #define X86_FEATURE_VMX                 KVM_X86_CPU_FEATURE(0x1, 0, ECX, 5)
 120 #define X86_FEATURE_SMX                 KVM_X86_CPU_FEATURE(0x1, 0, ECX, 6)
 121 #define X86_FEATURE_PDCM                KVM_X86_CPU_FEATURE(0x1, 0, ECX, 15)
 122 #define X86_FEATURE_PCID                KVM_X86_CPU_FEATURE(0x1, 0, ECX, 17)
 123 #define X86_FEATURE_X2APIC              KVM_X86_CPU_FEATURE(0x1, 0, ECX, 21)
 124 #define X86_FEATURE_MOVBE               KVM_X86_CPU_FEATURE(0x1, 0, ECX, 22)
 125 #define X86_FEATURE_TSC_DEADLINE_TIMER  KVM_X86_CPU_FEATURE(0x1, 0, ECX, 24)
 126 #define X86_FEATURE_XSAVE               KVM_X86_CPU_FEATURE(0x1, 0, ECX, 26)
 127 #define X86_FEATURE_OSXSAVE             KVM_X86_CPU_FEATURE(0x1, 0, ECX, 27)
 128 #define X86_FEATURE_RDRAND              KVM_X86_CPU_FEATURE(0x1, 0, ECX, 30)
 129 #define X86_FEATURE_HYPERVISOR          KVM_X86_CPU_FEATURE(0x1, 0, ECX, 31)
 130 #define X86_FEATURE_PAE                 KVM_X86_CPU_FEATURE(0x1, 0, EDX, 6)
 131 #define X86_FEATURE_MCE                 KVM_X86_CPU_FEATURE(0x1, 0, EDX, 7)
 132 #define X86_FEATURE_APIC                KVM_X86_CPU_FEATURE(0x1, 0, EDX, 9)
 133 #define X86_FEATURE_CLFLUSH             KVM_X86_CPU_FEATURE(0x1, 0, EDX, 19)
 134 #define X86_FEATURE_XMM                 KVM_X86_CPU_FEATURE(0x1, 0, EDX, 25)
 135 #define X86_FEATURE_XMM2                KVM_X86_CPU_FEATURE(0x1, 0, EDX, 26)
 136 #define X86_FEATURE_FSGSBASE            KVM_X86_CPU_FEATURE(0x7, 0, EBX, 0)
 137 #define X86_FEATURE_TSC_ADJUST          KVM_X86_CPU_FEATURE(0x7, 0, EBX, 1)
 138 #define X86_FEATURE_SGX                 KVM_X86_CPU_FEATURE(0x7, 0, EBX, 2)
 139 #define X86_FEATURE_HLE                 KVM_X86_CPU_FEATURE(0x7, 0, EBX, 4)
 140 #define X86_FEATURE_SMEP                KVM_X86_CPU_FEATURE(0x7, 0, EBX, 7)
 141 #define X86_FEATURE_INVPCID             KVM_X86_CPU_FEATURE(0x7, 0, EBX, 10)
 142 #define X86_FEATURE_RTM                 KVM_X86_CPU_FEATURE(0x7, 0, EBX, 11)
 143 #define X86_FEATURE_MPX                 KVM_X86_CPU_FEATURE(0x7, 0, EBX, 14)
 144 #define X86_FEATURE_SMAP                KVM_X86_CPU_FEATURE(0x7, 0, EBX, 20)
 145 #define X86_FEATURE_PCOMMIT             KVM_X86_CPU_FEATURE(0x7, 0, EBX, 22)
 146 #define X86_FEATURE_CLFLUSHOPT          KVM_X86_CPU_FEATURE(0x7, 0, EBX, 23)
 147 #define X86_FEATURE_CLWB                KVM_X86_CPU_FEATURE(0x7, 0, EBX, 24)
 148 #define X86_FEATURE_UMIP                KVM_X86_CPU_FEATURE(0x7, 0, ECX, 2)
 149 #define X86_FEATURE_PKU                 KVM_X86_CPU_FEATURE(0x7, 0, ECX, 3)
 150 #define X86_FEATURE_LA57                KVM_X86_CPU_FEATURE(0x7, 0, ECX, 16)
 151 #define X86_FEATURE_RDPID               KVM_X86_CPU_FEATURE(0x7, 0, ECX, 22)
 152 #define X86_FEATURE_SGX_LC              KVM_X86_CPU_FEATURE(0x7, 0, ECX, 30)
 153 #define X86_FEATURE_SHSTK               KVM_X86_CPU_FEATURE(0x7, 0, ECX, 7)
 154 #define X86_FEATURE_IBT                 KVM_X86_CPU_FEATURE(0x7, 0, EDX, 20)
 155 #define X86_FEATURE_AMX_TILE            KVM_X86_CPU_FEATURE(0x7, 0, EDX, 24)
 156 #define X86_FEATURE_SPEC_CTRL           KVM_X86_CPU_FEATURE(0x7, 0, EDX, 26)
 157 #define X86_FEATURE_ARCH_CAPABILITIES   KVM_X86_CPU_FEATURE(0x7, 0, EDX, 29)
 158 #define X86_FEATURE_PKS                 KVM_X86_CPU_FEATURE(0x7, 0, ECX, 31)
 159 #define X86_FEATURE_XTILECFG            KVM_X86_CPU_FEATURE(0xD, 0, EAX, 17)
 160 #define X86_FEATURE_XTILEDATA           KVM_X86_CPU_FEATURE(0xD, 0, EAX, 18)
 161 #define X86_FEATURE_XSAVES              KVM_X86_CPU_FEATURE(0xD, 1, EAX, 3)
 162 #define X86_FEATURE_XFD                 KVM_X86_CPU_FEATURE(0xD, 1, EAX, 4)
 163 #define X86_FEATURE_XTILEDATA_XFD       KVM_X86_CPU_FEATURE(0xD, 18, ECX, 2)
 164
 165 /*
 166  * Extended Leafs, a.k.a. AMD defined
 167  */
 168 #define X86_FEATURE_SVM                 KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 2)
 169 #define X86_FEATURE_NX                  KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 20)
 170 #define X86_FEATURE_GBPAGES             KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 26)
 171 #define X86_FEATURE_RDTSCP              KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 27)
 172 #define X86_FEATURE_LM                  KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 29)
 173 #define X86_FEATURE_INVTSC              KVM_X86_CPU_FEATURE(0x80000007, 0, EDX, 8)
 174 #define X86_FEATURE_RDPRU               KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 4)
 175 #define X86_FEATURE_AMD_IBPB            KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 12)
 176 #define X86_FEATURE_NPT                 KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 0)
 177 #define X86_FEATURE_LBRV                KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 1)
 178 #define X86_FEATURE_NRIPS               KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 3)
 179 #define X86_FEATURE_TSCRATEMSR          KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 4)
 180 #define X86_FEATURE_PAUSEFILTER         KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 10)
 181 #define X86_FEATURE_PFTHRESHOLD         KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 12)
 182 #define X86_FEATURE_VGIF                KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 16)
 183 #define X86_FEATURE_SEV                 KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 1)
 184 #define X86_FEATURE_SEV_ES              KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 3)
 185
 186 /*
 187  * KVM defined paravirt features.
 188  */
 189 #define X86_FEATURE_KVM_CLOCKSOURCE     KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 0)
 190 #define X86_FEATURE_KVM_NOP_IO_DELAY    KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 1)
 191 #define X86_FEATURE_KVM_MMU_OP          KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 2)
 192 #define X86_FEATURE_KVM_CLOCKSOURCE2    KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 3)
 193 #define X86_FEATURE_KVM_ASYNC_PF        KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 4)
 194 #define X86_FEATURE_KVM_STEAL_TIME      KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 5)
 195 #define X86_FEATURE_KVM_PV_EOI          KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 6)
 196 #define X86_FEATURE_KVM_PV_UNHALT       KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 7)
 197 /* Bit 8 apparently isn't used?!?! */
 198 #define X86_FEATURE_KVM_PV_TLB_FLUSH    KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 9)
 199 #define X86_FEATURE_KVM_ASYNC_PF_VMEXIT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 10)
 200 #define X86_FEATURE_KVM_PV_SEND_IPI     KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 11)
 201 #define X86_FEATURE_KVM_POLL_CONTROL    KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 12)
 202 #define X86_FEATURE_KVM_PV_SCHED_YIELD  KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 13)
 203 #define X86_FEATURE_KVM_ASYNC_PF_INT    KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 14)
 204 #define X86_FEATURE_KVM_MSI_EXT_DEST_ID KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 15)
 205 #define X86_FEATURE_KVM_HC_MAP_GPA_RANGE        KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 16)
 206 #define X86_FEATURE_KVM_MIGRATION_CONTROL       KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 17)
 207
 208 /*
 209  * Same idea as X86_FEATURE_XXX, but X86_PROPERTY_XXX retrieves a multi-bit
 210  * value/property as opposed to a single-bit feature.  Again, pack the info
 211  * into a 64-bit value to pass by value with no overhead.
 212  */
 213 struct kvm_x86_cpu_property {
 214         u32     function;
 215         u8      index;
 216         u8      reg;
 217         u8      lo_bit;
 218         u8      hi_bit;
 219 };
 220 #define KVM_X86_CPU_PROPERTY(fn, idx, gpr, low_bit, high_bit)                   \
 221 ({                                                                              \
 222         struct kvm_x86_cpu_property property = {                                \
 223                 .function = fn,                                                 \
 224                 .index = idx,                                                   \
 225                 .reg = KVM_CPUID_##gpr,                                         \
 226                 .lo_bit = low_bit,                                              \
 227                 .hi_bit = high_bit,                                             \
 228         };                                                                      \
 229                                                                                 \
 230         kvm_static_assert(low_bit < high_bit);                                  \
 231         kvm_static_assert((fn & 0xc0000000) == 0 ||                             \
 232                           (fn & 0xc0000000) == 0x40000000 ||                    \
 233                           (fn & 0xc0000000) == 0x80000000 ||                    \
 234                           (fn & 0xc0000000) == 0xc0000000);                     \
 235         kvm_static_assert(idx < BIT(sizeof(property.index) * BITS_PER_BYTE));   \
 236         property;                                                               \
 237 })
 238
 239 #define X86_PROPERTY_MAX_BASIC_LEAF             KVM_X86_CPU_PROPERTY(0, 0, EAX, 0, 31)
 240 #define X86_PROPERTY_PMU_VERSION                KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 0, 7)
 241 #define X86_PROPERTY_PMU_NR_GP_COUNTERS         KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 8, 15)
 242 #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH  KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 24, 31)
 243
 244 #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0       KVM_X86_CPU_PROPERTY(0xd,  0, EBX,  0, 31)
 245 #define X86_PROPERTY_XSTATE_MAX_SIZE            KVM_X86_CPU_PROPERTY(0xd,  0, ECX,  0, 31)
 246 #define X86_PROPERTY_XSTATE_TILE_SIZE           KVM_X86_CPU_PROPERTY(0xd, 18, EAX,  0, 31)
 247 #define X86_PROPERTY_XSTATE_TILE_OFFSET         KVM_X86_CPU_PROPERTY(0xd, 18, EBX,  0, 31)
 248 #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES     KVM_X86_CPU_PROPERTY(0x1d, 0, EAX,  0, 31)
 249 #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES       KVM_X86_CPU_PROPERTY(0x1d, 1, EAX,  0, 15)
 250 #define X86_PROPERTY_AMX_BYTES_PER_TILE         KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31)
 251 #define X86_PROPERTY_AMX_BYTES_PER_ROW          KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 0,  15)
 252 #define X86_PROPERTY_AMX_NR_TILE_REGS           KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 16, 31)
 253 #define X86_PROPERTY_AMX_MAX_ROWS               KVM_X86_CPU_PROPERTY(0x1d, 1, ECX, 0,  15)
 254
 255 #define X86_PROPERTY_MAX_KVM_LEAF               KVM_X86_CPU_PROPERTY(0x40000000, 0, EAX, 0, 31)
 256
 257 #define X86_PROPERTY_MAX_EXT_LEAF               KVM_X86_CPU_PROPERTY(0x80000000, 0, EAX, 0, 31)
 258 #define X86_PROPERTY_MAX_PHY_ADDR               KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 0, 7)
 259 #define X86_PROPERTY_MAX_VIRT_ADDR              KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 8, 15)
 260 #define X86_PROPERTY_PHYS_ADDR_REDUCTION        KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11)
 261
 262 #define X86_PROPERTY_MAX_CENTAUR_LEAF           KVM_X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31)
 263
 264 /*
 265  * Intel's architectural PMU events are bizarre.  They have a "feature" bit
 266  * that indicates the feature is _not_ supported, and a property that states
 267  * the length of the bit mask of unsupported features.  A feature is supported
 268  * if the size of the bit mask is larger than the "unavailable" bit, and said
 269  * bit is not set.
 270  *
 271  * Wrap the "unavailable" feature to simplify checking whether or not a given
 272  * architectural event is supported.
 273  */
 274 struct kvm_x86_pmu_feature {
 275         struct kvm_x86_cpu_feature anti_feature;
 276 };
 277 #define KVM_X86_PMU_FEATURE(name, __bit)                                        \
 278 ({                                                                              \
 279         struct kvm_x86_pmu_feature feature = {                                  \
 280                 .anti_feature = KVM_X86_CPU_FEATURE(0xa, 0, EBX, __bit),        \
 281         };                                                                      \
 282                                                                                 \
 283         feature;                                                                \
 284 })
 285
 286 #define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED    KVM_X86_PMU_FEATURE(BRANCH_INSNS_RETIRED, 5)
 287
 288 static inline unsigned int x86_family(unsigned int eax)
 289 {
 290         unsigned int x86;
 291
 292         x86 = (eax >> 8) & 0xf;
 293
 294         if (x86 == 0xf)
 295                 x86 += (eax >> 20) & 0xff;
 296
 297         return x86;
 298 }
 299
 300 static inline unsigned int x86_model(unsigned int eax)
 301 {
 302         return ((eax >> 12) & 0xf0) | ((eax >> 4) & 0x0f);
 303 }
 304
 305 /* Page table bitfield declarations */
 306 #define PTE_PRESENT_MASK        BIT_ULL(0)
 307 #define PTE_WRITABLE_MASK       BIT_ULL(1)
 308 #define PTE_USER_MASK           BIT_ULL(2)
 309 #define PTE_ACCESSED_MASK       BIT_ULL(5)
 310 #define PTE_DIRTY_MASK          BIT_ULL(6)
 311 #define PTE_LARGE_MASK          BIT_ULL(7)
 312 #define PTE_GLOBAL_MASK         BIT_ULL(8)
 313 #define PTE_NX_MASK             BIT_ULL(63)
 314
 315 #define PHYSICAL_PAGE_MASK      GENMASK_ULL(51, 12)
 316
 317 #define PAGE_SHIFT              12
 318 #define PAGE_SIZE               (1ULL << PAGE_SHIFT)
 319 #define PAGE_MASK               (~(PAGE_SIZE-1) & PHYSICAL_PAGE_MASK)
 320
 321 #define HUGEPAGE_SHIFT(x)       (PAGE_SHIFT + (((x) - 1) * 9))
 322 #define HUGEPAGE_SIZE(x)        (1UL << HUGEPAGE_SHIFT(x))
 323 #define HUGEPAGE_MASK(x)        (~(HUGEPAGE_SIZE(x) - 1) & PHYSICAL_PAGE_MASK)
 324
 325 #define PTE_GET_PA(pte)         ((pte) & PHYSICAL_PAGE_MASK)
 326 #define PTE_GET_PFN(pte)        (PTE_GET_PA(pte) >> PAGE_SHIFT)
 327
 328 /* General Registers in 64-Bit Mode */
 329 struct gpr64_regs {
 330         u64 rax;
 331         u64 rcx;
 332         u64 rdx;
 333         u64 rbx;
 334         u64 rsp;
 335         u64 rbp;
 336         u64 rsi;
 337         u64 rdi;
 338         u64 r8;
 339         u64 r9;
 340         u64 r10;
 341         u64 r11;
 342         u64 r12;
 343         u64 r13;
 344         u64 r14;
 345         u64 r15;
 346 };
 347
 348 struct desc64 {
 349         uint16_t limit0;
 350         uint16_t base0;
 351         unsigned base1:8, type:4, s:1, dpl:2, p:1;
 352         unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8;
 353         uint32_t base3;
 354         uint32_t zero1;
 355 } __attribute__((packed));
 356
 357 struct desc_ptr {
 358         uint16_t size;
 359         uint64_t address;
 360 } __attribute__((packed));
 361
 362 struct kvm_x86_state {
 363         struct kvm_xsave *xsave;
 364         struct kvm_vcpu_events events;
 365         struct kvm_mp_state mp_state;
 366         struct kvm_regs regs;
 367         struct kvm_xcrs xcrs;
 368         struct kvm_sregs sregs;
 369         struct kvm_debugregs debugregs;
 370         union {
 371                 struct kvm_nested_state nested;
 372                 char nested_[16384];
 373         };
 374         struct kvm_msrs msrs;
 375 };
 376
 377 static inline uint64_t get_desc64_base(const struct desc64 *desc)
 378 {
 379         return ((uint64_t)desc->base3 << 32) |
 380                 (desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
 381 }
 382
 383 static inline uint64_t rdtsc(void)
 384 {
 385         uint32_t eax, edx;
 386         uint64_t tsc_val;
 387         /*
 388          * The lfence is to wait (on Intel CPUs) until all previous
 389          * instructions have been executed. If software requires RDTSC to be
 390          * executed prior to execution of any subsequent instruction, it can
 391          * execute LFENCE immediately after RDTSC
 392          */
 393         __asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx));
 394         tsc_val = ((uint64_t)edx) << 32 | eax;
 395         return tsc_val;
 396 }
 397
 398 static inline uint64_t rdtscp(uint32_t *aux)
 399 {
 400         uint32_t eax, edx;
 401
 402         __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux));
 403         return ((uint64_t)edx) << 32 | eax;
 404 }
 405
 406 static inline uint64_t rdmsr(uint32_t msr)
 407 {
 408         uint32_t a, d;
 409
 410         __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory");
 411
 412         return a | ((uint64_t) d << 32);
 413 }
 414
 415 static inline void wrmsr(uint32_t msr, uint64_t value)
 416 {
 417         uint32_t a = value;
 418         uint32_t d = value >> 32;
 419
 420         __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory");
 421 }
 422
 423
 424 static inline uint16_t inw(uint16_t port)
 425 {
 426         uint16_t tmp;
 427
 428         __asm__ __volatile__("in %%dx, %%ax"
 429                 : /* output */ "=a" (tmp)
 430                 : /* input */ "d" (port));
 431
 432         return tmp;
 433 }
 434
 435 static inline uint16_t get_es(void)
 436 {
 437         uint16_t es;
 438
 439         __asm__ __volatile__("mov %%es, %[es]"
 440                              : /* output */ [es]"=rm"(es));
 441         return es;
 442 }
 443
 444 static inline uint16_t get_cs(void)
 445 {
 446         uint16_t cs;
 447
 448         __asm__ __volatile__("mov %%cs, %[cs]"
 449                              : /* output */ [cs]"=rm"(cs));
 450         return cs;
 451 }
 452
 453 static inline uint16_t get_ss(void)
 454 {
 455         uint16_t ss;
 456
 457         __asm__ __volatile__("mov %%ss, %[ss]"
 458                              : /* output */ [ss]"=rm"(ss));
 459         return ss;
 460 }
 461
 462 static inline uint16_t get_ds(void)
 463 {
 464         uint16_t ds;
 465
 466         __asm__ __volatile__("mov %%ds, %[ds]"
 467                              : /* output */ [ds]"=rm"(ds));
 468         return ds;
 469 }
 470
 471 static inline uint16_t get_fs(void)
 472 {
 473         uint16_t fs;
 474
 475         __asm__ __volatile__("mov %%fs, %[fs]"
 476                              : /* output */ [fs]"=rm"(fs));
 477         return fs;
 478 }
 479
 480 static inline uint16_t get_gs(void)
 481 {
 482         uint16_t gs;
 483
 484         __asm__ __volatile__("mov %%gs, %[gs]"
 485                              : /* output */ [gs]"=rm"(gs));
 486         return gs;
 487 }
 488
 489 static inline uint16_t get_tr(void)
 490 {
 491         uint16_t tr;
 492
 493         __asm__ __volatile__("str %[tr]"
 494                              : /* output */ [tr]"=rm"(tr));
 495         return tr;
 496 }
 497
 498 static inline uint64_t get_cr0(void)
 499 {
 500         uint64_t cr0;
 501
 502         __asm__ __volatile__("mov %%cr0, %[cr0]"
 503                              : /* output */ [cr0]"=r"(cr0));
 504         return cr0;
 505 }
 506
 507 static inline uint64_t get_cr3(void)
 508 {
 509         uint64_t cr3;
 510
 511         __asm__ __volatile__("mov %%cr3, %[cr3]"
 512                              : /* output */ [cr3]"=r"(cr3));
 513         return cr3;
 514 }
 515
 516 static inline uint64_t get_cr4(void)
 517 {
 518         uint64_t cr4;
 519
 520         __asm__ __volatile__("mov %%cr4, %[cr4]"
 521                              : /* output */ [cr4]"=r"(cr4));
 522         return cr4;
 523 }
 524
 525 static inline void set_cr4(uint64_t val)
 526 {
 527         __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory");
 528 }
 529
 530 static inline u64 xgetbv(u32 index)
 531 {
 532         u32 eax, edx;
 533
 534         __asm__ __volatile__("xgetbv;"
 535                      : "=a" (eax), "=d" (edx)
 536                      : "c" (index));
 537         return eax | ((u64)edx << 32);
 538 }
 539
 540 static inline void xsetbv(u32 index, u64 value)
 541 {
 542         u32 eax = value;
 543         u32 edx = value >> 32;
 544
 545         __asm__ __volatile__("xsetbv" :: "a" (eax), "d" (edx), "c" (index));
 546 }
 547
 548 static inline struct desc_ptr get_gdt(void)
 549 {
 550         struct desc_ptr gdt;
 551         __asm__ __volatile__("sgdt %[gdt]"
 552                              : /* output */ [gdt]"=m"(gdt));
 553         return gdt;
 554 }
 555
 556 static inline struct desc_ptr get_idt(void)
 557 {
 558         struct desc_ptr idt;
 559         __asm__ __volatile__("sidt %[idt]"
 560                              : /* output */ [idt]"=m"(idt));
 561         return idt;
 562 }
 563
 564 static inline void outl(uint16_t port, uint32_t value)
 565 {
 566         __asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value));
 567 }
 568
 569 static inline void __cpuid(uint32_t function, uint32_t index,
 570                            uint32_t *eax, uint32_t *ebx,
 571                            uint32_t *ecx, uint32_t *edx)
 572 {
 573         *eax = function;
 574         *ecx = index;
 575
 576         asm volatile("cpuid"
 577             : "=a" (*eax),
 578               "=b" (*ebx),
 579               "=c" (*ecx),
 580               "=d" (*edx)
 581             : "0" (*eax), "2" (*ecx)
 582             : "memory");
 583 }
 584
 585 static inline void cpuid(uint32_t function,
 586                          uint32_t *eax, uint32_t *ebx,
 587                          uint32_t *ecx, uint32_t *edx)
 588 {
 589         return __cpuid(function, 0, eax, ebx, ecx, edx);
 590 }
 591
 592 static inline uint32_t this_cpu_fms(void)
 593 {
 594         uint32_t eax, ebx, ecx, edx;
 595
 596         cpuid(1, &eax, &ebx, &ecx, &edx);
 597         return eax;
 598 }
 599
 600 static inline uint32_t this_cpu_family(void)
 601 {
 602         return x86_family(this_cpu_fms());
 603 }
 604
 605 static inline uint32_t this_cpu_model(void)
 606 {
 607         return x86_model(this_cpu_fms());
 608 }
 609
 610 static inline bool this_cpu_vendor_string_is(const char *vendor)
 611 {
 612         const uint32_t *chunk = (const uint32_t *)vendor;
 613         uint32_t eax, ebx, ecx, edx;
 614
 615         cpuid(0, &eax, &ebx, &ecx, &edx);
 616         return (ebx == chunk[0] && edx == chunk[1] && ecx == chunk[2]);
 617 }
 618
 619 static inline bool this_cpu_is_intel(void)
 620 {
 621         return this_cpu_vendor_string_is("GenuineIntel");
 622 }
 623
 624 /*
 625  * Exclude early K5 samples with a vendor string of "AMDisbetter!"
 626  */
 627 static inline bool this_cpu_is_amd(void)
 628 {
 629         return this_cpu_vendor_string_is("AuthenticAMD");
 630 }
 631
 632 static inline uint32_t __this_cpu_has(uint32_t function, uint32_t index,
 633                                       uint8_t reg, uint8_t lo, uint8_t hi)
 634 {
 635         uint32_t gprs[4];
 636
 637         __cpuid(function, index,
 638                 &gprs[KVM_CPUID_EAX], &gprs[KVM_CPUID_EBX],
 639                 &gprs[KVM_CPUID_ECX], &gprs[KVM_CPUID_EDX]);
 640
 641         return (gprs[reg] & GENMASK(hi, lo)) >> lo;
 642 }
 643
 644 static inline bool this_cpu_has(struct kvm_x86_cpu_feature feature)
 645 {
 646         return __this_cpu_has(feature.function, feature.index,
 647                               feature.reg, feature.bit, feature.bit);
 648 }
 649
 650 static inline uint32_t this_cpu_property(struct kvm_x86_cpu_property property)
 651 {
 652         return __this_cpu_has(property.function, property.index,
 653                               property.reg, property.lo_bit, property.hi_bit);
 654 }
 655
 656 static __always_inline bool this_cpu_has_p(struct kvm_x86_cpu_property property)
 657 {
 658         uint32_t max_leaf;
 659
 660         switch (property.function & 0xc0000000) {
 661         case 0:
 662                 max_leaf = this_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF);
 663                 break;
 664         case 0x40000000:
 665                 max_leaf = this_cpu_property(X86_PROPERTY_MAX_KVM_LEAF);
 666                 break;
 667         case 0x80000000:
 668                 max_leaf = this_cpu_property(X86_PROPERTY_MAX_EXT_LEAF);
 669                 break;
 670         case 0xc0000000:
 671                 max_leaf = this_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF);
 672         }
 673         return max_leaf >= property.function;
 674 }
 675
 676 static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature)
 677 {
 678         uint32_t nr_bits = this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH);
 679
 680         return nr_bits > feature.anti_feature.bit &&
 681                !this_cpu_has(feature.anti_feature);
 682 }
 683
 684 typedef u32             __attribute__((vector_size(16))) sse128_t;
 685 #define __sse128_u      union { sse128_t vec; u64 as_u64[2]; u32 as_u32[4]; }
 686 #define sse128_lo(x)    ({ __sse128_u t; t.vec = x; t.as_u64[0]; })
 687 #define sse128_hi(x)    ({ __sse128_u t; t.vec = x; t.as_u64[1]; })
 688
 689 static inline void read_sse_reg(int reg, sse128_t *data)
 690 {
 691         switch (reg) {
 692         case 0:
 693                 asm("movdqa %%xmm0, %0" : "=m"(*data));
 694                 break;
 695         case 1:
 696                 asm("movdqa %%xmm1, %0" : "=m"(*data));
 697                 break;
 698         case 2:
 699                 asm("movdqa %%xmm2, %0" : "=m"(*data));
 700                 break;
 701         case 3:
 702                 asm("movdqa %%xmm3, %0" : "=m"(*data));
 703                 break;
 704         case 4:
 705                 asm("movdqa %%xmm4, %0" : "=m"(*data));
 706                 break;
 707         case 5:
 708                 asm("movdqa %%xmm5, %0" : "=m"(*data));
 709                 break;
 710         case 6:
 711                 asm("movdqa %%xmm6, %0" : "=m"(*data));
 712                 break;
 713         case 7:
 714                 asm("movdqa %%xmm7, %0" : "=m"(*data));
 715                 break;
 716         default:
 717                 BUG();
 718         }
 719 }
 720
 721 static inline void write_sse_reg(int reg, const sse128_t *data)
 722 {
 723         switch (reg) {
 724         case 0:
 725                 asm("movdqa %0, %%xmm0" : : "m"(*data));
 726                 break;
 727         case 1:
 728                 asm("movdqa %0, %%xmm1" : : "m"(*data));
 729                 break;
 730         case 2:
 731                 asm("movdqa %0, %%xmm2" : : "m"(*data));
 732                 break;
 733         case 3:
 734                 asm("movdqa %0, %%xmm3" : : "m"(*data));
 735                 break;
 736         case 4:
 737                 asm("movdqa %0, %%xmm4" : : "m"(*data));
 738                 break;
 739         case 5:
 740                 asm("movdqa %0, %%xmm5" : : "m"(*data));
 741                 break;
 742         case 6:
 743                 asm("movdqa %0, %%xmm6" : : "m"(*data));
 744                 break;
 745         case 7:
 746                 asm("movdqa %0, %%xmm7" : : "m"(*data));
 747                 break;
 748         default:
 749                 BUG();
 750         }
 751 }
 752
 753 static inline void cpu_relax(void)
 754 {
 755         asm volatile("rep; nop" ::: "memory");
 756 }
 757
 758 #define ud2()                   \
 759         __asm__ __volatile__(   \
 760                 "ud2\n" \
 761                 )
 762
 763 #define hlt()                   \
 764         __asm__ __volatile__(   \
 765                 "hlt\n" \
 766                 )
 767
 768 struct kvm_x86_state *vcpu_save_state(struct kvm_vcpu *vcpu);
 769 void vcpu_load_state(struct kvm_vcpu *vcpu, struct kvm_x86_state *state);
 770 void kvm_x86_state_cleanup(struct kvm_x86_state *state);
 771
 772 const struct kvm_msr_list *kvm_get_msr_index_list(void);
 773 const struct kvm_msr_list *kvm_get_feature_msr_index_list(void);
 774 bool kvm_msr_is_in_save_restore_list(uint32_t msr_index);
 775 uint64_t kvm_get_feature_msr(uint64_t msr_index);
 776
 777 static inline void vcpu_msrs_get(struct kvm_vcpu *vcpu,
 778                                  struct kvm_msrs *msrs)
 779 {
 780         int r = __vcpu_ioctl(vcpu, KVM_GET_MSRS, msrs);
 781
 782         TEST_ASSERT(r == msrs->nmsrs,
 783                     "KVM_GET_MSRS failed, r: %i (failed on MSR %x)",
 784                     r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index);
 785 }
 786 static inline void vcpu_msrs_set(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs)
 787 {
 788         int r = __vcpu_ioctl(vcpu, KVM_SET_MSRS, msrs);
 789
 790         TEST_ASSERT(r == msrs->nmsrs,
 791                     "KVM_SET_MSRS failed, r: %i (failed on MSR %x)",
 792                     r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index);
 793 }
 794 static inline void vcpu_debugregs_get(struct kvm_vcpu *vcpu,
 795                                       struct kvm_debugregs *debugregs)
 796 {
 797         vcpu_ioctl(vcpu, KVM_GET_DEBUGREGS, debugregs);
 798 }
 799 static inline void vcpu_debugregs_set(struct kvm_vcpu *vcpu,
 800                                       struct kvm_debugregs *debugregs)
 801 {
 802         vcpu_ioctl(vcpu, KVM_SET_DEBUGREGS, debugregs);
 803 }
 804 static inline void vcpu_xsave_get(struct kvm_vcpu *vcpu,
 805                                   struct kvm_xsave *xsave)
 806 {
 807         vcpu_ioctl(vcpu, KVM_GET_XSAVE, xsave);
 808 }
 809 static inline void vcpu_xsave2_get(struct kvm_vcpu *vcpu,
 810                                    struct kvm_xsave *xsave)
 811 {
 812         vcpu_ioctl(vcpu, KVM_GET_XSAVE2, xsave);
 813 }
 814 static inline void vcpu_xsave_set(struct kvm_vcpu *vcpu,
 815                                   struct kvm_xsave *xsave)
 816 {
 817         vcpu_ioctl(vcpu, KVM_SET_XSAVE, xsave);
 818 }
 819 static inline void vcpu_xcrs_get(struct kvm_vcpu *vcpu,
 820                                  struct kvm_xcrs *xcrs)
 821 {
 822         vcpu_ioctl(vcpu, KVM_GET_XCRS, xcrs);
 823 }
 824 static inline void vcpu_xcrs_set(struct kvm_vcpu *vcpu, struct kvm_xcrs *xcrs)
 825 {
 826         vcpu_ioctl(vcpu, KVM_SET_XCRS, xcrs);
 827 }
 828
 829 const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid,
 830                                                uint32_t function, uint32_t index);
 831 const struct kvm_cpuid2 *kvm_get_supported_cpuid(void);
 832 const struct kvm_cpuid2 *kvm_get_supported_hv_cpuid(void);
 833 const struct kvm_cpuid2 *vcpu_get_supported_hv_cpuid(struct kvm_vcpu *vcpu);
 834
 835 static inline uint32_t kvm_cpu_fms(void)
 836 {
 837         return get_cpuid_entry(kvm_get_supported_cpuid(), 0x1, 0)->eax;
 838 }
 839
 840 static inline uint32_t kvm_cpu_family(void)
 841 {
 842         return x86_family(kvm_cpu_fms());
 843 }
 844
 845 static inline uint32_t kvm_cpu_model(void)
 846 {
 847         return x86_model(kvm_cpu_fms());
 848 }
 849
 850 bool kvm_cpuid_has(const struct kvm_cpuid2 *cpuid,
 851                    struct kvm_x86_cpu_feature feature);
 852
 853 static inline bool kvm_cpu_has(struct kvm_x86_cpu_feature feature)
 854 {
 855         return kvm_cpuid_has(kvm_get_supported_cpuid(), feature);
 856 }
 857
 858 uint32_t kvm_cpuid_property(const struct kvm_cpuid2 *cpuid,
 859                             struct kvm_x86_cpu_property property);
 860
 861 static inline uint32_t kvm_cpu_property(struct kvm_x86_cpu_property property)
 862 {
 863         return kvm_cpuid_property(kvm_get_supported_cpuid(), property);
 864 }
 865
 866 static __always_inline bool kvm_cpu_has_p(struct kvm_x86_cpu_property property)
 867 {
 868         uint32_t max_leaf;
 869
 870         switch (property.function & 0xc0000000) {
 871         case 0:
 872                 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF);
 873                 break;
 874         case 0x40000000:
 875                 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_KVM_LEAF);
 876                 break;
 877         case 0x80000000:
 878                 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_EXT_LEAF);
 879                 break;
 880         case 0xc0000000:
 881                 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF);
 882         }
 883         return max_leaf >= property.function;
 884 }
 885
 886 static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature)
 887 {
 888         uint32_t nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH);
 889
 890         return nr_bits > feature.anti_feature.bit &&
 891                !kvm_cpu_has(feature.anti_feature);
 892 }
 893
 894 static inline size_t kvm_cpuid2_size(int nr_entries)
 895 {
 896         return sizeof(struct kvm_cpuid2) +
 897                sizeof(struct kvm_cpuid_entry2) * nr_entries;
 898 }
 899
 900 /*
 901  * Allocate a "struct kvm_cpuid2* instance, with the 0-length arrary of
 902  * entries sized to hold @nr_entries.  The caller is responsible for freeing
 903  * the struct.
 904  */
 905 static inline struct kvm_cpuid2 *allocate_kvm_cpuid2(int nr_entries)
 906 {
 907         struct kvm_cpuid2 *cpuid;
 908
 909         cpuid = malloc(kvm_cpuid2_size(nr_entries));
 910         TEST_ASSERT(cpuid, "-ENOMEM when allocating kvm_cpuid2");
 911
 912         cpuid->nent = nr_entries;
 913
 914         return cpuid;
 915 }
 916
 917 void vcpu_init_cpuid(struct kvm_vcpu *vcpu, const struct kvm_cpuid2 *cpuid);
 918 void vcpu_set_hv_cpuid(struct kvm_vcpu *vcpu);
 919
 920 static inline struct kvm_cpuid_entry2 *__vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu,
 921                                                               uint32_t function,
 922                                                               uint32_t index)
 923 {
 924         return (struct kvm_cpuid_entry2 *)get_cpuid_entry(vcpu->cpuid,
 925                                                           function, index);
 926 }
 927
 928 static inline struct kvm_cpuid_entry2 *vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu,
 929                                                             uint32_t function)
 930 {
 931         return __vcpu_get_cpuid_entry(vcpu, function, 0);
 932 }
 933
 934 static inline int __vcpu_set_cpuid(struct kvm_vcpu *vcpu)
 935 {
 936         int r;
 937
 938         TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first");
 939         r = __vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid);
 940         if (r)
 941                 return r;
 942
 943         /* On success, refresh the cache to pick up adjustments made by KVM. */
 944         vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid);
 945         return 0;
 946 }
 947
 948 static inline void vcpu_set_cpuid(struct kvm_vcpu *vcpu)
 949 {
 950         TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first");
 951         vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid);
 952
 953         /* Refresh the cache to pick up adjustments made by KVM. */
 954         vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid);
 955 }
 956
 957 void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, uint8_t maxphyaddr);
 958
 959 void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, uint32_t function);
 960 void vcpu_set_or_clear_cpuid_feature(struct kvm_vcpu *vcpu,
 961                                      struct kvm_x86_cpu_feature feature,
 962                                      bool set);
 963
 964 static inline void vcpu_set_cpuid_feature(struct kvm_vcpu *vcpu,
 965                                           struct kvm_x86_cpu_feature feature)
 966 {
 967         vcpu_set_or_clear_cpuid_feature(vcpu, feature, true);
 968
 969 }
 970
 971 static inline void vcpu_clear_cpuid_feature(struct kvm_vcpu *vcpu,
 972                                             struct kvm_x86_cpu_feature feature)
 973 {
 974         vcpu_set_or_clear_cpuid_feature(vcpu, feature, false);
 975 }
 976
 977 uint64_t vcpu_get_msr(struct kvm_vcpu *vcpu, uint64_t msr_index);
 978 int _vcpu_set_msr(struct kvm_vcpu *vcpu, uint64_t msr_index, uint64_t msr_value);
 979
 980 static inline void vcpu_set_msr(struct kvm_vcpu *vcpu, uint64_t msr_index,
 981                                 uint64_t msr_value)
 982 {
 983         int r = _vcpu_set_msr(vcpu, msr_index, msr_value);
 984
 985         TEST_ASSERT(r == 1, KVM_IOCTL_ERROR(KVM_SET_MSRS, r));
 986 }
 987
 988
 989 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits);
 990 bool vm_is_unrestricted_guest(struct kvm_vm *vm);
 991
 992 struct ex_regs {
 993         uint64_t rax, rcx, rdx, rbx;
 994         uint64_t rbp, rsi, rdi;
 995         uint64_t r8, r9, r10, r11;
 996         uint64_t r12, r13, r14, r15;
 997         uint64_t vector;
 998         uint64_t error_code;
 999         uint64_t rip;
1000         uint64_t cs;
1001         uint64_t rflags;
1002 };
1003
1004 struct idt_entry {
1005         uint16_t offset0;
1006         uint16_t selector;
1007         uint16_t ist : 3;
1008         uint16_t : 5;
1009         uint16_t type : 4;
1010         uint16_t : 1;
1011         uint16_t dpl : 2;
1012         uint16_t p : 1;
1013         uint16_t offset1;
1014         uint32_t offset2; uint32_t reserved;
1015 };
1016
1017 void vm_init_descriptor_tables(struct kvm_vm *vm);
1018 void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu);
1019 void vm_install_exception_handler(struct kvm_vm *vm, int vector,
1020                         void (*handler)(struct ex_regs *));
1021
1022 /* If a toddler were to say "abracadabra". */
1023 #define KVM_EXCEPTION_MAGIC 0xabacadabaULL
1024
1025 /*
1026  * KVM selftest exception fixup uses registers to coordinate with the exception
1027  * handler, versus the kernel's in-memory tables and KVM-Unit-Tests's in-memory
1028  * per-CPU data.  Using only registers avoids having to map memory into the
1029  * guest, doesn't require a valid, stable GS.base, and reduces the risk of
1030  * for recursive faults when accessing memory in the handler.  The downside to
1031  * using registers is that it restricts what registers can be used by the actual
1032  * instruction.  But, selftests are 64-bit only, making register* pressure a
1033  * minor concern.  Use r9-r11 as they are volatile, i.e. don't need to be saved
1034  * by the callee, and except for r11 are not implicit parameters to any
1035  * instructions.  Ideally, fixup would use r8-r10 and thus avoid implicit
1036  * parameters entirely, but Hyper-V's hypercall ABI uses r8 and testing Hyper-V
1037  * is higher priority than testing non-faulting SYSCALL/SYSRET.
1038  *
1039  * Note, the fixup handler deliberately does not handle #DE, i.e. the vector
1040  * is guaranteed to be non-zero on fault.
1041  *
1042  * REGISTER INPUTS:
1043  * r9  = MAGIC
1044  * r10 = RIP
1045  * r11 = new RIP on fault
1046  *
1047  * REGISTER OUTPUTS:
1048  * r9  = exception vector (non-zero)
1049  * r10 = error code
1050  */
1051 #define KVM_ASM_SAFE(insn)                                      \
1052         "mov $" __stringify(KVM_EXCEPTION_MAGIC) ", %%r9\n\t"   \
1053         "lea 1f(%%rip), %%r10\n\t"                              \
1054         "lea 2f(%%rip), %%r11\n\t"                              \
1055         "1: " insn "\n\t"                                       \
1056         "xor %%r9, %%r9\n\t"                                    \
1057         "2:\n\t"                                                \
1058         "mov  %%r9b, %[vector]\n\t"                             \
1059         "mov  %%r10, %[error_code]\n\t"
1060
1061 #define KVM_ASM_SAFE_OUTPUTS(v, ec)     [vector] "=qm"(v), [error_code] "=rm"(ec)
1062 #define KVM_ASM_SAFE_CLOBBERS   "r9", "r10", "r11"
1063
1064 #define kvm_asm_safe(insn, inputs...)                                   \
1065 ({                                                                      \
1066         uint64_t ign_error_code;                                        \
1067         uint8_t vector;                                                 \
1068                                                                         \
1069         asm volatile(KVM_ASM_SAFE(insn)                                 \
1070                      : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code)     \
1071                      : inputs                                           \
1072                      : KVM_ASM_SAFE_CLOBBERS);                          \
1073         vector;                                                         \
1074 })
1075
1076 #define kvm_asm_safe_ec(insn, error_code, inputs...)                    \
1077 ({                                                                      \
1078         uint8_t vector;                                                 \
1079                                                                         \
1080         asm volatile(KVM_ASM_SAFE(insn)                                 \
1081                      : KVM_ASM_SAFE_OUTPUTS(vector, error_code)         \
1082                      : inputs                                           \
1083                      : KVM_ASM_SAFE_CLOBBERS);                          \
1084         vector;                                                         \
1085 })
1086
1087 static inline uint8_t rdmsr_safe(uint32_t msr, uint64_t *val)
1088 {
1089         uint64_t error_code;
1090         uint8_t vector;
1091         uint32_t a, d;
1092
1093         asm volatile(KVM_ASM_SAFE("rdmsr")
1094                      : "=a"(a), "=d"(d), KVM_ASM_SAFE_OUTPUTS(vector, error_code)
1095                      : "c"(msr)
1096                      : KVM_ASM_SAFE_CLOBBERS);
1097
1098         *val = (uint64_t)a | ((uint64_t)d << 32);
1099         return vector;
1100 }
1101
1102 static inline uint8_t wrmsr_safe(uint32_t msr, uint64_t val)
1103 {
1104         return kvm_asm_safe("wrmsr", "a"(val & -1u), "d"(val >> 32), "c"(msr));
1105 }
1106
1107 bool kvm_is_tdp_enabled(void);
1108
1109 uint64_t *__vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr,
1110                                     int *level);
1111 uint64_t *vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr);
1112
1113 uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2,
1114                        uint64_t a3);
1115 uint64_t __xen_hypercall(uint64_t nr, uint64_t a0, void *a1);
1116 void xen_hypercall(uint64_t nr, uint64_t a0, void *a1);
1117
1118 void __vm_xsave_require_permission(uint64_t xfeature, const char *name);
1119
1120 #define vm_xsave_require_permission(xfeature)   \
1121         __vm_xsave_require_permission(xfeature, #xfeature)
1122
1123 enum pg_level {
1124         PG_LEVEL_NONE,
1125         PG_LEVEL_4K,
1126         PG_LEVEL_2M,
1127         PG_LEVEL_1G,
1128         PG_LEVEL_512G,
1129         PG_LEVEL_NUM
1130 };
1131
1132 #define PG_LEVEL_SHIFT(_level) ((_level - 1) * 9 + 12)
1133 #define PG_LEVEL_SIZE(_level) (1ull << PG_LEVEL_SHIFT(_level))
1134
1135 #define PG_SIZE_4K PG_LEVEL_SIZE(PG_LEVEL_4K)
1136 #define PG_SIZE_2M PG_LEVEL_SIZE(PG_LEVEL_2M)
1137 #define PG_SIZE_1G PG_LEVEL_SIZE(PG_LEVEL_1G)
1138
1139 void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, int level);
1140 void virt_map_level(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
1141                     uint64_t nr_bytes, int level);
1142
1143 /*
1144  * Basic CPU control in CR0
1145  */
1146 #define X86_CR0_PE          (1UL<<0) /* Protection Enable */
1147 #define X86_CR0_MP          (1UL<<1) /* Monitor Coprocessor */
1148 #define X86_CR0_EM          (1UL<<2) /* Emulation */
1149 #define X86_CR0_TS          (1UL<<3) /* Task Switched */
1150 #define X86_CR0_ET          (1UL<<4) /* Extension Type */
1151 #define X86_CR0_NE          (1UL<<5) /* Numeric Error */
1152 #define X86_CR0_WP          (1UL<<16) /* Write Protect */
1153 #define X86_CR0_AM          (1UL<<18) /* Alignment Mask */
1154 #define X86_CR0_NW          (1UL<<29) /* Not Write-through */
1155 #define X86_CR0_CD          (1UL<<30) /* Cache Disable */
1156 #define X86_CR0_PG          (1UL<<31) /* Paging */
1157
1158 #define PFERR_PRESENT_BIT 0
1159 #define PFERR_WRITE_BIT 1
1160 #define PFERR_USER_BIT 2
1161 #define PFERR_RSVD_BIT 3
1162 #define PFERR_FETCH_BIT 4
1163 #define PFERR_PK_BIT 5
1164 #define PFERR_SGX_BIT 15
1165 #define PFERR_GUEST_FINAL_BIT 32
1166 #define PFERR_GUEST_PAGE_BIT 33
1167 #define PFERR_IMPLICIT_ACCESS_BIT 48
1168
1169 #define PFERR_PRESENT_MASK      BIT(PFERR_PRESENT_BIT)
1170 #define PFERR_WRITE_MASK        BIT(PFERR_WRITE_BIT)
1171 #define PFERR_USER_MASK         BIT(PFERR_USER_BIT)
1172 #define PFERR_RSVD_MASK         BIT(PFERR_RSVD_BIT)
1173 #define PFERR_FETCH_MASK        BIT(PFERR_FETCH_BIT)
1174 #define PFERR_PK_MASK           BIT(PFERR_PK_BIT)
1175 #define PFERR_SGX_MASK          BIT(PFERR_SGX_BIT)
1176 #define PFERR_GUEST_FINAL_MASK  BIT_ULL(PFERR_GUEST_FINAL_BIT)
1177 #define PFERR_GUEST_PAGE_MASK   BIT_ULL(PFERR_GUEST_PAGE_BIT)
1178 #define PFERR_IMPLICIT_ACCESS   BIT_ULL(PFERR_IMPLICIT_ACCESS_BIT)
1179
1180 #endif /* SELFTEST_KVM_PROCESSOR_H */