tools/perf/pmu-events/arch/s390/cf_z16/extended.json

   1 [
   2         {
   3                 "Unit": "CPU-M-CF",
   4                 "EventCode": "128",
   5                 "EventName": "L1D_RO_EXCL_WRITES",
   6                 "BriefDescription": "L1D Read-only Exclusive Writes",
   7                 "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
   8         },
   9         {
  10                 "Unit": "CPU-M-CF",
  11                 "EventCode": "129",
  12                 "EventName": "DTLB2_WRITES",
  13                 "BriefDescription": "DTLB2 Writes",
  14                 "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a replacement for what was provided for the DTLB on z13 and prior machines."
  15         },
  16         {
  17                 "Unit": "CPU-M-CF",
  18                 "EventCode": "130",
  19                 "EventName": "DTLB2_MISSES",
  20                 "BriefDescription": "DTLB2 Misses",
  21                 "PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on z13 and prior machines."
  22         },
  23         {
  24                 "Unit": "CPU-M-CF",
  25                 "EventCode": "131",
  26                 "EventName": "CRSTE_1MB_WRITES",
  27                 "BriefDescription": "One Megabyte CRSTE writes",
  28                 "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page."
  29         },
  30         {
  31                 "Unit": "CPU-M-CF",
  32                 "EventCode": "132",
  33                 "EventName": "DTLB2_GPAGE_WRITES",
  34                 "BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
  35                 "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB."
  36         },
  37         {
  38                 "Unit": "CPU-M-CF",
  39                 "EventCode": "134",
  40                 "EventName": "ITLB2_WRITES",
  41                 "BriefDescription": "ITLB2 Writes",
  42                 "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement for what was provided for the ITLB on z13 and prior machines."
  43         },
  44         {
  45                 "Unit": "CPU-M-CF",
  46                 "EventCode": "135",
  47                 "EventName": "ITLB2_MISSES",
  48                 "BriefDescription": "ITLB2 Misses",
  49                 "PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on z13 and prior machines."
  50         },
  51         {
  52                 "Unit": "CPU-M-CF",
  53                 "EventCode": "137",
  54                 "EventName": "TLB2_PTE_WRITES",
  55                 "BriefDescription": "TLB2 Page Table Entry Writes",
  56                 "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
  57         },
  58         {
  59                 "Unit": "CPU-M-CF",
  60                 "EventCode": "138",
  61                 "EventName": "TLB2_CRSTE_WRITES",
  62                 "BriefDescription": "TLB2 Combined Region and Segment Entry Writes",
  63                 "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
  64         },
  65         {
  66                 "Unit": "CPU-M-CF",
  67                 "EventCode": "139",
  68                 "EventName": "TLB2_ENGINES_BUSY",
  69                 "BriefDescription": "TLB2 Engines Busy",
  70                 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
  71         },
  72         {
  73                 "Unit": "CPU-M-CF",
  74                 "EventCode": "140",
  75                 "EventName": "TX_C_TEND",
  76                 "BriefDescription": "Completed TEND instructions in constrained TX mode",
  77                 "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode."
  78         },
  79         {
  80                 "Unit": "CPU-M-CF",
  81                 "EventCode": "141",
  82                 "EventName": "TX_NC_TEND",
  83                 "BriefDescription": "Completed TEND instructions in non-constrained TX mode",
  84                 "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode."
  85         },
  86         {
  87                 "Unit": "CPU-M-CF",
  88                 "EventCode": "143",
  89                 "EventName": "L1C_TLB2_MISSES",
  90                 "BriefDescription": "L1C TLB2 Misses",
  91                 "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress."
  92         },
  93         {
  94                 "Unit": "CPU-M-CF",
  95                 "EventCode": "145",
  96                 "EventName": "DCW_REQ",
  97                 "BriefDescription": "Directory Write Level 1 Data Cache from Cache",
  98                 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache."
  99         },
 100         {
 101                 "Unit": "CPU-M-CF",
 102                 "EventCode": "146",
 103                 "EventName": "DCW_REQ_IV",
 104                 "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Intervention",
 105                 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache with intervention."
 106         },
 107         {
 108                 "Unit": "CPU-M-CF",
 109                 "EventCode": "147",
 110                 "EventName": "DCW_REQ_CHIP_HIT",
 111                 "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Chip HP Hit",
 112                 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
 113         },
 114         {
 115                 "Unit": "CPU-M-CF",
 116                 "EventCode": "148",
 117                 "EventName": "DCW_REQ_DRAWER_HIT",
 118                 "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Drawer HP Hit",
 119                 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
 120         },
 121         {
 122                 "Unit": "CPU-M-CF",
 123                 "EventCode": "149",
 124                 "EventName": "DCW_ON_CHIP",
 125                 "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache",
 126                 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache."
 127         },
 128         {
 129                 "Unit": "CPU-M-CF",
 130                 "EventCode": "150",
 131                 "EventName": "DCW_ON_CHIP_IV",
 132                 "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Intervention",
 133                 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache with intervention."
 134         },
 135         {
 136                 "Unit": "CPU-M-CF",
 137                 "EventCode": "151",
 138                 "EventName": "DCW_ON_CHIP_CHIP_HIT",
 139                 "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Chip HP Hit",
 140                 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
 141         },
 142         {
 143                 "Unit": "CPU-M-CF",
 144                 "EventCode": "152",
 145                 "EventName": "DCW_ON_CHIP_DRAWER_HIT",
 146                 "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Drawer HP Hit",
 147                 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
 148         },
 149         {
 150                 "Unit": "CPU-M-CF",
 151                 "EventCode": "153",
 152                 "EventName": "DCW_ON_MODULE",
 153                 "BriefDescription": "Directory Write Level 1 Data Cache from On-Module Cache",
 154                 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Module Level-2 cache."
 155         },
 156         {
 157                 "Unit": "CPU-M-CF",
 158                 "EventCode": "154",
 159                 "EventName": "DCW_ON_DRAWER",
 160                 "BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer Cache",
 161                 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache."
 162         },
 163         {
 164                 "Unit": "CPU-M-CF",
 165                 "EventCode": "155",
 166                 "EventName": "DCW_OFF_DRAWER",
 167                 "BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer Cache",
 168                 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache."
 169         },
 170         {
 171                 "Unit": "CPU-M-CF",
 172                 "EventCode": "156",
 173                 "EventName": "DCW_ON_CHIP_MEMORY",
 174                 "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Memory",
 175                 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory."
 176         },
 177         {
 178                 "Unit": "CPU-M-CF",
 179                 "EventCode": "157",
 180                 "EventName": "DCW_ON_MODULE_MEMORY",
 181                 "BriefDescription": "Directory Write Level 1 Data Cache from On-Module Memory",
 182                 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Module memory."
 183         },
 184         {
 185                 "Unit": "CPU-M-CF",
 186                 "EventCode": "158",
 187                 "EventName": "DCW_ON_DRAWER_MEMORY",
 188                 "BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer Memory",
 189                 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory."
 190         },
 191         {
 192                 "Unit": "CPU-M-CF",
 193                 "EventCode": "159",
 194                 "EventName": "DCW_OFF_DRAWER_MEMORY",
 195                 "BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer Memory",
 196                 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory."
 197         },
 198         {
 199                 "Unit": "CPU-M-CF",
 200                 "EventCode": "160",
 201                 "EventName": "IDCW_ON_MODULE_IV",
 202                 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Intervention",
 203                 "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache with intervention."
 204         },
 205         {
 206                 "Unit": "CPU-M-CF",
 207                 "EventCode": "161",
 208                 "EventName": "IDCW_ON_MODULE_CHIP_HIT",
 209                 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Chip Hit",
 210                 "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using chip horizontal persistence, Chip-HP hit."
 211         },
 212         {
 213                 "Unit": "CPU-M-CF",
 214                 "EventCode": "162",
 215                 "EventName": "IDCW_ON_MODULE_DRAWER_HIT",
 216                 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Drawer Hit",
 217                 "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
 218         },
 219         {
 220                 "Unit": "CPU-M-CF",
 221                 "EventCode": "163",
 222                 "EventName": "IDCW_ON_DRAWER_IV",
 223                 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Intervention",
 224                 "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache with intervention."
 225         },
 226         {
 227                 "Unit": "CPU-M-CF",
 228                 "EventCode": "164",
 229                 "EventName": "IDCW_ON_DRAWER_CHIP_HIT",
 230                 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Chip Hit",
 231                 "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit."
 232         },
 233         {
 234                 "Unit": "CPU-M-CF",
 235                 "EventCode": "165",
 236                 "EventName": "IDCW_ON_DRAWER_DRAWER_HIT",
 237                 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Drawer Hit",
 238                 "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
 239         },
 240         {
 241                 "Unit": "CPU-M-CF",
 242                 "EventCode": "166",
 243                 "EventName": "IDCW_OFF_DRAWER_IV",
 244                 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Intervention",
 245                 "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache with intervention."
 246         },
 247         {
 248                 "Unit": "CPU-M-CF",
 249                 "EventCode": "167",
 250                 "EventName": "IDCW_OFF_DRAWER_CHIP_HIT",
 251                 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Chip Hit",
 252                 "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit."
 253         },
 254         {
 255                 "Unit": "CPU-M-CF",
 256                 "EventCode": "168",
 257                 "EventName": "IDCW_OFF_DRAWER_DRAWER_HIT",
 258                 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Drawer Hit",
 259                 "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
 260         },
 261         {
 262                 "Unit": "CPU-M-CF",
 263                 "EventCode": "169",
 264                 "EventName": "ICW_REQ",
 265                 "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache",
 266                 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced the requestors Level-2 cache."
 267         },
 268         {
 269                 "Unit": "CPU-M-CF",
 270                 "EventCode": "170",
 271                 "EventName": "ICW_REQ_IV",
 272                 "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Intervention",
 273                 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention."
 274         },
 275         {
 276                 "Unit": "CPU-M-CF",
 277                 "EventCode": "171",
 278                 "EventName": "ICW_REQ_CHIP_HIT",
 279                 "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Chip HP Hit",
 280                 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using chip level horizontal persistence, Chip-HP hit."
 281         },
 282         {
 283                 "Unit": "CPU-M-CF",
 284                 "EventCode": "172",
 285                 "EventName": "ICW_REQ_DRAWER_HIT",
 286                 "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Drawer HP Hit",
 287                 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestor’s Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
 288         },
 289         {
 290                 "Unit": "CPU-M-CF",
 291                 "EventCode": "173",
 292                 "EventName": "ICW_ON_CHIP",
 293                 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache",
 294                 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache."
 295         },
 296         {
 297                 "Unit": "CPU-M-CF",
 298                 "EventCode": "174",
 299                 "EventName": "ICW_ON_CHIP_IV",
 300                 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Intervention",
 301                 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Chip Level-2 cache with intervention."
 302         },
 303         {
 304                 "Unit": "CPU-M-CF",
 305                 "EventCode": "175",
 306                 "EventName": "ICW_ON_CHIP_CHIP_HIT",
 307                 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Chip HP Hit",
 308                 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using chip level horizontal persistence, Chip-HP hit."
 309         },
 310         {
 311                 "Unit": "CPU-M-CF",
 312                 "EventCode": "176",
 313                 "EventName": "ICW_ON_CHIP_DRAWER_HIT",
 314                 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Drawer HP Hit",
 315                 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip level 2 cache using drawer level horizontal persistence, Drawer-HP hit."
 316         },
 317         {
 318                 "Unit": "CPU-M-CF",
 319                 "EventCode": "177",
 320                 "EventName": "ICW_ON_MODULE",
 321                 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module Cache",
 322                 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache."
 323         },
 324         {
 325                 "Unit": "CPU-M-CF",
 326                 "EventCode": "178",
 327                 "EventName": "ICW_ON_DRAWER",
 328                 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer Cache",
 329                 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Drawer Level-2 cache."
 330         },
 331         {
 332                 "Unit": "CPU-M-CF",
 333                 "EventCode": "179",
 334                 "EventName": "ICW_OFF_DRAWER",
 335                 "BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer Cache",
 336                 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an Off-Drawer Level-2 cache."
 337         },
 338         {
 339                 "Unit": "CPU-M-CF",
 340                 "EventCode": "180",
 341                 "EventName": "ICW_ON_CHIP_MEMORY",
 342                 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Memory",
 343                 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory."
 344         },
 345         {
 346                 "Unit": "CPU-M-CF",
 347                 "EventCode": "181",
 348                 "EventName": "ICW_ON_MODULE_MEMORY",
 349                 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module Memory",
 350                 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Module memory."
 351         },
 352         {
 353                 "Unit": "CPU-M-CF",
 354                 "EventCode": "182",
 355                 "EventName": "ICW_ON_DRAWER_MEMORY",
 356                 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer Memory",
 357                 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory."
 358         },
 359         {
 360                 "Unit": "CPU-M-CF",
 361                 "EventCode": "183",
 362                 "EventName": "ICW_OFF_DRAWER_MEMORY",
 363                 "BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer Memory",
 364                 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory."
 365         },
 366         {
 367                 "Unit": "CPU-M-CF",
 368                 "EventCode": "224",
 369                 "EventName": "BCD_DFP_EXECUTION_SLOTS",
 370                 "BriefDescription": "Binary Coded Decimal to Decimal Floating Point conversions",
 371                 "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT."
 372         },
 373         {
 374                 "Unit": "CPU-M-CF",
 375                 "EventCode": "225",
 376                 "EventName": "VX_BCD_EXECUTION_SLOTS",
 377                 "BriefDescription": "Count finished vector arithmetic Binary Coded Decimal instructions",
 378                 "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMP, VMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOP, VCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVD, VCVDG."
 379         },
 380         {
 381                 "Unit": "CPU-M-CF",
 382                 "EventCode": "226",
 383                 "EventName": "DECIMAL_INSTRUCTIONS",
 384                 "BriefDescription": "Decimal instruction dispatched",
 385                 "PublicDescription": "Decimal instruction dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP."
 386         },
 387         {
 388                 "Unit": "CPU-M-CF",
 389                 "EventCode": "232",
 390                 "EventName": "LAST_HOST_TRANSLATIONS",
 391                 "BriefDescription": "Last host translation done",
 392                 "PublicDescription": "Last Host Translation done"
 393         },
 394         {
 395                 "Unit": "CPU-M-CF",
 396                 "EventCode": "244",
 397                 "EventName": "TX_NC_TABORT",
 398                 "BriefDescription": "Aborted transactions in unconstrained TX mode",
 399                 "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode."
 400         },
 401         {
 402                 "Unit": "CPU-M-CF",
 403                 "EventCode": "245",
 404                 "EventName": "TX_C_TABORT_NO_SPECIAL",
 405                 "BriefDescription": "Aborted transactions in constrained TX mode",
 406                 "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete."
 407         },
 408         {
 409                 "Unit": "CPU-M-CF",
 410                 "EventCode": "246",
 411                 "EventName": "TX_C_TABORT_SPECIAL",
 412                 "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
 413                 "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete."
 414         },
 415         {
 416                 "Unit": "CPU-M-CF",
 417                 "EventCode": "248",
 418                 "EventName": "DFLT_ACCESS",
 419                 "BriefDescription": "Cycles CPU spent obtaining access to Deflate unit",
 420                 "PublicDescription": "Cycles CPU spent obtaining access to Deflate unit"
 421         },
 422         {
 423                 "Unit": "CPU-M-CF",
 424                 "EventCode": "253",
 425                 "EventName": "DFLT_CYCLES",
 426                 "BriefDescription": "Cycles CPU is using Deflate unit",
 427                 "PublicDescription": "Cycles CPU is using Deflate unit"
 428         },
 429         {
 430                 "Unit": "CPU-M-CF",
 431                 "EventCode": "256",
 432                 "EventName": "SORTL",
 433                 "BriefDescription": "Count SORTL instructions",
 434                 "PublicDescription": "Increments by one for every SORT LISTS instruction executed."
 435         },
 436         {
 437                 "Unit": "CPU-M-CF",
 438                 "EventCode": "265",
 439                 "EventName": "DFLT_CC",
 440                 "BriefDescription": "Increments DEFLATE CONVERSION CALL",
 441                 "PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed."
 442         },
 443         {
 444                 "Unit": "CPU-M-CF",
 445                 "EventCode": "266",
 446                 "EventName": "DFLT_CCFINISH",
 447                 "BriefDescription": "Increments completed DEFLATE CONVERSION CALL",
 448                 "PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2."
 449         },
 450         {
 451                 "Unit": "CPU-M-CF",
 452                 "EventCode": "267",
 453                 "EventName": "NNPA_INVOCATIONS",
 454                 "BriefDescription": "NNPA Total invocations",
 455                 "PublicDescription": "Increments by one for every Neural Network Processing Assist instruction executed."
 456         },
 457         {
 458                 "Unit": "CPU-M-CF",
 459                 "EventCode": "268",
 460                 "EventName": "NNPA_COMPLETIONS",
 461                 "BriefDescription": "NNPA Total completions",
 462                 "PublicDescription": "Increments by one for every Neural Network Processing Assist instruction executed that ended in Condition Codes 0, 1 or 2."
 463         },
 464         {
 465                 "Unit": "CPU-M-CF",
 466                 "EventCode": "269",
 467                 "EventName": "NNPA_WAIT_LOCK",
 468                 "BriefDescription": "Cycles spent obtaining NNPA lock",
 469                 "PublicDescription": "Cycles CPU spent obtaining access to IBM Z Integrated Accelerator for AI."
 470         },
 471         {
 472                 "Unit": "CPU-M-CF",
 473                 "EventCode": "270",
 474                 "EventName": "NNPA_HOLD_LOCK",
 475                 "BriefDescription": "Cycles spent holding NNPA lock",
 476                 "PublicDescription": "Cycles CPU is using IBM Z Integrated Accelerator for AI."
 477         },
 478         {
 479                 "Unit": "CPU-M-CF",
 480                 "EventCode": "448",
 481                 "EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
 482                 "BriefDescription": "Cycle count with one thread active",
 483                 "PublicDescription": "Cycle count with one thread active"
 484         },
 485         {
 486                 "Unit": "CPU-M-CF",
 487                 "EventCode": "449",
 488                 "EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
 489                 "BriefDescription": "Cycle count with two threads active",
 490                 "PublicDescription": "Cycle count with two threads active"
 491         }
 492 ]