3 "ArchStdEvent": "L1I_CACHE_REFILL"
6 "ArchStdEvent": "L1I_TLB_REFILL"
9 "ArchStdEvent": "L1D_CACHE_REFILL"
12 "ArchStdEvent": "L1D_CACHE"
15 "ArchStdEvent": "L1D_TLB_REFILL"
18 "ArchStdEvent": "L1I_CACHE"
21 "ArchStdEvent": "L1D_CACHE_WB"
24 "ArchStdEvent": "L2D_CACHE"
27 "ArchStdEvent": "L2D_CACHE_REFILL"
30 "ArchStdEvent": "L2D_CACHE_WB"
33 "ArchStdEvent": "L2D_CACHE_ALLOCATE"
36 "ArchStdEvent": "L1D_TLB"
39 "ArchStdEvent": "L1I_TLB"
42 "ArchStdEvent": "L3D_CACHE_ALLOCATE"
45 "ArchStdEvent": "L3D_CACHE_REFILL"
48 "ArchStdEvent": "L3D_CACHE"
51 "ArchStdEvent": "L2D_TLB_REFILL"
54 "ArchStdEvent": "L2D_TLB"
57 "ArchStdEvent": "DTLB_WALK"
60 "ArchStdEvent": "ITLB_WALK"
63 "ArchStdEvent": "LL_CACHE_RD"
66 "ArchStdEvent": "LL_CACHE_MISS_RD"
69 "ArchStdEvent": "L1D_CACHE_LMISS_RD"
72 "ArchStdEvent": "L1D_CACHE_RD"
75 "ArchStdEvent": "L1D_CACHE_WR"
78 "ArchStdEvent": "L1D_CACHE_REFILL_RD"
81 "ArchStdEvent": "L1D_CACHE_REFILL_WR"
84 "ArchStdEvent": "L1D_CACHE_REFILL_INNER"
87 "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
90 "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
93 "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
96 "ArchStdEvent": "L1D_CACHE_INVAL"
99 "ArchStdEvent": "L1D_TLB_REFILL_RD"
102 "ArchStdEvent": "L1D_TLB_REFILL_WR"
105 "ArchStdEvent": "L1D_TLB_RD"
108 "ArchStdEvent": "L1D_TLB_WR"
111 "ArchStdEvent": "L2D_CACHE_RD"
114 "ArchStdEvent": "L2D_CACHE_WR"
117 "ArchStdEvent": "L2D_CACHE_REFILL_RD"
120 "ArchStdEvent": "L2D_CACHE_REFILL_WR"
123 "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
126 "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
129 "ArchStdEvent": "L2D_CACHE_INVAL"
132 "ArchStdEvent": "L2D_TLB_REFILL_RD"
135 "ArchStdEvent": "L2D_TLB_REFILL_WR"
138 "ArchStdEvent": "L2D_TLB_RD"
141 "ArchStdEvent": "L2D_TLB_WR"
144 "ArchStdEvent": "L3D_CACHE_RD"
147 "ArchStdEvent": "L1I_CACHE_LMISS"
150 "ArchStdEvent": "L2D_CACHE_LMISS_RD"
153 "ArchStdEvent": "L3D_CACHE_LMISS_RD"