1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015 Josh Poimboeuf <jpoimboe@redhat.com>
9 #define unlikely(cond) (cond)
11 #include "../../../arch/x86/lib/inat.c"
12 #include "../../../arch/x86/lib/insn.c"
14 #define CONFIG_64BIT 1
17 #include <asm/orc_types.h>
18 #include <objtool/check.h>
19 #include <objtool/elf.h>
20 #include <objtool/arch.h>
21 #include <objtool/warn.h>
22 #include <objtool/endianness.h>
23 #include <objtool/builtin.h>
26 int arch_ftrace_match(char *name)
28 return !strcmp(name, "__fentry__");
31 static int is_x86_64(const struct elf *elf)
33 switch (elf->ehdr.e_machine) {
39 WARN("unexpected ELF machine type %d", elf->ehdr.e_machine);
44 bool arch_callee_saved_reg(unsigned char reg)
71 unsigned long arch_dest_reloc_offset(int addend)
76 unsigned long arch_jump_destination(struct instruction *insn)
78 return insn->offset + insn->len + insn->immediate;
81 bool arch_pc_relative_reloc(struct reloc *reloc)
84 * All relocation types where P (the address of the target)
85 * is included in the computation.
87 switch (reloc_type(reloc)) {
94 case R_X86_64_GOTPC32:
95 case R_X86_64_GOTPCREL:
106 if (!(op = calloc(1, sizeof(*op)))) \
108 else for (*ops_list = op, ops_list = &op->next; op; op = NULL)
111 * Helpers to decode ModRM/SIB:
113 * r/m| AX CX DX BX | SP | BP | SI DI |
114 * | R8 R9 R10 R11 | R12 | R13 | R14 R15 |
115 * Mod+----------------+-----+-----+---------+
116 * 00 | [r/m] |[SIB]|[IP+]| [r/m] |
117 * 01 | [r/m + d8] |[S+d]| [r/m + d8] |
118 * 10 | [r/m + d32] |[S+D]| [r/m + d32] |
122 #define mod_is_mem() (modrm_mod != 3)
123 #define mod_is_reg() (modrm_mod == 3)
125 #define is_RIP() ((modrm_rm & 7) == CFI_BP && modrm_mod == 0)
126 #define have_SIB() ((modrm_rm & 7) == CFI_SP && mod_is_mem())
128 #define rm_is(reg) (have_SIB() ? \
129 sib_base == (reg) && sib_index == CFI_SP : \
132 #define rm_is_mem(reg) (mod_is_mem() && !is_RIP() && rm_is(reg))
133 #define rm_is_reg(reg) (mod_is_reg() && modrm_rm == (reg))
135 static bool has_notrack_prefix(struct insn *insn)
139 for (i = 0; i < insn->prefixes.nbytes; i++) {
140 if (insn->prefixes.bytes[i] == 0x3e)
147 int arch_decode_instruction(struct objtool_file *file, const struct section *sec,
148 unsigned long offset, unsigned int maxlen,
149 struct instruction *insn)
151 struct stack_op **ops_list = &insn->stack_ops;
152 const struct elf *elf = file->elf;
155 unsigned char op1, op2, op3, prefix,
156 rex = 0, rex_b = 0, rex_r = 0, rex_w = 0, rex_x = 0,
157 modrm = 0, modrm_mod = 0, modrm_rm = 0, modrm_reg = 0,
158 sib = 0, /* sib_scale = 0, */ sib_index = 0, sib_base = 0;
159 struct stack_op *op = NULL;
163 x86_64 = is_x86_64(elf);
167 ret = insn_decode(&ins, sec->data->d_buf + offset, maxlen,
168 x86_64 ? INSN_MODE_64 : INSN_MODE_32);
170 WARN("can't decode instruction at %s:0x%lx", sec->name, offset);
174 insn->len = ins.length;
175 insn->type = INSN_OTHER;
177 if (ins.vex_prefix.nbytes)
180 prefix = ins.prefixes.bytes[0];
182 op1 = ins.opcode.bytes[0];
183 op2 = ins.opcode.bytes[1];
184 op3 = ins.opcode.bytes[2];
186 if (ins.rex_prefix.nbytes) {
187 rex = ins.rex_prefix.bytes[0];
188 rex_w = X86_REX_W(rex) >> 3;
189 rex_r = X86_REX_R(rex) >> 2;
190 rex_x = X86_REX_X(rex) >> 1;
191 rex_b = X86_REX_B(rex);
194 if (ins.modrm.nbytes) {
195 modrm = ins.modrm.bytes[0];
196 modrm_mod = X86_MODRM_MOD(modrm);
197 modrm_reg = X86_MODRM_REG(modrm) + 8*rex_r;
198 modrm_rm = X86_MODRM_RM(modrm) + 8*rex_b;
201 if (ins.sib.nbytes) {
202 sib = ins.sib.bytes[0];
203 /* sib_scale = X86_SIB_SCALE(sib); */
204 sib_index = X86_SIB_INDEX(sib) + 8*rex_x;
205 sib_base = X86_SIB_BASE(sib) + 8*rex_b;
212 if (rex_w && rm_is_reg(CFI_SP)) {
214 /* add/sub reg, %rsp */
216 op->src.type = OP_SRC_ADD;
217 op->src.reg = modrm_reg;
218 op->dest.type = OP_DEST_REG;
219 op->dest.reg = CFI_SP;
228 op->src.type = OP_SRC_REG;
229 op->src.reg = (op1 & 0x7) + 8*rex_b;
230 op->dest.type = OP_DEST_PUSH;
239 op->src.type = OP_SRC_POP;
240 op->dest.type = OP_DEST_REG;
241 op->dest.reg = (op1 & 0x7) + 8*rex_b;
250 op->src.type = OP_SRC_CONST;
251 op->dest.type = OP_DEST_PUSH;
256 insn->type = INSN_JUMP_CONDITIONAL;
261 * 1000 00sw : mod OP r/m : immediate
263 * s - sign extend immediate
266 * OP: 000 ADD 100 AND
276 /* %rsp target only */
277 if (!rm_is_reg(CFI_SP))
280 imm = ins.immediate.value;
281 if (op1 & 2) { /* sign extend */
282 if (op1 & 1) { /* imm32 */
284 imm = (s64)imm >> 32;
287 imm = (s64)imm >> 56;
291 switch (modrm_reg & 7) {
296 /* add/sub imm, %rsp */
298 op->src.type = OP_SRC_ADD;
299 op->src.reg = CFI_SP;
300 op->src.offset = imm;
301 op->dest.type = OP_DEST_REG;
302 op->dest.reg = CFI_SP;
309 op->src.type = OP_SRC_AND;
310 op->src.reg = CFI_SP;
311 op->src.offset = ins.immediate.value;
312 op->dest.type = OP_DEST_REG;
313 op->dest.reg = CFI_SP;
328 if (modrm_reg == CFI_SP) {
333 op->src.type = OP_SRC_REG;
334 op->src.reg = CFI_SP;
335 op->dest.type = OP_DEST_REG;
336 op->dest.reg = modrm_rm;
341 /* skip RIP relative displacement */
345 /* skip nontrivial SIB */
348 if (sib_index != CFI_SP)
352 /* mov %rsp, disp(%reg) */
354 op->src.type = OP_SRC_REG;
355 op->src.reg = CFI_SP;
356 op->dest.type = OP_DEST_REG_INDIRECT;
357 op->dest.reg = modrm_rm;
358 op->dest.offset = ins.displacement.value;
366 if (rm_is_reg(CFI_SP)) {
370 op->src.type = OP_SRC_REG;
371 op->src.reg = modrm_reg;
372 op->dest.type = OP_DEST_REG;
373 op->dest.reg = CFI_SP;
383 if (rm_is_mem(CFI_BP)) {
385 /* mov reg, disp(%rbp) */
387 op->src.type = OP_SRC_REG;
388 op->src.reg = modrm_reg;
389 op->dest.type = OP_DEST_REG_INDIRECT;
390 op->dest.reg = CFI_BP;
391 op->dest.offset = ins.displacement.value;
396 if (rm_is_mem(CFI_SP)) {
398 /* mov reg, disp(%rsp) */
400 op->src.type = OP_SRC_REG;
401 op->src.reg = modrm_reg;
402 op->dest.type = OP_DEST_REG_INDIRECT;
403 op->dest.reg = CFI_SP;
404 op->dest.offset = ins.displacement.value;
415 if (rm_is_mem(CFI_BP)) {
417 /* mov disp(%rbp), reg */
419 op->src.type = OP_SRC_REG_INDIRECT;
420 op->src.reg = CFI_BP;
421 op->src.offset = ins.displacement.value;
422 op->dest.type = OP_DEST_REG;
423 op->dest.reg = modrm_reg;
428 if (rm_is_mem(CFI_SP)) {
430 /* mov disp(%rsp), reg */
432 op->src.type = OP_SRC_REG_INDIRECT;
433 op->src.reg = CFI_SP;
434 op->src.offset = ins.displacement.value;
435 op->dest.type = OP_DEST_REG;
436 op->dest.reg = modrm_reg;
445 WARN("invalid LEA encoding at %s:0x%lx", sec->name, offset);
449 /* skip non 64bit ops */
453 /* skip RIP relative displacement */
457 /* skip nontrivial SIB */
460 if (sib_index != CFI_SP)
464 /* lea disp(%src), %dst */
466 op->src.offset = ins.displacement.value;
467 if (!op->src.offset) {
468 /* lea (%src), %dst */
469 op->src.type = OP_SRC_REG;
471 /* lea disp(%src), %dst */
472 op->src.type = OP_SRC_ADD;
474 op->src.reg = modrm_rm;
475 op->dest.type = OP_DEST_REG;
476 op->dest.reg = modrm_reg;
483 op->src.type = OP_SRC_POP;
484 op->dest.type = OP_DEST_MEM;
489 insn->type = INSN_NOP;
495 op->src.type = OP_SRC_CONST;
496 op->dest.type = OP_DEST_PUSHF;
503 op->src.type = OP_SRC_POPF;
504 op->dest.type = OP_DEST_MEM;
513 insn->type = INSN_CLAC;
514 else if (modrm == 0xcb)
515 insn->type = INSN_STAC;
517 } else if (op2 >= 0x80 && op2 <= 0x8f) {
519 insn->type = INSN_JUMP_CONDITIONAL;
521 } else if (op2 == 0x05 || op2 == 0x07 || op2 == 0x34 ||
524 /* sysenter, sysret */
525 insn->type = INSN_CONTEXT_SWITCH;
527 } else if (op2 == 0x0b || op2 == 0xb9) {
530 insn->type = INSN_BUG;
532 } else if (op2 == 0x0d || op2 == 0x1f) {
535 insn->type = INSN_NOP;
537 } else if (op2 == 0x1e) {
539 if (prefix == 0xf3 && (modrm == 0xfa || modrm == 0xfb))
540 insn->type = INSN_ENDBR;
543 } else if (op2 == 0x38 && op3 == 0xf8) {
544 if (ins.prefixes.nbytes == 1 &&
545 ins.prefixes.bytes[0] == 0xf2) {
546 /* ENQCMD cannot be used in the kernel. */
547 WARN("ENQCMD instruction at %s:%lx", sec->name,
551 } else if (op2 == 0xa0 || op2 == 0xa8) {
555 op->src.type = OP_SRC_CONST;
556 op->dest.type = OP_DEST_PUSH;
559 } else if (op2 == 0xa1 || op2 == 0xa9) {
563 op->src.type = OP_SRC_POP;
564 op->dest.type = OP_DEST_MEM;
579 op->src.type = OP_SRC_REG;
580 op->src.reg = CFI_BP;
581 op->dest.type = OP_DEST_REG;
582 op->dest.reg = CFI_SP;
585 op->src.type = OP_SRC_POP;
586 op->dest.type = OP_DEST_REG;
587 op->dest.reg = CFI_BP;
593 insn->type = INSN_TRAP;
598 insn->type = INSN_JUMP_CONDITIONAL;
603 insn->type = INSN_JUMP_UNCONDITIONAL;
608 insn->type = INSN_RETURN;
611 case 0xc7: /* mov imm, r/m */
615 if (ins.length == 3+4+4 && !strncmp(sec->name, ".init.text", 10)) {
616 struct reloc *immr, *disp;
620 immr = find_reloc_by_dest(elf, (void *)sec, offset+3);
621 disp = find_reloc_by_dest(elf, (void *)sec, offset+7);
623 if (!immr || strcmp(immr->sym->name, "pv_ops"))
626 idx = (reloc_addend(immr) + 8) / sizeof(void *);
629 if (disp->sym->type == STT_SECTION)
630 func = find_symbol_by_offset(disp->sym->sec, reloc_addend(disp));
632 WARN("no func for pv_ops[]");
636 objtool_pv_add(file, idx, func);
641 case 0xcf: /* iret */
643 * Handle sync_core(), which has an IRET to self.
644 * All other IRET are in STT_NONE entry code.
646 sym = find_symbol_containing(sec, offset);
647 if (sym && sym->type == STT_FUNC) {
650 op->src.type = OP_SRC_ADD;
651 op->src.reg = CFI_SP;
652 op->src.offset = 5*8;
653 op->dest.type = OP_DEST_REG;
654 op->dest.reg = CFI_SP;
661 case 0xca: /* retf */
662 case 0xcb: /* retf */
663 insn->type = INSN_CONTEXT_SWITCH;
666 case 0xe0: /* loopne */
667 case 0xe1: /* loope */
668 case 0xe2: /* loop */
669 insn->type = INSN_JUMP_CONDITIONAL;
673 insn->type = INSN_CALL;
675 * For the impact on the stack, a CALL behaves like
676 * a PUSH of an immediate value (the return address).
679 op->src.type = OP_SRC_CONST;
680 op->dest.type = OP_DEST_PUSH;
685 insn->type = INSN_CLD;
689 insn->type = INSN_STD;
693 if (modrm_reg == 2 || modrm_reg == 3) {
695 insn->type = INSN_CALL_DYNAMIC;
696 if (has_notrack_prefix(&ins))
697 WARN("notrack prefix found at %s:0x%lx", sec->name, offset);
699 } else if (modrm_reg == 4) {
701 insn->type = INSN_JUMP_DYNAMIC;
702 if (has_notrack_prefix(&ins))
703 WARN("notrack prefix found at %s:0x%lx", sec->name, offset);
705 } else if (modrm_reg == 5) {
708 insn->type = INSN_CONTEXT_SWITCH;
710 } else if (modrm_reg == 6) {
714 op->src.type = OP_SRC_CONST;
715 op->dest.type = OP_DEST_PUSH;
725 insn->immediate = ins.immediate.nbytes ? ins.immediate.value : 0;
730 void arch_initial_func_cfi_state(struct cfi_init_state *state)
734 for (i = 0; i < CFI_NUM_REGS; i++) {
735 state->regs[i].base = CFI_UNDEFINED;
736 state->regs[i].offset = 0;
739 /* initial CFA (call frame address) */
740 state->cfa.base = CFI_SP;
741 state->cfa.offset = 8;
743 /* initial RA (return address) */
744 state->regs[CFI_RA].base = CFI_CFA;
745 state->regs[CFI_RA].offset = -8;
748 const char *arch_nop_insn(int len)
750 static const char nops[5][5] = {
758 if (len < 1 || len > 5) {
759 WARN("invalid NOP size: %d\n", len);
766 #define BYTE_RET 0xC3
768 const char *arch_ret_insn(int len)
770 static const char ret[5][5] = {
773 { BYTE_RET, 0xcc, BYTES_NOP1 },
774 { BYTE_RET, 0xcc, BYTES_NOP2 },
775 { BYTE_RET, 0xcc, BYTES_NOP3 },
778 if (len < 1 || len > 5) {
779 WARN("invalid RET size: %d\n", len);
786 int arch_decode_hint_reg(u8 sp_reg, int *base)
789 case ORC_REG_UNDEFINED:
790 *base = CFI_UNDEFINED;
798 case ORC_REG_SP_INDIRECT:
799 *base = CFI_SP_INDIRECT;
820 bool arch_is_retpoline(struct symbol *sym)
822 return !strncmp(sym->name, "__x86_indirect_", 15);
825 bool arch_is_rethunk(struct symbol *sym)
827 return !strcmp(sym->name, "__x86_return_thunk");
830 bool arch_is_embedded_insn(struct symbol *sym)
832 return !strcmp(sym->name, "retbleed_return_thunk") ||
833 !strcmp(sym->name, "srso_safe_ret");