1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
15 #define __packed __attribute((packed))
20 #define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config))
21 #define MAX_TEMPBUF_LEN 32
24 #define IBR_HDR_ECC_DEFAULT 0x00
25 #define IBR_HDR_ECC_FORCED_HAMMING 0x01
26 #define IBR_HDR_ECC_FORCED_RS 0x02
27 #define IBR_HDR_ECC_DISABLED 0x03
29 /* Boot Type - block ID */
30 #define IBR_HDR_I2C_ID 0x4D
31 #define IBR_HDR_SPI_ID 0x5A
32 #define IBR_HDR_NAND_ID 0x8B
33 #define IBR_HDR_SATA_ID 0x78
34 #define IBR_HDR_PEX_ID 0x9C
35 #define IBR_HDR_UART_ID 0x69
36 #define IBR_HDR_SDIO_ID 0xAE
37 #define IBR_DEF_ATTRIB 0x00
39 /* Structure of the main header, version 0 (Kirkwood, Dove) */
41 uint8_t blockid; /* 0x0 */
42 uint8_t nandeccmode; /* 0x1 */
43 uint16_t nandpagesize; /* 0x2-0x3 */
44 uint32_t blocksize; /* 0x4-0x7 */
45 uint32_t rsvd1; /* 0x8-0xB */
46 uint32_t srcaddr; /* 0xC-0xF */
47 uint32_t destaddr; /* 0x10-0x13 */
48 uint32_t execaddr; /* 0x14-0x17 */
49 uint8_t satapiomode; /* 0x18 */
50 uint8_t rsvd3; /* 0x19 */
51 uint16_t ddrinitdelay; /* 0x1A-0x1B */
52 uint16_t rsvd2; /* 0x1C-0x1D */
53 uint8_t ext; /* 0x1E */
54 uint8_t checksum; /* 0x1F */
57 struct ext_hdr_v0_reg {
62 #define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
66 uint8_t reserved[0x20 - sizeof(uint32_t)];
67 struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
72 /* Structure of the main header, version 1 (Armada 370/38x/XP) */
74 uint8_t blockid; /* 0x0 */
75 uint8_t flags; /* 0x1 */
76 uint16_t reserved2; /* 0x2-0x3 */
77 uint32_t blocksize; /* 0x4-0x7 */
78 uint8_t version; /* 0x8 */
79 uint8_t headersz_msb; /* 0x9 */
80 uint16_t headersz_lsb; /* 0xA-0xB */
81 uint32_t srcaddr; /* 0xC-0xF */
82 uint32_t destaddr; /* 0x10-0x13 */
83 uint32_t execaddr; /* 0x14-0x17 */
84 uint8_t options; /* 0x18 */
85 uint8_t nandblocksize; /* 0x19 */
86 uint8_t nandbadblklocation; /* 0x1A */
87 uint8_t reserved4; /* 0x1B */
88 uint16_t reserved5; /* 0x1C-0x1D */
89 uint8_t ext; /* 0x1E */
90 uint8_t checksum; /* 0x1F */
96 #define MAIN_HDR_V1_OPT_BAUD_DEFAULT 0
97 #define MAIN_HDR_V1_OPT_BAUD_2400 0x1
98 #define MAIN_HDR_V1_OPT_BAUD_4800 0x2
99 #define MAIN_HDR_V1_OPT_BAUD_9600 0x3
100 #define MAIN_HDR_V1_OPT_BAUD_19200 0x4
101 #define MAIN_HDR_V1_OPT_BAUD_38400 0x5
102 #define MAIN_HDR_V1_OPT_BAUD_57600 0x6
103 #define MAIN_HDR_V1_OPT_BAUD_115200 0x7
106 * Header for the optional headers, version 1 (Armada 370, Armada XP)
110 uint8_t headersz_msb;
111 uint16_t headersz_lsb;
116 * Public Key data in DER format
118 struct pubkey_der_v1 {
123 * Signature (RSA 2048)
130 * Structure of secure header (Armada 38x)
132 struct secure_hdr_v1 {
133 uint8_t headertype; /* 0x0 */
134 uint8_t headersz_msb; /* 0x1 */
135 uint16_t headersz_lsb; /* 0x2 - 0x3 */
136 uint32_t reserved1; /* 0x4 - 0x7 */
137 struct pubkey_der_v1 kak; /* 0x8 - 0x213 */
138 uint8_t jtag_delay; /* 0x214 */
139 uint8_t reserved2; /* 0x215 */
140 uint16_t reserved3; /* 0x216 - 0x217 */
141 uint32_t boxid; /* 0x218 - 0x21B */
142 uint32_t flashid; /* 0x21C - 0x21F */
143 struct sig_v1 hdrsig; /* 0x220 - 0x31F */
144 struct sig_v1 imgsig; /* 0x320 - 0x41F */
145 struct pubkey_der_v1 csk[16]; /* 0x420 - 0x24DF */
146 struct sig_v1 csksig; /* 0x24E0 - 0x25DF */
147 uint8_t next; /* 0x25E0 */
148 uint8_t reserved4; /* 0x25E1 */
149 uint16_t reserved5; /* 0x25E2 - 0x25E3 */
153 * Structure of register set
155 struct register_set_hdr_v1 {
156 uint8_t headertype; /* 0x0 */
157 uint8_t headersz_msb; /* 0x1 */
158 uint16_t headersz_lsb; /* 0x2 - 0x3 */
161 uint32_t address; /* 0x4+8*N - 0x7+8*N */
162 uint32_t value; /* 0x8+8*N - 0xB+8*N */
165 uint8_t next; /* 0xC+8*N */
166 uint8_t delay; /* 0xD+8*N */
167 uint16_t reserved; /* 0xE+8*N - 0xF+8*N */
168 } __packed last_entry;
173 * Value 0 in register_set_hdr_v1 delay field is special.
174 * Instead of delay it setup SDRAM Controller.
176 #define REGISTER_SET_HDR_OPT_DELAY_SDRAM_SETUP 0
177 #define REGISTER_SET_HDR_OPT_DELAY_MS(val) ((val) ?: 1)
180 * Various values for the opt_hdr_v1->headertype field, describing the
181 * different types of optional headers. The "secure" header contains
182 * informations related to secure boot (encryption keys, etc.). The
183 * "binary" header contains ARM binary code to be executed prior to
184 * executing the main payload (usually the bootloader). This is
185 * typically used to execute DDR3 training code. The "register" header
186 * allows to describe a set of (address, value) tuples that are
187 * generally used to configure the DRAM controller.
189 #define OPT_HDR_V1_SECURE_TYPE 0x1
190 #define OPT_HDR_V1_BINARY_TYPE 0x2
191 #define OPT_HDR_V1_REGISTER_TYPE 0x3
203 enum kwbimage_cmd_types {
213 void init_kwb_image_type (void);
216 * Byte 8 of the image header contains the version number. In the v0
217 * header, byte 8 was reserved, and always set to 0. In the v1 header,
218 * byte 8 has been changed to a proper field, set to 1.
220 static inline unsigned int kwbimage_version(const void *header)
222 const unsigned char *ptr = header;
226 static inline size_t kwbheader_size(const void *header)
228 if (kwbimage_version(header) == 0) {
229 const struct main_hdr_v0 *hdr = header;
231 return sizeof(*hdr) +
232 (hdr->ext & 0x1) ? sizeof(struct ext_hdr_v0) : 0;
234 const struct main_hdr_v1 *hdr = header;
236 return (hdr->headersz_msb << 16) |
237 le16_to_cpu(hdr->headersz_lsb);
241 static inline size_t kwbheader_size_for_csum(const void *header)
243 if (kwbimage_version(header) == 0)
244 return sizeof(struct main_hdr_v0);
246 return kwbheader_size(header);
249 static inline uint32_t opt_hdr_v1_size(const struct opt_hdr_v1 *ohdr)
251 return (ohdr->headersz_msb << 16) | le16_to_cpu(ohdr->headersz_lsb);
254 static inline int opt_hdr_v1_valid_size(const struct opt_hdr_v1 *ohdr,
255 const void *mhdr_end)
259 if ((void *)(ohdr + 1) > mhdr_end)
262 ohdr_size = opt_hdr_v1_size(ohdr);
263 if (ohdr_size < 8 || (void *)((uint8_t *)ohdr + ohdr_size) > mhdr_end)
269 static inline struct opt_hdr_v1 *opt_hdr_v1_first(void *img) {
270 struct main_hdr_v1 *mhdr;
272 if (kwbimage_version(img) != 1)
277 return (struct opt_hdr_v1 *)(mhdr + 1);
282 static inline uint8_t *opt_hdr_v1_ext(struct opt_hdr_v1 *cur)
284 uint32_t size = opt_hdr_v1_size(cur);
286 return (uint8_t *)cur + size - 4;
289 static inline struct opt_hdr_v1 *_opt_hdr_v1_next(struct opt_hdr_v1 *cur)
291 return (struct opt_hdr_v1 *)((uint8_t *)cur + opt_hdr_v1_size(cur));
294 static inline struct opt_hdr_v1 *opt_hdr_v1_next(struct opt_hdr_v1 *cur)
296 if (*opt_hdr_v1_ext(cur) & 0x1)
297 return _opt_hdr_v1_next(cur);
302 #define for_each_opt_hdr_v1(ohdr, img) \
303 for ((ohdr) = opt_hdr_v1_first((img)); \
305 (ohdr) = opt_hdr_v1_next((ohdr)))
307 #endif /* _KWBIMAGE_H_ */