tools/kwbimage.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2008
   4  * Marvell Semiconductor <www.marvell.com>
   5  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   6  */
   7
   8 #ifndef _KWBIMAGE_H_
   9 #define _KWBIMAGE_H_
  10
  11 #include <compiler.h>
  12 #include <stdint.h>
  13
  14 #define KWBIMAGE_MAX_CONFIG     ((0x1dc - 0x20)/sizeof(struct reg_config))
  15 #define MAX_TEMPBUF_LEN         32
  16
  17 /* NAND ECC Mode */
  18 #define IBR_HDR_ECC_DEFAULT             0x00
  19 #define IBR_HDR_ECC_FORCED_HAMMING      0x01
  20 #define IBR_HDR_ECC_FORCED_RS           0x02
  21 #define IBR_HDR_ECC_DISABLED            0x03
  22
  23 /* Boot Type - block ID */
  24 #define IBR_HDR_I2C_ID                  0x4D
  25 #define IBR_HDR_SPI_ID                  0x5A
  26 #define IBR_HDR_NAND_ID                 0x8B
  27 #define IBR_HDR_SATA_ID                 0x78
  28 #define IBR_HDR_PEX_ID                  0x9C
  29 #define IBR_HDR_UART_ID                 0x69
  30 #define IBR_HDR_SDIO_ID                 0xAE
  31 #define IBR_DEF_ATTRIB                  0x00
  32
  33 /* Structure of the main header, version 0 (Kirkwood, Dove) */
  34 struct main_hdr_v0 {
  35         uint8_t  blockid;               /* 0x0       */
  36         uint8_t  nandeccmode;           /* 0x1       */
  37         uint16_t nandpagesize;          /* 0x2-0x3   */
  38         uint32_t blocksize;             /* 0x4-0x7   */
  39         uint32_t rsvd1;                 /* 0x8-0xB   */
  40         uint32_t srcaddr;               /* 0xC-0xF   */
  41         uint32_t destaddr;              /* 0x10-0x13 */
  42         uint32_t execaddr;              /* 0x14-0x17 */
  43         uint8_t  satapiomode;           /* 0x18      */
  44         uint8_t  rsvd3;                 /* 0x19      */
  45         uint16_t ddrinitdelay;          /* 0x1A-0x1B */
  46         uint16_t rsvd2;                 /* 0x1C-0x1D */
  47         uint8_t  ext;                   /* 0x1E      */
  48         uint8_t  checksum;              /* 0x1F      */
  49 };
  50
  51 struct ext_hdr_v0_reg {
  52         uint32_t raddr;
  53         uint32_t rdata;
  54 };
  55
  56 #define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
  57
  58 struct ext_hdr_v0 {
  59         uint32_t              offset;
  60         uint8_t               reserved[0x20 - sizeof(uint32_t)];
  61         struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
  62         uint8_t               reserved2[7];
  63         uint8_t               checksum;
  64 };
  65
  66 struct kwb_header {
  67         struct main_hdr_v0      kwb_hdr;
  68         struct ext_hdr_v0       kwb_exthdr;
  69 };
  70
  71 /* Structure of the main header, version 1 (Armada 370/38x/XP) */
  72 struct main_hdr_v1 {
  73         uint8_t  blockid;               /* 0x0       */
  74         uint8_t  flags;                 /* 0x1       */
  75         uint16_t reserved2;             /* 0x2-0x3   */
  76         uint32_t blocksize;             /* 0x4-0x7   */
  77         uint8_t  version;               /* 0x8       */
  78         uint8_t  headersz_msb;          /* 0x9       */
  79         uint16_t headersz_lsb;          /* 0xA-0xB   */
  80         uint32_t srcaddr;               /* 0xC-0xF   */
  81         uint32_t destaddr;              /* 0x10-0x13 */
  82         uint32_t execaddr;              /* 0x14-0x17 */
  83         uint8_t  options;               /* 0x18      */
  84         uint8_t  nandblocksize;         /* 0x19      */
  85         uint8_t  nandbadblklocation;    /* 0x1A      */
  86         uint8_t  reserved4;             /* 0x1B      */
  87         uint16_t reserved5;             /* 0x1C-0x1D */
  88         uint8_t  ext;                   /* 0x1E      */
  89         uint8_t  checksum;              /* 0x1F      */
  90 };
  91
  92 /*
  93  * Main header options
  94  */
  95 #define MAIN_HDR_V1_OPT_BAUD_DEFAULT    0
  96 #define MAIN_HDR_V1_OPT_BAUD_2400       0x1
  97 #define MAIN_HDR_V1_OPT_BAUD_4800       0x2
  98 #define MAIN_HDR_V1_OPT_BAUD_9600       0x3
  99 #define MAIN_HDR_V1_OPT_BAUD_19200      0x4
 100 #define MAIN_HDR_V1_OPT_BAUD_38400      0x5
 101 #define MAIN_HDR_V1_OPT_BAUD_57600      0x6
 102 #define MAIN_HDR_V1_OPT_BAUD_115200     0x7
 103
 104 /*
 105  * Header for the optional headers, version 1 (Armada 370, Armada XP)
 106  */
 107 struct opt_hdr_v1 {
 108         uint8_t  headertype;
 109         uint8_t  headersz_msb;
 110         uint16_t headersz_lsb;
 111         char     data[0];
 112 };
 113
 114 /*
 115  * Public Key data in DER format
 116  */
 117 struct pubkey_der_v1 {
 118         uint8_t key[524];
 119 };
 120
 121 /*
 122  * Signature (RSA 2048)
 123  */
 124 struct sig_v1 {
 125         uint8_t sig[256];
 126 };
 127
 128 /*
 129  * Structure of secure header (Armada 38x)
 130  */
 131 struct secure_hdr_v1 {
 132         uint8_t  headertype;            /* 0x0 */
 133         uint8_t  headersz_msb;          /* 0x1 */
 134         uint16_t headersz_lsb;          /* 0x2 - 0x3 */
 135         uint32_t reserved1;             /* 0x4 - 0x7 */
 136         struct pubkey_der_v1 kak;       /* 0x8 - 0x213 */
 137         uint8_t  jtag_delay;            /* 0x214 */
 138         uint8_t  reserved2;             /* 0x215 */
 139         uint16_t reserved3;             /* 0x216 - 0x217 */
 140         uint32_t boxid;                 /* 0x218 - 0x21B */
 141         uint32_t flashid;               /* 0x21C - 0x21F */
 142         struct sig_v1 hdrsig;           /* 0x220 - 0x31F */
 143         struct sig_v1 imgsig;           /* 0x320 - 0x41F */
 144         struct pubkey_der_v1 csk[16];   /* 0x420 - 0x24DF */
 145         struct sig_v1 csksig;           /* 0x24E0 - 0x25DF */
 146         uint8_t  next;                  /* 0x25E0 */
 147         uint8_t  reserved4;             /* 0x25E1 */
 148         uint16_t reserved5;             /* 0x25E2 - 0x25E3 */
 149 };
 150
 151 /*
 152  * Various values for the opt_hdr_v1->headertype field, describing the
 153  * different types of optional headers. The "secure" header contains
 154  * informations related to secure boot (encryption keys, etc.). The
 155  * "binary" header contains ARM binary code to be executed prior to
 156  * executing the main payload (usually the bootloader). This is
 157  * typically used to execute DDR3 training code. The "register" header
 158  * allows to describe a set of (address, value) tuples that are
 159  * generally used to configure the DRAM controller.
 160  */
 161 #define OPT_HDR_V1_SECURE_TYPE   0x1
 162 #define OPT_HDR_V1_BINARY_TYPE   0x2
 163 #define OPT_HDR_V1_REGISTER_TYPE 0x3
 164
 165 #define KWBHEADER_V1_SIZE(hdr) \
 166         (((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb))
 167
 168 enum kwbimage_cmd {
 169         CMD_INVALID,
 170         CMD_BOOT_FROM,
 171         CMD_NAND_ECC_MODE,
 172         CMD_NAND_PAGE_SIZE,
 173         CMD_SATA_PIO_MODE,
 174         CMD_DDR_INIT_DELAY,
 175         CMD_DATA
 176 };
 177
 178 enum kwbimage_cmd_types {
 179         CFG_INVALID = -1,
 180         CFG_COMMAND,
 181         CFG_DATA0,
 182         CFG_DATA1
 183 };
 184
 185 /*
 186  * functions
 187  */
 188 void init_kwb_image_type (void);
 189
 190 /*
 191  * Byte 8 of the image header contains the version number. In the v0
 192  * header, byte 8 was reserved, and always set to 0. In the v1 header,
 193  * byte 8 has been changed to a proper field, set to 1.
 194  */
 195 static inline unsigned int image_version(void *header)
 196 {
 197         unsigned char *ptr = header;
 198         return ptr[8];
 199 }
 200
 201 #endif /* _KWBIMAGE_H_ */