tools/kwbimage.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2008
   4  * Marvell Semiconductor <www.marvell.com>
   5  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   6  */
   7
   8 #ifndef _KWBIMAGE_H_
   9 #define _KWBIMAGE_H_
  10
  11 #include <compiler.h>
  12 #include <stdint.h>
  13
  14 #ifdef __GNUC__
  15 #define __packed __attribute((packed))
  16 #else
  17 #define __packed
  18 #endif
  19
  20 #define KWBIMAGE_MAX_CONFIG     ((0x1dc - 0x20)/sizeof(struct reg_config))
  21 #define MAX_TEMPBUF_LEN         32
  22
  23 /* NAND ECC Mode */
  24 #define IBR_HDR_ECC_DEFAULT             0x00
  25 #define IBR_HDR_ECC_FORCED_HAMMING      0x01
  26 #define IBR_HDR_ECC_FORCED_RS           0x02
  27 #define IBR_HDR_ECC_DISABLED            0x03
  28
  29 /* Boot Type - block ID */
  30 #define IBR_HDR_I2C_ID                  0x4D
  31 #define IBR_HDR_SPI_ID                  0x5A
  32 #define IBR_HDR_NAND_ID                 0x8B
  33 #define IBR_HDR_SATA_ID                 0x78
  34 #define IBR_HDR_PEX_ID                  0x9C
  35 #define IBR_HDR_UART_ID                 0x69
  36 #define IBR_HDR_SDIO_ID                 0xAE
  37 #define IBR_DEF_ATTRIB                  0x00
  38
  39 /* Structure of the main header, version 0 (Kirkwood, Dove) */
  40 struct main_hdr_v0 {
  41         uint8_t  blockid;               /* 0x0       */
  42         uint8_t  nandeccmode;           /* 0x1       */
  43         uint16_t nandpagesize;          /* 0x2-0x3   */
  44         uint32_t blocksize;             /* 0x4-0x7   */
  45         uint32_t rsvd1;                 /* 0x8-0xB   */
  46         uint32_t srcaddr;               /* 0xC-0xF   */
  47         uint32_t destaddr;              /* 0x10-0x13 */
  48         uint32_t execaddr;              /* 0x14-0x17 */
  49         uint8_t  satapiomode;           /* 0x18      */
  50         uint8_t  rsvd3;                 /* 0x19      */
  51         uint16_t ddrinitdelay;          /* 0x1A-0x1B */
  52         uint16_t rsvd2;                 /* 0x1C-0x1D */
  53         uint8_t  ext;                   /* 0x1E      */
  54         uint8_t  checksum;              /* 0x1F      */
  55 } __packed;
  56
  57 struct ext_hdr_v0_reg {
  58         uint32_t raddr;
  59         uint32_t rdata;
  60 } __packed;
  61
  62 #define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
  63
  64 struct ext_hdr_v0 {
  65         uint32_t              offset;
  66         uint8_t               reserved[0x20 - sizeof(uint32_t)];
  67         struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
  68         uint8_t               reserved2[7];
  69         uint8_t               checksum;
  70 } __packed;
  71
  72 /* Structure of the main header, version 1 (Armada 370/XP/375/38x/39x) */
  73 struct main_hdr_v1 {
  74         uint8_t  blockid;               /* 0x0       */
  75         uint8_t  flags;                 /* 0x1       */
  76         uint16_t nandpagesize;          /* 0x2-0x3   */
  77         uint32_t blocksize;             /* 0x4-0x7   */
  78         uint8_t  version;               /* 0x8       */
  79         uint8_t  headersz_msb;          /* 0x9       */
  80         uint16_t headersz_lsb;          /* 0xA-0xB   */
  81         uint32_t srcaddr;               /* 0xC-0xF   */
  82         uint32_t destaddr;              /* 0x10-0x13 */
  83         uint32_t execaddr;              /* 0x14-0x17 */
  84         uint8_t  options;               /* 0x18      */
  85         uint8_t  nandblocksize;         /* 0x19      */
  86         uint8_t  nandbadblklocation;    /* 0x1A      */
  87         uint8_t  reserved4;             /* 0x1B      */
  88         uint16_t reserved5;             /* 0x1C-0x1D */
  89         uint8_t  ext;                   /* 0x1E      */
  90         uint8_t  checksum;              /* 0x1F      */
  91 } __packed;
  92
  93 /*
  94  * Main header options
  95  */
  96 #define MAIN_HDR_V1_OPT_BAUD_DEFAULT    0
  97 #define MAIN_HDR_V1_OPT_BAUD_2400       0x1
  98 #define MAIN_HDR_V1_OPT_BAUD_4800       0x2
  99 #define MAIN_HDR_V1_OPT_BAUD_9600       0x3
 100 #define MAIN_HDR_V1_OPT_BAUD_19200      0x4
 101 #define MAIN_HDR_V1_OPT_BAUD_38400      0x5
 102 #define MAIN_HDR_V1_OPT_BAUD_57600      0x6
 103 #define MAIN_HDR_V1_OPT_BAUD_115200     0x7
 104
 105 /*
 106  * Header for the optional headers, version 1 (Armada 370/XP/375/38x/39x)
 107  */
 108 struct opt_hdr_v1 {
 109         uint8_t  headertype;
 110         uint8_t  headersz_msb;
 111         uint16_t headersz_lsb;
 112         char     data[0];
 113 } __packed;
 114
 115 /*
 116  * Public Key data in DER format
 117  */
 118 struct pubkey_der_v1 {
 119         uint8_t key[524];
 120 } __packed;
 121
 122 /*
 123  * Signature (RSA 2048)
 124  */
 125 struct sig_v1 {
 126         uint8_t sig[256];
 127 } __packed;
 128
 129 /*
 130  * Structure of secure header (Armada XP/375/38x/39x)
 131  */
 132 struct secure_hdr_v1 {
 133         uint8_t  headertype;            /* 0x0 */
 134         uint8_t  headersz_msb;          /* 0x1 */
 135         uint16_t headersz_lsb;          /* 0x2 - 0x3 */
 136         uint32_t reserved1;             /* 0x4 - 0x7 */
 137         struct pubkey_der_v1 kak;       /* 0x8 - 0x213 */
 138         uint8_t  jtag_delay;            /* 0x214 */
 139         uint8_t  reserved2;             /* 0x215 */
 140         uint16_t reserved3;             /* 0x216 - 0x217 */
 141         uint32_t boxid;                 /* 0x218 - 0x21B */
 142         uint32_t flashid;               /* 0x21C - 0x21F */
 143         struct sig_v1 hdrsig;           /* 0x220 - 0x31F */
 144         struct sig_v1 imgsig;           /* 0x320 - 0x41F */
 145         struct pubkey_der_v1 csk[16];   /* 0x420 - 0x24DF */
 146         struct sig_v1 csksig;           /* 0x24E0 - 0x25DF */
 147         uint8_t  next;                  /* 0x25E0 */
 148         uint8_t  reserved4;             /* 0x25E1 */
 149         uint16_t reserved5;             /* 0x25E2 - 0x25E3 */
 150 } __packed;
 151
 152 /*
 153  * Structure of register set
 154  */
 155 struct register_set_hdr_v1 {
 156         uint8_t  headertype;            /* 0x0 */
 157         uint8_t  headersz_msb;          /* 0x1 */
 158         uint16_t headersz_lsb;          /* 0x2 - 0x3 */
 159         union {
 160                 struct {
 161                         uint32_t address;       /* 0x4+8*N - 0x7+8*N */
 162                         uint32_t value;         /* 0x8+8*N - 0xB+8*N */
 163                 } __packed entry;
 164                 struct {
 165                         uint8_t  next;          /* 0xC+8*N */
 166                         uint8_t  delay;         /* 0xD+8*N */
 167                         uint16_t reserved;      /* 0xE+8*N - 0xF+8*N */
 168                 } __packed last_entry;
 169         } data[];
 170 } __packed;
 171
 172 /*
 173  * Value 0 in register_set_hdr_v1 delay field is special.
 174  * Instead of delay it setup SDRAM Controller.
 175  */
 176 #define REGISTER_SET_HDR_OPT_DELAY_SDRAM_SETUP 0
 177 #define REGISTER_SET_HDR_OPT_DELAY_MS(val) ((val) ?: 1)
 178
 179 /*
 180  * Various values for the opt_hdr_v1->headertype field, describing the
 181  * different types of optional headers. The "secure" header contains
 182  * informations related to secure boot (encryption keys, etc.). The
 183  * "binary" header contains ARM binary code to be executed prior to
 184  * executing the main payload (usually the bootloader). This is
 185  * typically used to execute DDR3 training code. The "register" header
 186  * allows to describe a set of (address, value) tuples that are
 187  * generally used to configure the DRAM controller.
 188  */
 189 #define OPT_HDR_V1_SECURE_TYPE   0x1
 190 #define OPT_HDR_V1_BINARY_TYPE   0x2
 191 #define OPT_HDR_V1_REGISTER_TYPE 0x3
 192
 193 enum kwbimage_cmd {
 194         CMD_INVALID,
 195         CMD_BOOT_FROM,
 196         CMD_NAND_ECC_MODE,
 197         CMD_NAND_PAGE_SIZE,
 198         CMD_SATA_PIO_MODE,
 199         CMD_DDR_INIT_DELAY,
 200         CMD_DATA
 201 };
 202
 203 enum kwbimage_cmd_types {
 204         CFG_INVALID = -1,
 205         CFG_COMMAND,
 206         CFG_DATA0,
 207         CFG_DATA1
 208 };
 209
 210 /*
 211  * functions
 212  */
 213 void init_kwb_image_type (void);
 214
 215 /*
 216  * Byte 8 of the image header contains the version number. In the v0
 217  * header, byte 8 was reserved, and always set to 0. In the v1 header,
 218  * byte 8 has been changed to a proper field, set to 1.
 219  */
 220 static inline unsigned int kwbimage_version(const void *header)
 221 {
 222         const unsigned char *ptr = header;
 223         return ptr[8];
 224 }
 225
 226 static inline size_t kwbheader_size(const void *header)
 227 {
 228         if (kwbimage_version(header) == 0) {
 229                 const struct main_hdr_v0 *hdr = header;
 230
 231                 return sizeof(*hdr) +
 232                        (hdr->ext & 0x1) ? sizeof(struct ext_hdr_v0) : 0;
 233         } else {
 234                 const struct main_hdr_v1 *hdr = header;
 235
 236                 return (hdr->headersz_msb << 16) |
 237                        le16_to_cpu(hdr->headersz_lsb);
 238         }
 239 }
 240
 241 static inline size_t kwbheader_size_for_csum(const void *header)
 242 {
 243         if (kwbimage_version(header) == 0)
 244                 return sizeof(struct main_hdr_v0);
 245         else
 246                 return kwbheader_size(header);
 247 }
 248
 249 static inline uint32_t opt_hdr_v1_size(const struct opt_hdr_v1 *ohdr)
 250 {
 251         return (ohdr->headersz_msb << 16) | le16_to_cpu(ohdr->headersz_lsb);
 252 }
 253
 254 static inline int opt_hdr_v1_valid_size(const struct opt_hdr_v1 *ohdr,
 255                                         const void *mhdr_end)
 256 {
 257         uint32_t ohdr_size;
 258
 259         if ((void *)(ohdr + 1) > mhdr_end)
 260                 return 0;
 261
 262         ohdr_size = opt_hdr_v1_size(ohdr);
 263         if (ohdr_size < 8 || (void *)((uint8_t *)ohdr + ohdr_size) > mhdr_end)
 264                 return 0;
 265
 266         return 1;
 267 }
 268
 269 static inline struct opt_hdr_v1 *opt_hdr_v1_first(void *img) {
 270         struct main_hdr_v1 *mhdr;
 271
 272         if (kwbimage_version(img) != 1)
 273                 return NULL;
 274
 275         mhdr = img;
 276         if (mhdr->ext & 0x1)
 277                 return (struct opt_hdr_v1 *)(mhdr + 1);
 278         else
 279                 return NULL;
 280 }
 281
 282 static inline uint8_t *opt_hdr_v1_ext(struct opt_hdr_v1 *cur)
 283 {
 284         uint32_t size = opt_hdr_v1_size(cur);
 285
 286         return (uint8_t *)cur + size - 4;
 287 }
 288
 289 static inline struct opt_hdr_v1 *_opt_hdr_v1_next(struct opt_hdr_v1 *cur)
 290 {
 291         return (struct opt_hdr_v1 *)((uint8_t *)cur + opt_hdr_v1_size(cur));
 292 }
 293
 294 static inline struct opt_hdr_v1 *opt_hdr_v1_next(struct opt_hdr_v1 *cur)
 295 {
 296         if (*opt_hdr_v1_ext(cur) & 0x1)
 297                 return _opt_hdr_v1_next(cur);
 298         else
 299                 return NULL;
 300 }
 301
 302 #define for_each_opt_hdr_v1(ohdr, img)          \
 303         for ((ohdr) = opt_hdr_v1_first((img));  \
 304              (ohdr) != NULL;                    \
 305              (ohdr) = opt_hdr_v1_next((ohdr)))
 306
 307 #endif /* _KWBIMAGE_H_ */