1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
15 #define __packed __attribute((packed))
20 #define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config))
21 #define MAX_TEMPBUF_LEN 32
24 #define IBR_HDR_ECC_DEFAULT 0x00
25 #define IBR_HDR_ECC_FORCED_HAMMING 0x01
26 #define IBR_HDR_ECC_FORCED_RS 0x02
27 #define IBR_HDR_ECC_DISABLED 0x03
29 /* Boot Type - block ID */
30 #define IBR_HDR_I2C_ID 0x4D
31 #define IBR_HDR_SPI_ID 0x5A
32 #define IBR_HDR_NAND_ID 0x8B
33 #define IBR_HDR_SATA_ID 0x78
34 #define IBR_HDR_PEX_ID 0x9C
35 #define IBR_HDR_UART_ID 0x69
36 #define IBR_HDR_SDIO_ID 0xAE
37 #define IBR_DEF_ATTRIB 0x00
39 /* Structure of the main header, version 0 (Kirkwood, Dove) */
41 uint8_t blockid; /* 0x0 */
42 uint8_t nandeccmode; /* 0x1 */
43 uint16_t nandpagesize; /* 0x2-0x3 */
44 uint32_t blocksize; /* 0x4-0x7 */
45 uint32_t rsvd1; /* 0x8-0xB */
46 uint32_t srcaddr; /* 0xC-0xF */
47 uint32_t destaddr; /* 0x10-0x13 */
48 uint32_t execaddr; /* 0x14-0x17 */
49 uint8_t satapiomode; /* 0x18 */
50 uint8_t rsvd3; /* 0x19 */
51 uint16_t ddrinitdelay; /* 0x1A-0x1B */
52 uint16_t rsvd2; /* 0x1C-0x1D */
53 uint8_t ext; /* 0x1E */
54 uint8_t checksum; /* 0x1F */
57 struct ext_hdr_v0_reg {
62 #define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
66 uint8_t reserved[0x20 - sizeof(uint32_t)];
67 struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
73 struct main_hdr_v0 kwb_hdr;
74 struct ext_hdr_v0 kwb_exthdr;
77 /* Structure of the main header, version 1 (Armada 370/38x/XP) */
79 uint8_t blockid; /* 0x0 */
80 uint8_t flags; /* 0x1 */
81 uint16_t reserved2; /* 0x2-0x3 */
82 uint32_t blocksize; /* 0x4-0x7 */
83 uint8_t version; /* 0x8 */
84 uint8_t headersz_msb; /* 0x9 */
85 uint16_t headersz_lsb; /* 0xA-0xB */
86 uint32_t srcaddr; /* 0xC-0xF */
87 uint32_t destaddr; /* 0x10-0x13 */
88 uint32_t execaddr; /* 0x14-0x17 */
89 uint8_t options; /* 0x18 */
90 uint8_t nandblocksize; /* 0x19 */
91 uint8_t nandbadblklocation; /* 0x1A */
92 uint8_t reserved4; /* 0x1B */
93 uint16_t reserved5; /* 0x1C-0x1D */
94 uint8_t ext; /* 0x1E */
95 uint8_t checksum; /* 0x1F */
101 #define MAIN_HDR_V1_OPT_BAUD_DEFAULT 0
102 #define MAIN_HDR_V1_OPT_BAUD_2400 0x1
103 #define MAIN_HDR_V1_OPT_BAUD_4800 0x2
104 #define MAIN_HDR_V1_OPT_BAUD_9600 0x3
105 #define MAIN_HDR_V1_OPT_BAUD_19200 0x4
106 #define MAIN_HDR_V1_OPT_BAUD_38400 0x5
107 #define MAIN_HDR_V1_OPT_BAUD_57600 0x6
108 #define MAIN_HDR_V1_OPT_BAUD_115200 0x7
111 * Header for the optional headers, version 1 (Armada 370, Armada XP)
115 uint8_t headersz_msb;
116 uint16_t headersz_lsb;
121 * Public Key data in DER format
123 struct pubkey_der_v1 {
128 * Signature (RSA 2048)
135 * Structure of secure header (Armada 38x)
137 struct secure_hdr_v1 {
138 uint8_t headertype; /* 0x0 */
139 uint8_t headersz_msb; /* 0x1 */
140 uint16_t headersz_lsb; /* 0x2 - 0x3 */
141 uint32_t reserved1; /* 0x4 - 0x7 */
142 struct pubkey_der_v1 kak; /* 0x8 - 0x213 */
143 uint8_t jtag_delay; /* 0x214 */
144 uint8_t reserved2; /* 0x215 */
145 uint16_t reserved3; /* 0x216 - 0x217 */
146 uint32_t boxid; /* 0x218 - 0x21B */
147 uint32_t flashid; /* 0x21C - 0x21F */
148 struct sig_v1 hdrsig; /* 0x220 - 0x31F */
149 struct sig_v1 imgsig; /* 0x320 - 0x41F */
150 struct pubkey_der_v1 csk[16]; /* 0x420 - 0x24DF */
151 struct sig_v1 csksig; /* 0x24E0 - 0x25DF */
152 uint8_t next; /* 0x25E0 */
153 uint8_t reserved4; /* 0x25E1 */
154 uint16_t reserved5; /* 0x25E2 - 0x25E3 */
158 * Structure of register set
160 struct register_set_hdr_v1 {
161 uint8_t headertype; /* 0x0 */
162 uint8_t headersz_msb; /* 0x1 */
163 uint16_t headersz_lsb; /* 0x2 - 0x3 */
166 uint32_t address; /* 0x4+8*N - 0x7+8*N */
167 uint32_t value; /* 0x8+8*N - 0xB+8*N */
170 uint8_t next; /* 0xC+8*N */
171 uint8_t delay; /* 0xD+8*N */
172 uint16_t reserved; /* 0xE+8*N - 0xF+8*N */
173 } __packed last_entry;
178 * Value 0 in register_set_hdr_v1 delay field is special.
179 * Instead of delay it setup SDRAM Controller.
181 #define REGISTER_SET_HDR_OPT_DELAY_SDRAM_SETUP 0
182 #define REGISTER_SET_HDR_OPT_DELAY_MS(val) ((val) ?: 1)
185 * Various values for the opt_hdr_v1->headertype field, describing the
186 * different types of optional headers. The "secure" header contains
187 * informations related to secure boot (encryption keys, etc.). The
188 * "binary" header contains ARM binary code to be executed prior to
189 * executing the main payload (usually the bootloader). This is
190 * typically used to execute DDR3 training code. The "register" header
191 * allows to describe a set of (address, value) tuples that are
192 * generally used to configure the DRAM controller.
194 #define OPT_HDR_V1_SECURE_TYPE 0x1
195 #define OPT_HDR_V1_BINARY_TYPE 0x2
196 #define OPT_HDR_V1_REGISTER_TYPE 0x3
198 #define KWBHEADER_V0_SIZE(hdr) \
199 (((hdr)->ext & 0x1) ? sizeof(struct kwb_header) : \
200 sizeof(struct main_hdr_v0))
202 #define KWBHEADER_V1_SIZE(hdr) \
203 (((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb))
215 enum kwbimage_cmd_types {
225 void init_kwb_image_type (void);
228 * Byte 8 of the image header contains the version number. In the v0
229 * header, byte 8 was reserved, and always set to 0. In the v1 header,
230 * byte 8 has been changed to a proper field, set to 1.
232 static inline unsigned int image_version(const void *header)
234 const unsigned char *ptr = header;
238 #endif /* _KWBIMAGE_H_ */