1 // SPDX-License-Identifier: GPL-2.0+
3 * Image manipulator for Marvell SoCs
4 * supports Kirkwood, Dove, Armada 370, Armada XP, Armada 375, Armada 38x and
7 * (C) Copyright 2013 Thomas Petazzoni
8 * <thomas.petazzoni@free-electrons.com>
11 #define OPENSSL_API_COMPAT 0x10101000L
13 #include "imagetool.h"
20 #include <openssl/bn.h>
21 #include <openssl/rsa.h>
22 #include <openssl/pem.h>
23 #include <openssl/err.h>
24 #include <openssl/evp.h>
26 #if OPENSSL_VERSION_NUMBER < 0x10100000L || \
27 (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x2070000fL)
28 static void RSA_get0_key(const RSA *r,
29 const BIGNUM **n, const BIGNUM **e, const BIGNUM **d)
39 #elif !defined(LIBRESSL_VERSION_NUMBER)
40 void EVP_MD_CTX_cleanup(EVP_MD_CTX *ctx)
42 EVP_MD_CTX_reset(ctx);
46 /* fls - find last (most-significant) bit set in 4-bit integer */
47 static inline int fls4(int num)
61 static struct image_cfg_element *image_cfg;
63 static int verbose_mode;
77 struct boot_mode boot_modes[] = {
78 { IBR_HDR_I2C_ID, "i2c" },
79 { IBR_HDR_SPI_ID, "spi" },
80 { IBR_HDR_NAND_ID, "nand" },
81 { IBR_HDR_SATA_ID, "sata" },
82 { IBR_HDR_PEX_ID, "pex" },
83 { IBR_HDR_UART_ID, "uart" },
84 { IBR_HDR_SDIO_ID, "sdio" },
88 struct nand_ecc_mode {
93 struct nand_ecc_mode nand_ecc_modes[] = {
94 { IBR_HDR_ECC_DEFAULT, "default" },
95 { IBR_HDR_ECC_FORCED_HAMMING, "hamming" },
96 { IBR_HDR_ECC_FORCED_RS, "rs" },
97 { IBR_HDR_ECC_DISABLED, "disabled" },
101 /* Used to identify an undefined execution or destination address */
102 #define ADDR_INVALID ((uint32_t)-1)
104 #define BINARY_MAX_ARGS 255
106 /* In-memory representation of a line of the configuration file */
108 enum image_cfg_type {
109 IMAGE_CFG_VERSION = 0x1,
113 IMAGE_CFG_NAND_BLKSZ,
114 IMAGE_CFG_NAND_BADBLK_LOCATION,
115 IMAGE_CFG_NAND_ECC_MODE,
116 IMAGE_CFG_NAND_PAGESZ,
120 IMAGE_CFG_DATA_DELAY,
128 IMAGE_CFG_JTAG_DELAY,
131 IMAGE_CFG_SEC_COMMON_IMG,
132 IMAGE_CFG_SEC_SPECIALIZED_IMG,
133 IMAGE_CFG_SEC_BOOT_DEV,
134 IMAGE_CFG_SEC_FUSE_DUMP,
139 static const char * const id_strs[] = {
140 [IMAGE_CFG_VERSION] = "VERSION",
141 [IMAGE_CFG_BOOT_FROM] = "BOOT_FROM",
142 [IMAGE_CFG_DEST_ADDR] = "DEST_ADDR",
143 [IMAGE_CFG_EXEC_ADDR] = "EXEC_ADDR",
144 [IMAGE_CFG_NAND_BLKSZ] = "NAND_BLKSZ",
145 [IMAGE_CFG_NAND_BADBLK_LOCATION] = "NAND_BADBLK_LOCATION",
146 [IMAGE_CFG_NAND_ECC_MODE] = "NAND_ECC_MODE",
147 [IMAGE_CFG_NAND_PAGESZ] = "NAND_PAGE_SIZE",
148 [IMAGE_CFG_CPU] = "CPU",
149 [IMAGE_CFG_BINARY] = "BINARY",
150 [IMAGE_CFG_DATA] = "DATA",
151 [IMAGE_CFG_DATA_DELAY] = "DATA_DELAY",
152 [IMAGE_CFG_BAUDRATE] = "BAUDRATE",
153 [IMAGE_CFG_UART_PORT] = "UART_PORT",
154 [IMAGE_CFG_UART_MPP] = "UART_MPP",
155 [IMAGE_CFG_DEBUG] = "DEBUG",
156 [IMAGE_CFG_KAK] = "KAK",
157 [IMAGE_CFG_CSK] = "CSK",
158 [IMAGE_CFG_CSK_INDEX] = "CSK_INDEX",
159 [IMAGE_CFG_JTAG_DELAY] = "JTAG_DELAY",
160 [IMAGE_CFG_BOX_ID] = "BOX_ID",
161 [IMAGE_CFG_FLASH_ID] = "FLASH_ID",
162 [IMAGE_CFG_SEC_COMMON_IMG] = "SEC_COMMON_IMG",
163 [IMAGE_CFG_SEC_SPECIALIZED_IMG] = "SEC_SPECIALIZED_IMG",
164 [IMAGE_CFG_SEC_BOOT_DEV] = "SEC_BOOT_DEV",
165 [IMAGE_CFG_SEC_FUSE_DUMP] = "SEC_FUSE_DUMP"
168 struct image_cfg_element {
169 enum image_cfg_type type;
171 unsigned int version;
172 unsigned int cpu_sheeva;
173 unsigned int bootfrom;
176 unsigned int loadaddr;
177 unsigned int args[BINARY_MAX_ARGS];
180 unsigned int dstaddr;
181 unsigned int execaddr;
182 unsigned int nandblksz;
183 unsigned int nandbadblklocation;
184 unsigned int nandeccmode;
185 unsigned int nandpagesz;
186 struct ext_hdr_v0_reg regdata;
187 unsigned int regdata_delay;
188 unsigned int baudrate;
189 unsigned int uart_port;
190 unsigned int uart_mpp;
192 const char *key_name;
197 bool sec_specialized_img;
198 unsigned int sec_boot_dev;
203 #define IMAGE_CFG_ELEMENT_MAX 256
206 * Utility functions to manipulate boot mode and ecc modes (convert
207 * them back and forth between description strings and the
208 * corresponding numerical identifiers).
211 static const char *image_boot_mode_name(unsigned int id)
215 for (i = 0; boot_modes[i].name; i++)
216 if (boot_modes[i].id == id)
217 return boot_modes[i].name;
221 static int image_boot_mode_id(const char *boot_mode_name)
225 for (i = 0; boot_modes[i].name; i++)
226 if (!strcmp(boot_modes[i].name, boot_mode_name))
227 return boot_modes[i].id;
232 static const char *image_nand_ecc_mode_name(unsigned int id)
236 for (i = 0; nand_ecc_modes[i].name; i++)
237 if (nand_ecc_modes[i].id == id)
238 return nand_ecc_modes[i].name;
243 static int image_nand_ecc_mode_id(const char *nand_ecc_mode_name)
247 for (i = 0; nand_ecc_modes[i].name; i++)
248 if (!strcmp(nand_ecc_modes[i].name, nand_ecc_mode_name))
249 return nand_ecc_modes[i].id;
253 static struct image_cfg_element *
254 image_find_option(unsigned int optiontype)
258 for (i = 0; i < cfgn; i++) {
259 if (image_cfg[i].type == optiontype)
260 return &image_cfg[i];
267 image_count_options(unsigned int optiontype)
270 unsigned int count = 0;
272 for (i = 0; i < cfgn; i++)
273 if (image_cfg[i].type == optiontype)
279 static int image_get_csk_index(void)
281 struct image_cfg_element *e;
283 e = image_find_option(IMAGE_CFG_CSK_INDEX);
290 static bool image_get_spezialized_img(void)
292 struct image_cfg_element *e;
294 e = image_find_option(IMAGE_CFG_SEC_SPECIALIZED_IMG);
298 return e->sec_specialized_img;
301 static int image_get_bootfrom(void)
303 struct image_cfg_element *e;
305 e = image_find_option(IMAGE_CFG_BOOT_FROM);
307 /* fallback to SPI if no BOOT_FROM is not provided */
308 return IBR_HDR_SPI_ID;
313 static int image_is_cpu_sheeva(void)
315 struct image_cfg_element *e;
317 e = image_find_option(IMAGE_CFG_CPU);
321 return e->cpu_sheeva;
325 * Compute a 8-bit checksum of a memory area. This algorithm follows
326 * the requirements of the Marvell SoC BootROM specifications.
328 static uint8_t image_checksum8(void *start, uint32_t len)
333 /* check len and return zero checksum if invalid */
346 * Verify checksum over a complete header that includes the checksum field.
347 * Return 1 when OK, otherwise 0.
349 static int main_hdr_checksum_ok(void *hdr)
351 /* Offsets of checksum in v0 and v1 headers are the same */
352 struct main_hdr_v0 *main_hdr = (struct main_hdr_v0 *)hdr;
355 checksum = image_checksum8(hdr, kwbheader_size_for_csum(hdr));
356 /* Calculated checksum includes the header checksum field. Compensate
359 checksum -= main_hdr->checksum;
361 return checksum == main_hdr->checksum;
364 static uint32_t image_checksum32(void *start, uint32_t len)
369 /* check len and return zero checksum if invalid */
373 if (len % sizeof(uint32_t)) {
374 fprintf(stderr, "Length %d is not in multiple of %zu\n",
375 len, sizeof(uint32_t));
382 len -= sizeof(uint32_t);
388 static unsigned int options_to_baudrate(uint8_t options)
390 switch (options & 0x7) {
391 case MAIN_HDR_V1_OPT_BAUD_2400:
393 case MAIN_HDR_V1_OPT_BAUD_4800:
395 case MAIN_HDR_V1_OPT_BAUD_9600:
397 case MAIN_HDR_V1_OPT_BAUD_19200:
399 case MAIN_HDR_V1_OPT_BAUD_38400:
401 case MAIN_HDR_V1_OPT_BAUD_57600:
403 case MAIN_HDR_V1_OPT_BAUD_115200:
405 case MAIN_HDR_V1_OPT_BAUD_DEFAULT:
411 static uint8_t baudrate_to_option(unsigned int baudrate)
415 return MAIN_HDR_V1_OPT_BAUD_2400;
417 return MAIN_HDR_V1_OPT_BAUD_4800;
419 return MAIN_HDR_V1_OPT_BAUD_9600;
421 return MAIN_HDR_V1_OPT_BAUD_19200;
423 return MAIN_HDR_V1_OPT_BAUD_38400;
425 return MAIN_HDR_V1_OPT_BAUD_57600;
427 return MAIN_HDR_V1_OPT_BAUD_115200;
429 return MAIN_HDR_V1_OPT_BAUD_DEFAULT;
433 static void kwb_msg(const char *fmt, ...)
439 vfprintf(stdout, fmt, ap);
444 static int openssl_err(const char *msg)
446 unsigned long ssl_err = ERR_get_error();
448 fprintf(stderr, "%s", msg);
449 fprintf(stderr, ": %s\n",
450 ERR_error_string(ssl_err, 0));
455 static int kwb_load_rsa_key(const char *keydir, const char *name, RSA **p_rsa)
464 snprintf(path, sizeof(path), "%s/%s.key", keydir, name);
465 f = fopen(path, "r");
467 fprintf(stderr, "Couldn't open RSA private key: '%s': %s\n",
468 path, strerror(errno));
472 rsa = PEM_read_RSAPrivateKey(f, 0, NULL, "");
474 openssl_err("Failure reading private key");
484 static int kwb_load_cfg_key(struct image_tool_params *params,
485 unsigned int cfg_option, const char *key_name,
488 struct image_cfg_element *e_key;
494 e_key = image_find_option(cfg_option);
496 fprintf(stderr, "%s not configured\n", key_name);
500 res = kwb_load_rsa_key(params->keydir, e_key->key_name, &key);
502 fprintf(stderr, "Failed to load %s\n", key_name);
511 static int kwb_load_kak(struct image_tool_params *params, RSA **p_kak)
513 return kwb_load_cfg_key(params, IMAGE_CFG_KAK, "KAK", p_kak);
516 static int kwb_load_csk(struct image_tool_params *params, RSA **p_csk)
518 return kwb_load_cfg_key(params, IMAGE_CFG_CSK, "CSK", p_csk);
521 static int kwb_compute_pubkey_hash(struct pubkey_der_v1 *pk,
522 struct hash_v1 *hash)
525 unsigned int key_size;
526 unsigned int hash_size;
529 if (!pk || !hash || pk->key[0] != 0x30 || pk->key[1] != 0x82)
532 key_size = (pk->key[2] << 8) + pk->key[3] + 4;
534 ctx = EVP_MD_CTX_create();
536 return openssl_err("EVP context creation failed");
538 EVP_MD_CTX_init(ctx);
539 if (!EVP_DigestInit(ctx, EVP_sha256())) {
540 ret = openssl_err("Digest setup failed");
544 if (!EVP_DigestUpdate(ctx, pk->key, key_size)) {
545 ret = openssl_err("Hashing data failed");
549 if (!EVP_DigestFinal(ctx, hash->hash, &hash_size)) {
550 ret = openssl_err("Could not obtain hash");
554 EVP_MD_CTX_cleanup(ctx);
557 EVP_MD_CTX_destroy(ctx);
561 static int kwb_import_pubkey(RSA **key, struct pubkey_der_v1 *src, char *keyname)
564 const unsigned char *ptr;
570 rsa = d2i_RSAPublicKey(key, &ptr, sizeof(src->key));
572 openssl_err("error decoding public key");
578 fprintf(stderr, "Failed to decode %s pubkey\n", keyname);
582 static int kwb_export_pubkey(RSA *key, struct pubkey_der_v1 *dst, FILE *hashf,
585 int size_exp, size_mod, size_seq;
586 const BIGNUM *key_e, *key_n;
588 char *errmsg = "Failed to encode %s\n";
590 RSA_get0_key(key, NULL, &key_e, NULL);
591 RSA_get0_key(key, &key_n, NULL, NULL);
593 if (!key || !key_e || !key_n || !dst) {
594 fprintf(stderr, "export pk failed: (%p, %p, %p, %p)",
595 key, key_e, key_n, dst);
596 fprintf(stderr, errmsg, keyname);
601 * According to the specs, the key should be PKCS#1 DER encoded.
602 * But unfortunately the really required encoding seems to be different;
603 * it violates DER...! (But it still conformes to BER.)
604 * (Length always in long form w/ 2 byte length code; no leading zero
605 * when MSB of first byte is set...)
606 * So we cannot use the encoding func provided by OpenSSL and have to
607 * do the encoding manually.
610 size_exp = BN_num_bytes(key_e);
611 size_mod = BN_num_bytes(key_n);
612 size_seq = 4 + size_mod + 4 + size_exp;
614 if (size_mod > 256) {
615 fprintf(stderr, "export pk failed: wrong mod size: %d\n",
617 fprintf(stderr, errmsg, keyname);
621 if (4 + size_seq > sizeof(dst->key)) {
622 fprintf(stderr, "export pk failed: seq too large (%d, %zu)\n",
623 4 + size_seq, sizeof(dst->key));
624 fprintf(stderr, errmsg, keyname);
630 /* PKCS#1 (RFC3447) RSAPublicKey structure */
631 *cur++ = 0x30; /* SEQUENCE */
633 *cur++ = (size_seq >> 8) & 0xFF;
634 *cur++ = size_seq & 0xFF;
636 *cur++ = 0x02; /* INTEGER */
638 *cur++ = (size_mod >> 8) & 0xFF;
639 *cur++ = size_mod & 0xFF;
640 BN_bn2bin(key_n, cur);
643 *cur++ = 0x02; /* INTEGER */
645 *cur++ = (size_exp >> 8) & 0xFF;
646 *cur++ = size_exp & 0xFF;
647 BN_bn2bin(key_e, cur);
650 struct hash_v1 pk_hash;
654 ret = kwb_compute_pubkey_hash(dst, &pk_hash);
656 fprintf(stderr, errmsg, keyname);
660 fprintf(hashf, "SHA256 = ");
661 for (i = 0 ; i < sizeof(pk_hash.hash); ++i)
662 fprintf(hashf, "%02X", pk_hash.hash[i]);
663 fprintf(hashf, "\n");
669 static int kwb_sign(RSA *key, void *data, int datasz, struct sig_v1 *sig,
674 unsigned int sig_size;
678 evp_key = EVP_PKEY_new();
680 return openssl_err("EVP_PKEY object creation failed");
682 if (!EVP_PKEY_set1_RSA(evp_key, key)) {
683 ret = openssl_err("EVP key setup failed");
687 size = EVP_PKEY_size(evp_key);
688 if (size > sizeof(sig->sig)) {
689 fprintf(stderr, "Buffer to small for signature (%d bytes)\n",
695 ctx = EVP_MD_CTX_create();
697 ret = openssl_err("EVP context creation failed");
700 EVP_MD_CTX_init(ctx);
701 if (!EVP_SignInit(ctx, EVP_sha256())) {
702 ret = openssl_err("Signer setup failed");
706 if (!EVP_SignUpdate(ctx, data, datasz)) {
707 ret = openssl_err("Signing data failed");
711 if (!EVP_SignFinal(ctx, sig->sig, &sig_size, evp_key)) {
712 ret = openssl_err("Could not obtain signature");
716 EVP_MD_CTX_cleanup(ctx);
717 EVP_MD_CTX_destroy(ctx);
718 EVP_PKEY_free(evp_key);
723 EVP_MD_CTX_destroy(ctx);
725 EVP_PKEY_free(evp_key);
726 fprintf(stderr, "Failed to create %s signature\n", signame);
730 static int kwb_verify(RSA *key, void *data, int datasz, struct sig_v1 *sig,
738 evp_key = EVP_PKEY_new();
740 return openssl_err("EVP_PKEY object creation failed");
742 if (!EVP_PKEY_set1_RSA(evp_key, key)) {
743 ret = openssl_err("EVP key setup failed");
747 size = EVP_PKEY_size(evp_key);
748 if (size > sizeof(sig->sig)) {
749 fprintf(stderr, "Invalid signature size (%d bytes)\n",
755 ctx = EVP_MD_CTX_create();
757 ret = openssl_err("EVP context creation failed");
760 EVP_MD_CTX_init(ctx);
761 if (!EVP_VerifyInit(ctx, EVP_sha256())) {
762 ret = openssl_err("Verifier setup failed");
766 if (!EVP_VerifyUpdate(ctx, data, datasz)) {
767 ret = openssl_err("Hashing data failed");
771 if (EVP_VerifyFinal(ctx, sig->sig, sizeof(sig->sig), evp_key) != 1) {
772 ret = openssl_err("Could not verify signature");
776 EVP_MD_CTX_cleanup(ctx);
777 EVP_MD_CTX_destroy(ctx);
778 EVP_PKEY_free(evp_key);
783 EVP_MD_CTX_destroy(ctx);
785 EVP_PKEY_free(evp_key);
786 fprintf(stderr, "Failed to verify %s signature\n", signame);
790 static int kwb_sign_and_verify(RSA *key, void *data, int datasz,
791 struct sig_v1 *sig, char *signame)
793 if (kwb_sign(key, data, datasz, sig, signame) < 0)
796 if (kwb_verify(key, data, datasz, sig, signame) < 0)
803 static int kwb_dump_fuse_cmds_38x(FILE *out, struct secure_hdr_v1 *sec_hdr)
805 struct hash_v1 kak_pub_hash;
806 struct image_cfg_element *e;
807 unsigned int fuse_line;
813 if (!out || !sec_hdr)
816 ret = kwb_compute_pubkey_hash(&sec_hdr->kak, &kak_pub_hash);
820 fprintf(out, "# burn KAK pub key hash\n");
821 ptr = kak_pub_hash.hash;
822 for (fuse_line = 26; fuse_line <= 30; ++fuse_line) {
823 fprintf(out, "fuse prog -y %u 0 ", fuse_line);
825 for (i = 4; i-- > 0;)
826 fprintf(out, "%02hx", (ushort)ptr[i]);
830 if (fuse_line < 30) {
831 for (i = 3; i-- > 0;)
832 fprintf(out, "%02hx", (ushort)ptr[i]);
835 fprintf(out, "000000");
838 fprintf(out, " 1\n");
841 fprintf(out, "# burn CSK selection\n");
843 idx = image_get_csk_index();
844 if (idx < 0 || idx > 15) {
849 for (fuse_line = 31; fuse_line < 31 + idx; ++fuse_line)
850 fprintf(out, "fuse prog -y %u 0 00000001 00000000 1\n",
853 fprintf(out, "# CSK index is 0; no mods needed\n");
856 e = image_find_option(IMAGE_CFG_BOX_ID);
858 fprintf(out, "# set box ID\n");
859 fprintf(out, "fuse prog -y 48 0 %08x 00000000 1\n", e->boxid);
862 e = image_find_option(IMAGE_CFG_FLASH_ID);
864 fprintf(out, "# set flash ID\n");
865 fprintf(out, "fuse prog -y 47 0 %08x 00000000 1\n", e->flashid);
868 fprintf(out, "# enable secure mode ");
869 fprintf(out, "(must be the last fuse line written)\n");
872 e = image_find_option(IMAGE_CFG_SEC_BOOT_DEV);
874 fprintf(stderr, "ERROR: secured mode boot device not given\n");
879 if (e->sec_boot_dev > 0xff) {
880 fprintf(stderr, "ERROR: secured mode boot device invalid\n");
885 val |= (e->sec_boot_dev << 8);
887 fprintf(out, "fuse prog -y 24 0 %08x 0103e0a9 1\n", val);
889 fprintf(out, "# lock (unused) fuse lines (0-23)s\n");
890 for (fuse_line = 0; fuse_line < 24; ++fuse_line)
891 fprintf(out, "fuse prog -y %u 2 1\n", fuse_line);
893 fprintf(out, "# OK, that's all :-)\n");
899 static int kwb_dump_fuse_cmds(struct secure_hdr_v1 *sec_hdr)
902 struct image_cfg_element *e;
904 e = image_find_option(IMAGE_CFG_SEC_FUSE_DUMP);
908 if (!strcmp(e->name, "a38x")) {
909 FILE *out = fopen("kwb_fuses_a38x.txt", "w+");
912 fprintf(stderr, "Couldn't open eFuse settings: '%s': %s\n",
913 "kwb_fuses_a38x.txt", strerror(errno));
917 kwb_dump_fuse_cmds_38x(out, sec_hdr);
928 static size_t image_headersz_align(size_t headersz, uint8_t blockid)
931 * Header needs to be 4-byte aligned, which is already ensured by code
932 * above. Moreover UART images must have header aligned to 128 bytes
933 * (xmodem block size), NAND images to 256 bytes (ECC calculation),
934 * and SATA and SDIO images to 512 bytes (storage block size).
935 * Note that SPI images do not have to have header size aligned
936 * to 256 bytes because it is possible to read from SPI storage from
937 * any offset (read offset does not have to be aligned to block size).
939 if (blockid == IBR_HDR_UART_ID)
940 return ALIGN(headersz, 128);
941 else if (blockid == IBR_HDR_NAND_ID)
942 return ALIGN(headersz, 256);
943 else if (blockid == IBR_HDR_SATA_ID || blockid == IBR_HDR_SDIO_ID)
944 return ALIGN(headersz, 512);
949 static size_t image_headersz_v0(int *hasext)
953 headersz = sizeof(struct main_hdr_v0);
954 if (image_count_options(IMAGE_CFG_DATA) > 0) {
955 headersz += sizeof(struct ext_hdr_v0);
960 return image_headersz_align(headersz, image_get_bootfrom());
963 static void *image_create_v0(size_t *imagesz, struct image_tool_params *params,
966 struct image_cfg_element *e;
968 struct main_hdr_v0 *main_hdr;
973 * Calculate the size of the header and the size of the
976 headersz = image_headersz_v0(&has_ext);
978 image = malloc(headersz);
980 fprintf(stderr, "Cannot allocate memory for image\n");
984 memset(image, 0, headersz);
986 main_hdr = (struct main_hdr_v0 *)image;
988 /* Fill in the main header */
989 main_hdr->blocksize =
990 cpu_to_le32(payloadsz);
991 main_hdr->srcaddr = cpu_to_le32(headersz);
992 main_hdr->ext = has_ext;
993 main_hdr->version = 0;
994 main_hdr->destaddr = cpu_to_le32(params->addr);
995 main_hdr->execaddr = cpu_to_le32(params->ep);
996 main_hdr->blockid = image_get_bootfrom();
998 e = image_find_option(IMAGE_CFG_NAND_ECC_MODE);
1000 main_hdr->nandeccmode = e->nandeccmode;
1001 e = image_find_option(IMAGE_CFG_NAND_PAGESZ);
1003 main_hdr->nandpagesize = cpu_to_le16(e->nandpagesz);
1004 main_hdr->checksum = image_checksum8(image,
1005 sizeof(struct main_hdr_v0));
1008 * For SATA srcaddr is specified in number of sectors starting from
1009 * sector 0. The main header is stored at sector number 1.
1010 * This expects the sector size to be 512 bytes.
1011 * Header size is already aligned.
1013 if (main_hdr->blockid == IBR_HDR_SATA_ID)
1014 main_hdr->srcaddr = cpu_to_le32(headersz / 512 + 1);
1017 * For SDIO srcaddr is specified in number of sectors starting from
1018 * sector 0. The main header is stored at sector number 0.
1019 * This expects sector size to be 512 bytes.
1020 * Header size is already aligned.
1022 if (main_hdr->blockid == IBR_HDR_SDIO_ID)
1023 main_hdr->srcaddr = cpu_to_le32(headersz / 512);
1025 /* For PCIe srcaddr is not used and must be set to 0xFFFFFFFF. */
1026 if (main_hdr->blockid == IBR_HDR_PEX_ID)
1027 main_hdr->srcaddr = cpu_to_le32(0xFFFFFFFF);
1029 /* Generate the ext header */
1031 struct ext_hdr_v0 *ext_hdr;
1034 ext_hdr = (struct ext_hdr_v0 *)
1035 (image + sizeof(struct main_hdr_v0));
1036 ext_hdr->offset = cpu_to_le32(0x40);
1038 for (cfgi = 0, datai = 0; cfgi < cfgn; cfgi++) {
1039 e = &image_cfg[cfgi];
1040 if (e->type != IMAGE_CFG_DATA)
1043 ext_hdr->rcfg[datai].raddr =
1044 cpu_to_le32(e->regdata.raddr);
1045 ext_hdr->rcfg[datai].rdata =
1046 cpu_to_le32(e->regdata.rdata);
1050 ext_hdr->checksum = image_checksum8(ext_hdr,
1051 sizeof(struct ext_hdr_v0));
1054 *imagesz = headersz;
1058 static size_t image_headersz_v1(int *hasext)
1060 struct image_cfg_element *e;
1069 * Calculate the size of the header and the size of the
1072 headersz = sizeof(struct main_hdr_v1);
1074 if (image_get_csk_index() >= 0) {
1075 headersz += sizeof(struct secure_hdr_v1);
1080 cpu_sheeva = image_is_cpu_sheeva();
1083 for (cfgi = 0; cfgi < cfgn; cfgi++) {
1084 e = &image_cfg[cfgi];
1086 if (e->type == IMAGE_CFG_DATA)
1089 if (e->type == IMAGE_CFG_DATA_DELAY ||
1090 (e->type == IMAGE_CFG_BINARY && count > 0)) {
1091 headersz += sizeof(struct register_set_hdr_v1) + 8 * count + 4;
1095 if (e->type != IMAGE_CFG_BINARY)
1098 ret = stat(e->binary.file, &s);
1103 memset(cwd, 0, sizeof(cwd));
1104 if (!getcwd(cwd, sizeof(cwd))) {
1105 dir = "current working directory";
1106 perror("getcwd() failed");
1110 "Didn't find the file '%s' in '%s' which is mandatory to generate the image\n"
1111 "This file generally contains the DDR3 training code, and should be extracted from an existing bootable\n"
1112 "image for your board. Use 'dumpimage -T kwbimage -p 0' to extract it from an existing image.\n",
1113 e->binary.file, dir);
1117 headersz += sizeof(struct opt_hdr_v1) + sizeof(uint32_t) +
1118 (e->binary.nargs) * sizeof(uint32_t);
1120 if (e->binary.loadaddr) {
1122 * BootROM loads kwbimage header (in which the
1123 * executable code is also stored) to address
1124 * 0x40004000 or 0x40000000. Thus there is
1125 * restriction for the load address of the N-th
1128 unsigned int base_addr, low_addr, high_addr;
1130 base_addr = cpu_sheeva ? 0x40004000 : 0x40000000;
1131 low_addr = base_addr + headersz;
1132 high_addr = low_addr +
1133 (BINARY_MAX_ARGS - e->binary.nargs) * sizeof(uint32_t);
1135 if (cpu_sheeva && e->binary.loadaddr % 16) {
1137 "Invalid LOAD_ADDRESS 0x%08x for BINARY %s with %d args.\n"
1138 "Address for CPU SHEEVA must be 16-byte aligned.\n",
1139 e->binary.loadaddr, e->binary.file, e->binary.nargs);
1143 if (e->binary.loadaddr % 4 || e->binary.loadaddr < low_addr ||
1144 e->binary.loadaddr > high_addr) {
1146 "Invalid LOAD_ADDRESS 0x%08x for BINARY %s with %d args.\n"
1147 "Address must be 4-byte aligned and in range 0x%08x-0x%08x.\n",
1148 e->binary.loadaddr, e->binary.file,
1149 e->binary.nargs, low_addr, high_addr);
1152 headersz = e->binary.loadaddr - base_addr;
1153 } else if (cpu_sheeva) {
1154 headersz = ALIGN(headersz, 16);
1156 headersz = ALIGN(headersz, 4);
1159 headersz += ALIGN(s.st_size, 4) + sizeof(uint32_t);
1165 headersz += sizeof(struct register_set_hdr_v1) + 8 * count + 4;
1167 return image_headersz_align(headersz, image_get_bootfrom());
1170 static int add_binary_header_v1(uint8_t **cur, uint8_t **next_ext,
1171 struct image_cfg_element *binarye,
1172 struct main_hdr_v1 *main_hdr)
1174 struct opt_hdr_v1 *hdr = (struct opt_hdr_v1 *)*cur;
1186 hdr->headertype = OPT_HDR_V1_BINARY_TYPE;
1188 bin = fopen(binarye->binary.file, "r");
1190 fprintf(stderr, "Cannot open binary file %s\n",
1191 binarye->binary.file);
1195 if (fstat(fileno(bin), &s)) {
1196 fprintf(stderr, "Cannot stat binary file %s\n",
1197 binarye->binary.file);
1201 *cur += sizeof(struct opt_hdr_v1);
1203 args = (uint32_t *)*cur;
1204 *args = cpu_to_le32(binarye->binary.nargs);
1206 for (argi = 0; argi < binarye->binary.nargs; argi++)
1207 args[argi] = cpu_to_le32(binarye->binary.args[argi]);
1209 *cur += (binarye->binary.nargs + 1) * sizeof(uint32_t);
1212 * ARM executable code inside the BIN header on platforms with Sheeva
1213 * CPU (A370 and AXP) must always be aligned with the 128-bit boundary.
1214 * In the case when this code is not position independent (e.g. ARM
1215 * SPL), it must be placed at fixed load and execute address.
1216 * This requirement can be met by inserting dummy arguments into
1217 * BIN header, if needed.
1219 cpu_sheeva = image_is_cpu_sheeva();
1220 base_addr = cpu_sheeva ? 0x40004000 : 0x40000000;
1221 offset = *cur - (uint8_t *)main_hdr;
1222 if (binarye->binary.loadaddr)
1223 add_args = (binarye->binary.loadaddr - base_addr - offset) / sizeof(uint32_t);
1224 else if (cpu_sheeva)
1225 add_args = ((16 - offset % 16) % 16) / sizeof(uint32_t);
1229 *(args - 1) = cpu_to_le32(binarye->binary.nargs + add_args);
1230 *cur += add_args * sizeof(uint32_t);
1233 ret = fread(*cur, s.st_size, 1, bin);
1236 "Could not read binary image %s\n",
1237 binarye->binary.file);
1243 *cur += ALIGN(s.st_size, 4);
1245 *((uint32_t *)*cur) = 0x00000000;
1249 *cur += sizeof(uint32_t);
1251 binhdrsz = sizeof(struct opt_hdr_v1) +
1252 (binarye->binary.nargs + add_args + 2) * sizeof(uint32_t) +
1253 ALIGN(s.st_size, 4);
1254 hdr->headersz_lsb = cpu_to_le16(binhdrsz & 0xFFFF);
1255 hdr->headersz_msb = (binhdrsz & 0xFFFF0000) >> 16;
1265 static int export_pub_kak_hash(RSA *kak, struct secure_hdr_v1 *secure_hdr)
1270 hashf = fopen("pub_kak_hash.txt", "w");
1272 fprintf(stderr, "Couldn't open hash file: '%s': %s\n",
1273 "pub_kak_hash.txt", strerror(errno));
1277 res = kwb_export_pubkey(kak, &secure_hdr->kak, hashf, "KAK");
1281 return res < 0 ? 1 : 0;
1284 static int kwb_sign_csk_with_kak(struct image_tool_params *params,
1285 struct secure_hdr_v1 *secure_hdr, RSA *csk)
1288 RSA *kak_pub = NULL;
1289 int csk_idx = image_get_csk_index();
1290 struct sig_v1 tmp_sig;
1292 if (csk_idx < 0 || csk_idx > 15) {
1293 fprintf(stderr, "Invalid CSK index %d\n", csk_idx);
1297 if (kwb_load_kak(params, &kak) < 0)
1300 if (export_pub_kak_hash(kak, secure_hdr))
1303 if (kwb_import_pubkey(&kak_pub, &secure_hdr->kak, "KAK") < 0)
1306 if (kwb_export_pubkey(csk, &secure_hdr->csk[csk_idx], NULL, "CSK") < 0)
1309 if (kwb_sign_and_verify(kak, &secure_hdr->csk,
1310 sizeof(secure_hdr->csk) +
1311 sizeof(secure_hdr->csksig),
1312 &tmp_sig, "CSK") < 0)
1315 if (kwb_verify(kak_pub, &secure_hdr->csk,
1316 sizeof(secure_hdr->csk) +
1317 sizeof(secure_hdr->csksig),
1318 &tmp_sig, "CSK (2)") < 0)
1321 secure_hdr->csksig = tmp_sig;
1326 static int add_secure_header_v1(struct image_tool_params *params, uint8_t *ptr,
1327 int payloadsz, size_t headersz, uint8_t *image,
1328 struct secure_hdr_v1 *secure_hdr)
1330 struct image_cfg_element *e_jtagdelay;
1331 struct image_cfg_element *e_boxid;
1332 struct image_cfg_element *e_flashid;
1334 unsigned char *image_ptr;
1336 struct sig_v1 tmp_sig;
1337 bool specialized_img = image_get_spezialized_img();
1339 kwb_msg("Create secure header content\n");
1341 e_jtagdelay = image_find_option(IMAGE_CFG_JTAG_DELAY);
1342 e_boxid = image_find_option(IMAGE_CFG_BOX_ID);
1343 e_flashid = image_find_option(IMAGE_CFG_FLASH_ID);
1345 if (kwb_load_csk(params, &csk) < 0)
1348 secure_hdr->headertype = OPT_HDR_V1_SECURE_TYPE;
1349 secure_hdr->headersz_msb = 0;
1350 secure_hdr->headersz_lsb = cpu_to_le16(sizeof(struct secure_hdr_v1));
1352 secure_hdr->jtag_delay = e_jtagdelay->jtag_delay;
1353 if (e_boxid && specialized_img)
1354 secure_hdr->boxid = cpu_to_le32(e_boxid->boxid);
1355 if (e_flashid && specialized_img)
1356 secure_hdr->flashid = cpu_to_le32(e_flashid->flashid);
1358 if (kwb_sign_csk_with_kak(params, secure_hdr, csk))
1361 image_ptr = ptr + headersz;
1362 image_size = payloadsz - headersz;
1364 if (kwb_sign_and_verify(csk, image_ptr, image_size,
1365 &secure_hdr->imgsig, "image") < 0)
1368 if (kwb_sign_and_verify(csk, image, headersz, &tmp_sig, "header") < 0)
1371 secure_hdr->hdrsig = tmp_sig;
1373 kwb_dump_fuse_cmds(secure_hdr);
1378 static void finish_register_set_header_v1(uint8_t **cur, uint8_t **next_ext,
1379 struct register_set_hdr_v1 *register_set_hdr,
1380 int *datai, uint8_t delay)
1382 int size = sizeof(struct register_set_hdr_v1) + 8 * (*datai) + 4;
1384 register_set_hdr->headertype = OPT_HDR_V1_REGISTER_TYPE;
1385 register_set_hdr->headersz_lsb = cpu_to_le16(size & 0xFFFF);
1386 register_set_hdr->headersz_msb = size >> 16;
1387 register_set_hdr->data[*datai].last_entry.delay = delay;
1390 *next_ext = ®ister_set_hdr->data[*datai].last_entry.next;
1394 static void *image_create_v1(size_t *imagesz, struct image_tool_params *params,
1395 uint8_t *ptr, int payloadsz)
1397 struct image_cfg_element *e;
1398 struct main_hdr_v1 *main_hdr;
1399 struct opt_hdr_v1 *ohdr;
1400 struct register_set_hdr_v1 *register_set_hdr;
1401 struct secure_hdr_v1 *secure_hdr = NULL;
1403 uint8_t *image, *cur;
1405 uint8_t *next_ext = NULL;
1410 * Calculate the size of the header and the size of the
1413 headersz = image_headersz_v1(&hasext);
1417 image = malloc(headersz);
1419 fprintf(stderr, "Cannot allocate memory for image\n");
1423 memset(image, 0, headersz);
1425 main_hdr = (struct main_hdr_v1 *)image;
1427 cur += sizeof(struct main_hdr_v1);
1428 next_ext = &main_hdr->ext;
1430 /* Fill the main header */
1431 main_hdr->blocksize =
1432 cpu_to_le32(payloadsz);
1433 main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
1434 main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
1435 main_hdr->destaddr = cpu_to_le32(params->addr);
1436 main_hdr->execaddr = cpu_to_le32(params->ep);
1437 main_hdr->srcaddr = cpu_to_le32(headersz);
1438 main_hdr->ext = hasext;
1439 main_hdr->version = 1;
1440 main_hdr->blockid = image_get_bootfrom();
1442 e = image_find_option(IMAGE_CFG_NAND_BLKSZ);
1444 main_hdr->nandblocksize = e->nandblksz / (64 * 1024);
1445 e = image_find_option(IMAGE_CFG_NAND_PAGESZ);
1447 main_hdr->nandpagesize = cpu_to_le16(e->nandpagesz);
1448 e = image_find_option(IMAGE_CFG_NAND_BADBLK_LOCATION);
1450 main_hdr->nandbadblklocation = e->nandbadblklocation;
1451 e = image_find_option(IMAGE_CFG_BAUDRATE);
1453 main_hdr->options |= baudrate_to_option(e->baudrate);
1454 e = image_find_option(IMAGE_CFG_UART_PORT);
1456 main_hdr->options |= (e->uart_port & 3) << 3;
1457 e = image_find_option(IMAGE_CFG_UART_MPP);
1459 main_hdr->options |= (e->uart_mpp & 7) << 5;
1460 e = image_find_option(IMAGE_CFG_DEBUG);
1462 main_hdr->flags = e->debug ? 0x1 : 0;
1465 * For SATA srcaddr is specified in number of sectors starting from
1466 * sector 0. The main header is stored at sector number 1.
1467 * This expects the sector size to be 512 bytes.
1468 * Header size is already aligned.
1470 if (main_hdr->blockid == IBR_HDR_SATA_ID)
1471 main_hdr->srcaddr = cpu_to_le32(headersz / 512 + 1);
1474 * For SDIO srcaddr is specified in number of sectors starting from
1475 * sector 0. The main header is stored at sector number 0.
1476 * This expects sector size to be 512 bytes.
1477 * Header size is already aligned.
1479 if (main_hdr->blockid == IBR_HDR_SDIO_ID)
1480 main_hdr->srcaddr = cpu_to_le32(headersz / 512);
1482 /* For PCIe srcaddr is not used and must be set to 0xFFFFFFFF. */
1483 if (main_hdr->blockid == IBR_HDR_PEX_ID)
1484 main_hdr->srcaddr = cpu_to_le32(0xFFFFFFFF);
1486 if (image_get_csk_index() >= 0) {
1488 * only reserve the space here; we fill the header later since
1489 * we need the header to be complete to compute the signatures
1491 secure_hdr = (struct secure_hdr_v1 *)cur;
1492 cur += sizeof(struct secure_hdr_v1);
1494 next_ext = &secure_hdr->next;
1498 for (cfgi = 0; cfgi < cfgn; cfgi++) {
1499 e = &image_cfg[cfgi];
1500 if (e->type != IMAGE_CFG_DATA &&
1501 e->type != IMAGE_CFG_DATA_DELAY &&
1502 e->type != IMAGE_CFG_BINARY)
1506 register_set_hdr = (struct register_set_hdr_v1 *)cur;
1508 /* If delay is not specified, use the smallest possible value. */
1509 if (e->type == IMAGE_CFG_DATA_DELAY)
1510 delay = e->regdata_delay;
1512 delay = REGISTER_SET_HDR_OPT_DELAY_MS(0);
1515 * DATA_DELAY command is the last entry in the register set
1516 * header and BINARY command inserts new binary header.
1517 * Therefore BINARY command requires to finish register set
1518 * header if some DATA command was specified. And DATA_DELAY
1519 * command automatically finish register set header even when
1520 * there was no DATA command.
1522 if (e->type == IMAGE_CFG_DATA_DELAY ||
1523 (e->type == IMAGE_CFG_BINARY && datai != 0))
1524 finish_register_set_header_v1(&cur, &next_ext, register_set_hdr,
1527 if (e->type == IMAGE_CFG_DATA) {
1528 register_set_hdr->data[datai].entry.address =
1529 cpu_to_le32(e->regdata.raddr);
1530 register_set_hdr->data[datai].entry.value =
1531 cpu_to_le32(e->regdata.rdata);
1535 if (e->type == IMAGE_CFG_BINARY) {
1536 if (add_binary_header_v1(&cur, &next_ext, e, main_hdr))
1541 /* Set delay to the smallest possible value. */
1542 delay = REGISTER_SET_HDR_OPT_DELAY_MS(0);
1543 finish_register_set_header_v1(&cur, &next_ext, register_set_hdr,
1547 if (secure_hdr && add_secure_header_v1(params, ptr, payloadsz + headersz,
1548 headersz, image, secure_hdr))
1551 *imagesz = headersz;
1553 /* Fill the real header size without padding into the main header */
1554 headersz = sizeof(*main_hdr);
1555 for_each_opt_hdr_v1 (ohdr, main_hdr)
1556 headersz += opt_hdr_v1_size(ohdr);
1557 main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
1558 main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
1560 /* Calculate and set the header checksum */
1561 main_hdr->checksum = image_checksum8(main_hdr, headersz);
1566 static int recognize_keyword(char *keyword)
1570 for (kw_id = 1; kw_id < IMAGE_CFG_COUNT; ++kw_id)
1571 if (!strcmp(keyword, id_strs[kw_id]))
1577 static int image_create_config_parse_oneline(char *line,
1578 struct image_cfg_element *el)
1580 char *keyword, *saveptr, *value1, *value2;
1581 char delimiters[] = " \t";
1582 int keyword_id, ret, argi;
1583 char *unknown_msg = "Ignoring unknown line '%s'\n";
1585 keyword = strtok_r(line, delimiters, &saveptr);
1586 keyword_id = recognize_keyword(keyword);
1589 fprintf(stderr, unknown_msg, line);
1593 el->type = keyword_id;
1595 value1 = strtok_r(NULL, delimiters, &saveptr);
1598 fprintf(stderr, "Parameter missing in line '%s'\n", line);
1602 switch (keyword_id) {
1603 case IMAGE_CFG_VERSION:
1604 el->version = atoi(value1);
1607 if (strcmp(value1, "FEROCEON") == 0)
1609 else if (strcmp(value1, "SHEEVA") == 0)
1611 else if (strcmp(value1, "A9") == 0)
1614 fprintf(stderr, "Invalid CPU %s\n", value1);
1618 case IMAGE_CFG_BOOT_FROM:
1619 ret = image_boot_mode_id(value1);
1622 fprintf(stderr, "Invalid boot media '%s'\n", value1);
1627 case IMAGE_CFG_NAND_BLKSZ:
1628 el->nandblksz = strtoul(value1, NULL, 16);
1630 case IMAGE_CFG_NAND_BADBLK_LOCATION:
1631 el->nandbadblklocation = strtoul(value1, NULL, 16);
1633 case IMAGE_CFG_NAND_ECC_MODE:
1634 ret = image_nand_ecc_mode_id(value1);
1637 fprintf(stderr, "Invalid NAND ECC mode '%s'\n", value1);
1640 el->nandeccmode = ret;
1642 case IMAGE_CFG_NAND_PAGESZ:
1643 el->nandpagesz = strtoul(value1, NULL, 16);
1645 case IMAGE_CFG_BINARY:
1648 el->binary.file = strdup(value1);
1650 char *value = strtok_r(NULL, delimiters, &saveptr);
1656 if (!strcmp(value, "LOAD_ADDRESS")) {
1657 value = strtok_r(NULL, delimiters, &saveptr);
1660 "Missing address argument for BINARY LOAD_ADDRESS\n");
1663 el->binary.loadaddr = strtoul(value, &endptr, 16);
1666 "Invalid argument '%s' for BINARY LOAD_ADDRESS\n",
1670 value = strtok_r(NULL, delimiters, &saveptr);
1673 "Unexpected argument '%s' after BINARY LOAD_ADDRESS\n",
1680 el->binary.args[argi] = strtoul(value, &endptr, 16);
1682 fprintf(stderr, "Invalid argument '%s' for BINARY\n", value);
1686 if (argi >= BINARY_MAX_ARGS) {
1688 "Too many arguments for BINARY\n");
1692 el->binary.nargs = argi;
1694 case IMAGE_CFG_DATA:
1695 value2 = strtok_r(NULL, delimiters, &saveptr);
1697 if (!value1 || !value2) {
1699 "Invalid number of arguments for DATA\n");
1703 el->regdata.raddr = strtoul(value1, NULL, 16);
1704 el->regdata.rdata = strtoul(value2, NULL, 16);
1706 case IMAGE_CFG_DATA_DELAY:
1707 if (!strcmp(value1, "SDRAM_SETUP"))
1708 el->regdata_delay = REGISTER_SET_HDR_OPT_DELAY_SDRAM_SETUP;
1710 el->regdata_delay = REGISTER_SET_HDR_OPT_DELAY_MS(strtoul(value1, NULL, 10));
1711 if (el->regdata_delay > 255) {
1712 fprintf(stderr, "Maximal DATA_DELAY is 255\n");
1716 case IMAGE_CFG_BAUDRATE:
1717 el->baudrate = strtoul(value1, NULL, 10);
1719 case IMAGE_CFG_UART_PORT:
1720 el->uart_port = strtoul(value1, NULL, 16);
1722 case IMAGE_CFG_UART_MPP:
1723 el->uart_mpp = strtoul(value1, NULL, 16);
1725 case IMAGE_CFG_DEBUG:
1726 el->debug = strtoul(value1, NULL, 10);
1729 el->key_name = strdup(value1);
1732 el->key_name = strdup(value1);
1734 case IMAGE_CFG_CSK_INDEX:
1735 el->csk_idx = strtol(value1, NULL, 0);
1737 case IMAGE_CFG_JTAG_DELAY:
1738 el->jtag_delay = strtoul(value1, NULL, 0);
1740 case IMAGE_CFG_BOX_ID:
1741 el->boxid = strtoul(value1, NULL, 0);
1743 case IMAGE_CFG_FLASH_ID:
1744 el->flashid = strtoul(value1, NULL, 0);
1746 case IMAGE_CFG_SEC_SPECIALIZED_IMG:
1747 el->sec_specialized_img = true;
1749 case IMAGE_CFG_SEC_COMMON_IMG:
1750 el->sec_specialized_img = false;
1752 case IMAGE_CFG_SEC_BOOT_DEV:
1753 el->sec_boot_dev = strtoul(value1, NULL, 0);
1755 case IMAGE_CFG_SEC_FUSE_DUMP:
1756 el->name = strdup(value1);
1759 fprintf(stderr, unknown_msg, line);
1766 * Parse the configuration file 'fcfg' into the array of configuration
1767 * elements 'image_cfg', and return the number of configuration
1768 * elements in 'cfgn'.
1770 static int image_create_config_parse(FILE *fcfg)
1775 /* Parse the configuration file */
1776 while (!feof(fcfg)) {
1780 /* Read the current line */
1781 memset(buf, 0, sizeof(buf));
1782 line = fgets(buf, sizeof(buf), fcfg);
1786 /* Ignore useless lines */
1787 if (line[0] == '\n' || line[0] == '#')
1790 /* Strip final newline */
1791 if (line[strlen(line) - 1] == '\n')
1792 line[strlen(line) - 1] = 0;
1794 /* Parse the current line */
1795 ret = image_create_config_parse_oneline(line,
1802 if (cfgi >= IMAGE_CFG_ELEMENT_MAX) {
1804 "Too many configuration elements in .cfg file\n");
1813 static int image_get_version(void)
1815 struct image_cfg_element *e;
1817 e = image_find_option(IMAGE_CFG_VERSION);
1824 static void kwbimage_set_header(void *ptr, struct stat *sbuf, int ifd,
1825 struct image_tool_params *params)
1830 size_t headersz = 0;
1837 * Do not use sbuf->st_size as it contains size with padding.
1838 * We need original image data size, so stat original file.
1840 if (stat(params->datafile, &s)) {
1841 fprintf(stderr, "Could not stat data file %s: %s\n",
1842 params->datafile, strerror(errno));
1845 datasz = ALIGN(s.st_size, 4);
1847 fcfg = fopen(params->imagename, "r");
1849 fprintf(stderr, "Could not open input file %s\n",
1854 image_cfg = malloc(IMAGE_CFG_ELEMENT_MAX *
1855 sizeof(struct image_cfg_element));
1857 fprintf(stderr, "Cannot allocate memory\n");
1862 memset(image_cfg, 0,
1863 IMAGE_CFG_ELEMENT_MAX * sizeof(struct image_cfg_element));
1866 ret = image_create_config_parse(fcfg);
1873 version = image_get_version();
1876 * Fallback to version 0 if no version is provided in the
1881 image = image_create_v0(&headersz, params, datasz + 4);
1885 image = image_create_v1(&headersz, params, ptr, datasz + 4);
1889 fprintf(stderr, "Unsupported version %d\n", version);
1895 fprintf(stderr, "Could not create image\n");
1902 /* Build and add image data checksum */
1903 checksum = cpu_to_le32(image_checksum32((uint8_t *)ptr + headersz,
1905 memcpy((uint8_t *)ptr + headersz + datasz, &checksum, sizeof(uint32_t));
1907 /* Finally copy the header into the image area */
1908 memcpy(ptr, image, headersz);
1913 static void kwbimage_print_header(const void *ptr)
1915 struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr;
1916 struct bin_hdr_v0 *bhdr;
1917 struct opt_hdr_v1 *ohdr;
1919 printf("Image Type: MVEBU Boot from %s Image\n",
1920 image_boot_mode_name(mhdr->blockid));
1921 printf("Image version:%d\n", kwbimage_version(ptr));
1923 for_each_opt_hdr_v1 (ohdr, mhdr) {
1924 if (ohdr->headertype == OPT_HDR_V1_BINARY_TYPE) {
1925 printf("BIN Img Size: ");
1926 genimg_print_size(opt_hdr_v1_size(ohdr) - 12 -
1928 printf("BIN Img Offs: %08x\n",
1929 (unsigned)((uint8_t *)ohdr - (uint8_t *)mhdr) +
1930 8 + 4 * ohdr->data[0]);
1934 for_each_bin_hdr_v0(bhdr, mhdr) {
1935 printf("BIN Img Size: ");
1936 genimg_print_size(le32_to_cpu(bhdr->size));
1937 printf("BIN Img Addr: %08x\n", le32_to_cpu(bhdr->destaddr));
1938 printf("BIN Img Entr: %08x\n", le32_to_cpu(bhdr->execaddr));
1941 printf("Data Size: ");
1942 genimg_print_size(mhdr->blocksize - sizeof(uint32_t));
1943 printf("Load Address: %08x\n", mhdr->destaddr);
1944 printf("Entry Point: %08x\n", mhdr->execaddr);
1947 static int kwbimage_check_image_types(uint8_t type)
1949 if (type == IH_TYPE_KWBIMAGE)
1950 return EXIT_SUCCESS;
1952 return EXIT_FAILURE;
1955 static int kwbimage_verify_header(unsigned char *ptr, int image_size,
1956 struct image_tool_params *params)
1958 size_t header_size = kwbheader_size(ptr);
1964 if (header_size > image_size)
1965 return -FDT_ERR_BADSTRUCTURE;
1967 if (!main_hdr_checksum_ok(ptr))
1968 return -FDT_ERR_BADSTRUCTURE;
1970 /* Only version 0 extended header has checksum */
1971 if (kwbimage_version(ptr) == 0) {
1972 struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr;
1973 struct ext_hdr_v0 *ext_hdr;
1974 struct bin_hdr_v0 *bhdr;
1976 for_each_ext_hdr_v0(ext_hdr, ptr) {
1977 csum = image_checksum8(ext_hdr, sizeof(*ext_hdr) - 1);
1978 if (csum != ext_hdr->checksum)
1979 return -FDT_ERR_BADSTRUCTURE;
1982 for_each_bin_hdr_v0(bhdr, ptr) {
1983 csum = image_checksum8(bhdr, (uint8_t *)&bhdr->checksum - (uint8_t *)bhdr - 1);
1984 if (csum != bhdr->checksum)
1985 return -FDT_ERR_BADSTRUCTURE;
1987 if (bhdr->offset > sizeof(*bhdr) || bhdr->offset % 4 != 0)
1988 return -FDT_ERR_BADSTRUCTURE;
1990 if (bhdr->offset + bhdr->size + 4 > sizeof(*bhdr) || bhdr->size % 4 != 0)
1991 return -FDT_ERR_BADSTRUCTURE;
1993 if (image_checksum32((uint8_t *)bhdr + bhdr->offset, bhdr->size) !=
1994 *(uint32_t *)((uint8_t *)bhdr + bhdr->offset + bhdr->size))
1995 return -FDT_ERR_BADSTRUCTURE;
1998 blockid = mhdr->blockid;
1999 offset = le32_to_cpu(mhdr->srcaddr);
2000 size = le32_to_cpu(mhdr->blocksize);
2001 } else if (kwbimage_version(ptr) == 1) {
2002 struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
2003 const uint8_t *mhdr_end;
2004 struct opt_hdr_v1 *ohdr;
2006 mhdr_end = (uint8_t *)mhdr + header_size;
2007 for_each_opt_hdr_v1 (ohdr, ptr)
2008 if (!opt_hdr_v1_valid_size(ohdr, mhdr_end))
2009 return -FDT_ERR_BADSTRUCTURE;
2011 blockid = mhdr->blockid;
2012 offset = le32_to_cpu(mhdr->srcaddr);
2013 size = le32_to_cpu(mhdr->blocksize);
2015 return -FDT_ERR_BADSTRUCTURE;
2019 * For SATA srcaddr is specified in number of sectors.
2020 * The main header is must be stored at sector number 1.
2021 * This expects that sector size is 512 bytes and recalculates
2022 * data offset to bytes relative to the main header.
2024 if (blockid == IBR_HDR_SATA_ID) {
2026 return -FDT_ERR_BADSTRUCTURE;
2032 * For SDIO srcaddr is specified in number of sectors.
2033 * This expects that sector size is 512 bytes and recalculates
2034 * data offset to bytes.
2036 if (blockid == IBR_HDR_SDIO_ID)
2040 * For PCIe srcaddr is always set to 0xFFFFFFFF.
2041 * This expects that data starts after all headers.
2043 if (blockid == IBR_HDR_PEX_ID && offset == 0xFFFFFFFF)
2044 offset = header_size;
2046 if (offset > image_size || offset % 4 != 0)
2047 return -FDT_ERR_BADSTRUCTURE;
2049 if (size < 4 || offset + size > image_size || size % 4 != 0)
2050 return -FDT_ERR_BADSTRUCTURE;
2052 if (image_checksum32(ptr + offset, size - 4) !=
2053 *(uint32_t *)(ptr + offset + size - 4))
2054 return -FDT_ERR_BADSTRUCTURE;
2059 static int kwbimage_generate(struct image_tool_params *params,
2060 struct image_type_params *tparams)
2070 fcfg = fopen(params->imagename, "r");
2072 fprintf(stderr, "Could not open input file %s\n",
2077 if (stat(params->datafile, &s)) {
2078 fprintf(stderr, "Could not stat data file %s: %s\n",
2079 params->datafile, strerror(errno));
2083 image_cfg = malloc(IMAGE_CFG_ELEMENT_MAX *
2084 sizeof(struct image_cfg_element));
2086 fprintf(stderr, "Cannot allocate memory\n");
2091 memset(image_cfg, 0,
2092 IMAGE_CFG_ELEMENT_MAX * sizeof(struct image_cfg_element));
2095 ret = image_create_config_parse(fcfg);
2102 bootfrom = image_get_bootfrom();
2103 version = image_get_version();
2106 * Fallback to version 0 if no version is provided in the
2111 alloc_len = image_headersz_v0(NULL);
2115 alloc_len = image_headersz_v1(NULL);
2120 if (alloc_len > 192*1024) {
2121 fprintf(stderr, "Header is too big (%u bytes), maximal kwbimage header size is %u bytes\n", alloc_len, 192*1024);
2128 fprintf(stderr, "Unsupported version %d\n", version);
2135 hdr = malloc(alloc_len);
2137 fprintf(stderr, "%s: malloc return failure: %s\n",
2138 params->cmdname, strerror(errno));
2142 memset(hdr, 0, alloc_len);
2143 tparams->header_size = alloc_len;
2147 * The resulting image needs to be 4-byte aligned. At least
2148 * the Marvell hdrparser tool complains if its unaligned.
2149 * After the image data is stored 4-byte checksum.
2150 * Final UART image must be aligned to 128 bytes.
2151 * Final SPI and NAND images must be aligned to 256 bytes.
2152 * Final SATA and SDIO images must be aligned to 512 bytes.
2154 if (bootfrom == IBR_HDR_SPI_ID || bootfrom == IBR_HDR_NAND_ID)
2155 return 4 + (256 - (alloc_len + s.st_size + 4) % 256) % 256;
2156 else if (bootfrom == IBR_HDR_SATA_ID || bootfrom == IBR_HDR_SDIO_ID)
2157 return 4 + (512 - (alloc_len + s.st_size + 4) % 512) % 512;
2158 else if (bootfrom == IBR_HDR_UART_ID)
2159 return 4 + (128 - (alloc_len + s.st_size + 4) % 128) % 128;
2161 return 4 + (4 - s.st_size % 4) % 4;
2164 static int kwbimage_generate_config(void *ptr, struct image_tool_params *params)
2166 struct main_hdr_v0 *mhdr0 = (struct main_hdr_v0 *)ptr;
2167 struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
2168 size_t header_size = kwbheader_size(ptr);
2169 struct register_set_hdr_v1 *regset_hdr;
2170 struct ext_hdr_v0_reg *regdata;
2171 struct ext_hdr_v0 *ehdr0;
2172 struct bin_hdr_v0 *bhdr0;
2173 struct opt_hdr_v1 *ohdr;
2182 f = fopen(params->outfile, "w");
2184 fprintf(stderr, "Can't open \"%s\": %s\n", params->outfile, strerror(errno));
2188 version = kwbimage_version(ptr);
2192 if (mhdr0->ext > 1 || mhdr0->bin ||
2193 ((ehdr0 = ext_hdr_v0_first(ptr)) &&
2194 (ehdr0->match_addr || ehdr0->match_mask || ehdr0->match_value)))
2199 fprintf(f, "VERSION %d\n", version);
2201 fprintf(f, "BOOT_FROM %s\n", image_boot_mode_name(mhdr->blockid) ?: "<unknown>");
2203 if (version == 0 && mhdr->blockid == IBR_HDR_NAND_ID)
2204 fprintf(f, "NAND_ECC_MODE %s\n", image_nand_ecc_mode_name(mhdr0->nandeccmode));
2206 if (mhdr->blockid == IBR_HDR_NAND_ID)
2207 fprintf(f, "NAND_PAGE_SIZE 0x%x\n", (unsigned)mhdr->nandpagesize);
2209 if (version != 0 && mhdr->blockid == IBR_HDR_NAND_ID)
2210 fprintf(f, "NAND_BLKSZ 0x%x\n", (unsigned)mhdr->nandblocksize);
2212 if (mhdr->blockid == IBR_HDR_NAND_ID && (mhdr->nandbadblklocation != 0 || is_v0_ext))
2213 fprintf(f, "NAND_BADBLK_LOCATION 0x%x\n", (unsigned)mhdr->nandbadblklocation);
2215 if (version == 0 && mhdr->blockid == IBR_HDR_SATA_ID)
2216 fprintf(f, "SATA_PIO_MODE %u\n", (unsigned)mhdr0->satapiomode);
2219 * Addresses and sizes which are specified by mkimage command line
2220 * arguments and not in kwbimage config file
2224 fprintf(f, "#HEADER_SIZE 0x%x\n",
2225 ((unsigned)mhdr->headersz_msb << 8) | le16_to_cpu(mhdr->headersz_lsb));
2227 fprintf(f, "#SRC_ADDRESS 0x%x\n", le32_to_cpu(mhdr->srcaddr));
2228 fprintf(f, "#BLOCK_SIZE 0x%x\n", le32_to_cpu(mhdr->blocksize));
2229 fprintf(f, "#DEST_ADDRESS 0x%08x\n", le32_to_cpu(mhdr->destaddr));
2230 fprintf(f, "#EXEC_ADDRESS 0x%08x\n", le32_to_cpu(mhdr->execaddr));
2233 if (options_to_baudrate(mhdr->options))
2234 fprintf(f, "BAUDRATE %u\n", options_to_baudrate(mhdr->options));
2235 if (options_to_baudrate(mhdr->options) ||
2236 ((mhdr->options >> 3) & 0x3) || ((mhdr->options >> 5) & 0x7)) {
2237 fprintf(f, "UART_PORT %u\n", (unsigned)((mhdr->options >> 3) & 0x3));
2238 fprintf(f, "UART_MPP 0x%x\n", (unsigned)((mhdr->options >> 5) & 0x7));
2240 if (mhdr->flags & 0x1)
2241 fprintf(f, "DEBUG 1\n");
2245 for_each_opt_hdr_v1(ohdr, ptr) {
2246 if (ohdr->headertype == OPT_HDR_V1_SECURE_TYPE) {
2247 fprintf(f, "#SECURE_HEADER\n");
2248 } else if (ohdr->headertype == OPT_HDR_V1_BINARY_TYPE) {
2249 fprintf(f, "BINARY binary%d.bin", cur_idx);
2250 for (i = 0; i < ohdr->data[0]; i++)
2251 fprintf(f, " 0x%x", le32_to_cpu(((uint32_t *)ohdr->data)[i + 1]));
2252 offset = (unsigned)((uint8_t *)ohdr - (uint8_t *)mhdr) + 8 + 4 * ohdr->data[0];
2253 fprintf(f, " LOAD_ADDRESS 0x%08x\n", 0x40000000 + offset);
2254 fprintf(f, " # for CPU SHEEVA: LOAD_ADDRESS 0x%08x\n", 0x40004000 + offset);
2256 } else if (ohdr->headertype == OPT_HDR_V1_REGISTER_TYPE) {
2257 regset_hdr = (struct register_set_hdr_v1 *)ohdr;
2259 i < opt_hdr_v1_size(ohdr) - sizeof(struct opt_hdr_v1) -
2260 sizeof(regset_hdr->data[0].last_entry);
2262 fprintf(f, "DATA 0x%08x 0x%08x\n",
2263 le32_to_cpu(regset_hdr->data[i].entry.address),
2264 le32_to_cpu(regset_hdr->data[i].entry.value));
2265 if (opt_hdr_v1_size(ohdr) - sizeof(struct opt_hdr_v1) >=
2266 sizeof(regset_hdr->data[0].last_entry)) {
2267 if (regset_hdr->data[0].last_entry.delay)
2268 fprintf(f, "DATA_DELAY %u\n",
2269 (unsigned)regset_hdr->data[0].last_entry.delay);
2271 fprintf(f, "DATA_DELAY SDRAM_SETUP\n");
2276 if (version == 0 && !is_v0_ext && le16_to_cpu(mhdr0->ddrinitdelay))
2277 fprintf(f, "DDR_INIT_DELAY %u\n", (unsigned)le16_to_cpu(mhdr0->ddrinitdelay));
2279 for_each_ext_hdr_v0(ehdr0, ptr) {
2281 fprintf(f, "\nMATCH ADDRESS 0x%08x MASK 0x%08x VALUE 0x%08x\n",
2282 le32_to_cpu(ehdr0->match_addr),
2283 le32_to_cpu(ehdr0->match_mask),
2284 le32_to_cpu(ehdr0->match_value));
2285 if (ehdr0->rsvd1[0] || ehdr0->rsvd1[1] || ehdr0->rsvd1[2] ||
2286 ehdr0->rsvd1[3] || ehdr0->rsvd1[4] || ehdr0->rsvd1[5] ||
2287 ehdr0->rsvd1[6] || ehdr0->rsvd1[7])
2288 fprintf(f, "#DDR_RSVD1 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
2289 ehdr0->rsvd1[0], ehdr0->rsvd1[1], ehdr0->rsvd1[2],
2290 ehdr0->rsvd1[3], ehdr0->rsvd1[4], ehdr0->rsvd1[5],
2291 ehdr0->rsvd1[6], ehdr0->rsvd1[7]);
2292 if (ehdr0->rsvd2[0] || ehdr0->rsvd2[1] || ehdr0->rsvd2[2] ||
2293 ehdr0->rsvd2[3] || ehdr0->rsvd2[4] || ehdr0->rsvd2[5] ||
2295 fprintf(f, "#DDR_RSVD2 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
2296 ehdr0->rsvd2[0], ehdr0->rsvd2[1], ehdr0->rsvd2[2],
2297 ehdr0->rsvd2[3], ehdr0->rsvd2[4], ehdr0->rsvd2[5],
2299 if (ehdr0->ddrwritetype)
2300 fprintf(f, "DDR_WRITE_TYPE %u\n", (unsigned)ehdr0->ddrwritetype);
2301 if (ehdr0->ddrresetmpp)
2302 fprintf(f, "DDR_RESET_MPP 0x%x\n", (unsigned)ehdr0->ddrresetmpp);
2303 if (ehdr0->ddrclkenmpp)
2304 fprintf(f, "DDR_CLKEN_MPP 0x%x\n", (unsigned)ehdr0->ddrclkenmpp);
2305 if (ehdr0->ddrinitdelay)
2306 fprintf(f, "DDR_INIT_DELAY %u\n", (unsigned)ehdr0->ddrinitdelay);
2309 if (ehdr0->offset) {
2310 for (regdata = (struct ext_hdr_v0_reg *)((uint8_t *)ptr + ehdr0->offset);
2311 (uint8_t *)regdata < (uint8_t *)ptr + header_size &&
2312 (regdata->raddr || regdata->rdata);
2314 fprintf(f, "DATA 0x%08x 0x%08x\n", le32_to_cpu(regdata->raddr),
2315 le32_to_cpu(regdata->rdata));
2316 if ((uint8_t *)regdata != (uint8_t *)ptr + ehdr0->offset)
2317 fprintf(f, "DATA 0x0 0x0\n");
2320 if (le32_to_cpu(ehdr0->enddelay))
2321 fprintf(f, "DATA_DELAY %u\n", le32_to_cpu(ehdr0->enddelay));
2323 fprintf(f, "DATA_DELAY SDRAM_SETUP\n");
2327 for_each_bin_hdr_v0(bhdr0, ptr) {
2328 fprintf(f, "\nMATCH ADDRESS 0x%08x MASK 0x%08x VALUE 0x%08x\n",
2329 le32_to_cpu(bhdr0->match_addr),
2330 le32_to_cpu(bhdr0->match_mask),
2331 le32_to_cpu(bhdr0->match_value));
2333 fprintf(f, "BINARY binary%d.bin", cur_idx);
2334 params_count = fls4(bhdr0->params_flags & 0xF);
2335 for (i = 0; i < params_count; i++)
2336 fprintf(f, " 0x%x", (bhdr0->params[i] & (1 << i)) ? bhdr0->params[i] : 0);
2337 fprintf(f, " LOAD_ADDRESS 0x%08x", le32_to_cpu(bhdr0->destaddr));
2338 fprintf(f, " EXEC_ADDRESS 0x%08x", le32_to_cpu(bhdr0->execaddr));
2341 fprintf(f, "#BINARY_OFFSET 0x%x\n", le32_to_cpu(bhdr0->offset));
2342 fprintf(f, "#BINARY_SIZE 0x%x\n", le32_to_cpu(bhdr0->size));
2345 fprintf(f, "#BINARY_RSVD1 0x%x\n", (unsigned)bhdr0->rsvd1);
2347 fprintf(f, "#BINARY_RSVD2 0x%x\n", (unsigned)bhdr0->rsvd2);
2352 /* Undocumented reserved fields */
2354 if (version == 0 && (mhdr0->rsvd1[0] || mhdr0->rsvd1[1] || mhdr0->rsvd1[2]))
2355 fprintf(f, "#RSVD1 0x%x 0x%x 0x%x\n", (unsigned)mhdr0->rsvd1[0],
2356 (unsigned)mhdr0->rsvd1[1], (unsigned)mhdr0->rsvd1[2]);
2358 if (version == 0 && le16_to_cpu(mhdr0->rsvd2))
2359 fprintf(f, "#RSVD2 0x%x\n", (unsigned)le16_to_cpu(mhdr0->rsvd2));
2361 if (version != 0 && mhdr->reserved4)
2362 fprintf(f, "#RESERVED4 0x%x\n", (unsigned)mhdr->reserved4);
2364 if (version != 0 && mhdr->reserved5)
2365 fprintf(f, "#RESERVED5 0x%x\n", (unsigned)le16_to_cpu(mhdr->reserved5));
2372 static int kwbimage_extract_subimage(void *ptr, struct image_tool_params *params)
2374 struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
2375 size_t header_size = kwbheader_size(ptr);
2376 struct bin_hdr_v0 *bhdr;
2377 struct opt_hdr_v1 *ohdr;
2378 int idx = params->pflag;
2384 /* Generate kwbimage config file when '-p -1' is specified */
2386 return kwbimage_generate_config(ptr, params);
2392 /* Extract data image when -p is not specified or when '-p 0' is specified */
2393 offset = le32_to_cpu(mhdr->srcaddr);
2395 if (mhdr->blockid == IBR_HDR_SATA_ID) {
2400 if (mhdr->blockid == IBR_HDR_SDIO_ID)
2403 if (mhdr->blockid == IBR_HDR_PEX_ID && offset == 0xFFFFFFFF)
2404 offset = header_size;
2406 image = (ulong)((uint8_t *)ptr + offset);
2407 size = le32_to_cpu(mhdr->blocksize) - 4;
2409 /* Extract N-th binary header executabe image when other '-p N' is specified */
2411 for_each_opt_hdr_v1(ohdr, ptr) {
2412 if (ohdr->headertype != OPT_HDR_V1_BINARY_TYPE)
2415 if (idx == cur_idx) {
2416 image = (ulong)&ohdr->data[4 + 4 * ohdr->data[0]];
2417 size = opt_hdr_v1_size(ohdr) - 12 - 4 * ohdr->data[0];
2423 for_each_bin_hdr_v0(bhdr, ptr) {
2424 if (idx == cur_idx) {
2425 image = (ulong)bhdr + bhdr->offset;
2433 fprintf(stderr, "Argument -p %d is invalid\n", idx);
2434 fprintf(stderr, "Available subimages:\n");
2435 fprintf(stderr, " -p -1 - kwbimage config file\n");
2436 fprintf(stderr, " -p 0 - data image\n");
2437 if (cur_idx - 1 > 0)
2438 fprintf(stderr, " -p N - Nth binary header image (totally: %d)\n",
2444 return imagetool_save_subimage(params->outfile, image, size);
2448 * Report Error if xflag is set in addition to default
2450 static int kwbimage_check_params(struct image_tool_params *params)
2452 if (!params->lflag && !params->iflag && !params->pflag &&
2453 (!params->imagename || !strlen(params->imagename))) {
2454 char *msg = "Configuration file for kwbimage creation omitted";
2456 fprintf(stderr, "Error:%s - %s\n", params->cmdname, msg);
2460 return (params->dflag && (params->fflag || params->lflag)) ||
2461 (params->fflag && (params->dflag || params->lflag)) ||
2462 (params->lflag && (params->dflag || params->fflag)) ||
2467 * kwbimage type parameters definition
2471 "Marvell MVEBU Boot Image support",
2474 kwbimage_check_params,
2475 kwbimage_verify_header,
2476 kwbimage_print_header,
2477 kwbimage_set_header,
2478 kwbimage_extract_subimage,
2479 kwbimage_check_image_types,