1 // SPDX-License-Identifier: GPL-2.0+
3 * Image manipulator for Marvell SoCs
4 * supports Kirkwood, Dove, Armada 370, Armada XP, Armada 375, Armada 38x and
7 * (C) Copyright 2013 Thomas Petazzoni
8 * <thomas.petazzoni@free-electrons.com>
10 * (C) Copyright 2022 Pali Rohár <pali@kernel.org>
13 #define OPENSSL_API_COMPAT 0x10101000L
15 #include "imagetool.h"
22 #include <openssl/bn.h>
23 #include <openssl/rsa.h>
24 #include <openssl/pem.h>
25 #include <openssl/err.h>
26 #include <openssl/evp.h>
28 #if OPENSSL_VERSION_NUMBER < 0x10100000L || \
29 (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x2070000fL)
30 static void RSA_get0_key(const RSA *r,
31 const BIGNUM **n, const BIGNUM **e, const BIGNUM **d)
41 #elif !defined(LIBRESSL_VERSION_NUMBER)
42 void EVP_MD_CTX_cleanup(EVP_MD_CTX *ctx)
44 EVP_MD_CTX_reset(ctx);
48 /* fls - find last (most-significant) bit set in 4-bit integer */
49 static inline int fls4(int num)
63 static struct image_cfg_element *image_cfg;
65 static int verbose_mode;
79 struct boot_mode boot_modes[] = {
80 { IBR_HDR_I2C_ID, "i2c" },
81 { IBR_HDR_SPI_ID, "spi" },
82 { IBR_HDR_NAND_ID, "nand" },
83 { IBR_HDR_SATA_ID, "sata" },
84 { IBR_HDR_PEX_ID, "pex" },
85 { IBR_HDR_UART_ID, "uart" },
86 { IBR_HDR_SDIO_ID, "sdio" },
90 struct nand_ecc_mode {
95 struct nand_ecc_mode nand_ecc_modes[] = {
96 { IBR_HDR_ECC_DEFAULT, "default" },
97 { IBR_HDR_ECC_FORCED_HAMMING, "hamming" },
98 { IBR_HDR_ECC_FORCED_RS, "rs" },
99 { IBR_HDR_ECC_DISABLED, "disabled" },
103 /* Used to identify an undefined execution or destination address */
104 #define ADDR_INVALID ((uint32_t)-1)
106 #define BINARY_MAX_ARGS 255
108 /* In-memory representation of a line of the configuration file */
110 enum image_cfg_type {
111 IMAGE_CFG_VERSION = 0x1,
115 IMAGE_CFG_NAND_BLKSZ,
116 IMAGE_CFG_NAND_BADBLK_LOCATION,
117 IMAGE_CFG_NAND_ECC_MODE,
118 IMAGE_CFG_NAND_PAGESZ,
122 IMAGE_CFG_DATA_DELAY,
130 IMAGE_CFG_JTAG_DELAY,
133 IMAGE_CFG_SEC_COMMON_IMG,
134 IMAGE_CFG_SEC_SPECIALIZED_IMG,
135 IMAGE_CFG_SEC_BOOT_DEV,
136 IMAGE_CFG_SEC_FUSE_DUMP,
141 static const char * const id_strs[] = {
142 [IMAGE_CFG_VERSION] = "VERSION",
143 [IMAGE_CFG_BOOT_FROM] = "BOOT_FROM",
144 [IMAGE_CFG_DEST_ADDR] = "DEST_ADDR",
145 [IMAGE_CFG_EXEC_ADDR] = "EXEC_ADDR",
146 [IMAGE_CFG_NAND_BLKSZ] = "NAND_BLKSZ",
147 [IMAGE_CFG_NAND_BADBLK_LOCATION] = "NAND_BADBLK_LOCATION",
148 [IMAGE_CFG_NAND_ECC_MODE] = "NAND_ECC_MODE",
149 [IMAGE_CFG_NAND_PAGESZ] = "NAND_PAGE_SIZE",
150 [IMAGE_CFG_CPU] = "CPU",
151 [IMAGE_CFG_BINARY] = "BINARY",
152 [IMAGE_CFG_DATA] = "DATA",
153 [IMAGE_CFG_DATA_DELAY] = "DATA_DELAY",
154 [IMAGE_CFG_BAUDRATE] = "BAUDRATE",
155 [IMAGE_CFG_UART_PORT] = "UART_PORT",
156 [IMAGE_CFG_UART_MPP] = "UART_MPP",
157 [IMAGE_CFG_DEBUG] = "DEBUG",
158 [IMAGE_CFG_KAK] = "KAK",
159 [IMAGE_CFG_CSK] = "CSK",
160 [IMAGE_CFG_CSK_INDEX] = "CSK_INDEX",
161 [IMAGE_CFG_JTAG_DELAY] = "JTAG_DELAY",
162 [IMAGE_CFG_BOX_ID] = "BOX_ID",
163 [IMAGE_CFG_FLASH_ID] = "FLASH_ID",
164 [IMAGE_CFG_SEC_COMMON_IMG] = "SEC_COMMON_IMG",
165 [IMAGE_CFG_SEC_SPECIALIZED_IMG] = "SEC_SPECIALIZED_IMG",
166 [IMAGE_CFG_SEC_BOOT_DEV] = "SEC_BOOT_DEV",
167 [IMAGE_CFG_SEC_FUSE_DUMP] = "SEC_FUSE_DUMP"
170 struct image_cfg_element {
171 enum image_cfg_type type;
173 unsigned int version;
174 unsigned int cpu_sheeva;
175 unsigned int bootfrom;
178 unsigned int loadaddr;
179 unsigned int args[BINARY_MAX_ARGS];
182 unsigned int dstaddr;
183 unsigned int execaddr;
184 unsigned int nandblksz;
185 unsigned int nandbadblklocation;
186 unsigned int nandeccmode;
187 unsigned int nandpagesz;
188 struct ext_hdr_v0_reg regdata;
189 unsigned int regdata_delay;
190 unsigned int baudrate;
191 unsigned int uart_port;
192 unsigned int uart_mpp;
194 const char *key_name;
199 bool sec_specialized_img;
200 unsigned int sec_boot_dev;
205 #define IMAGE_CFG_ELEMENT_MAX 256
208 * Utility functions to manipulate boot mode and ecc modes (convert
209 * them back and forth between description strings and the
210 * corresponding numerical identifiers).
213 static const char *image_boot_mode_name(unsigned int id)
217 for (i = 0; boot_modes[i].name; i++)
218 if (boot_modes[i].id == id)
219 return boot_modes[i].name;
223 static int image_boot_mode_id(const char *boot_mode_name)
227 for (i = 0; boot_modes[i].name; i++)
228 if (!strcmp(boot_modes[i].name, boot_mode_name))
229 return boot_modes[i].id;
234 static const char *image_nand_ecc_mode_name(unsigned int id)
238 for (i = 0; nand_ecc_modes[i].name; i++)
239 if (nand_ecc_modes[i].id == id)
240 return nand_ecc_modes[i].name;
245 static int image_nand_ecc_mode_id(const char *nand_ecc_mode_name)
249 for (i = 0; nand_ecc_modes[i].name; i++)
250 if (!strcmp(nand_ecc_modes[i].name, nand_ecc_mode_name))
251 return nand_ecc_modes[i].id;
255 static struct image_cfg_element *
256 image_find_option(unsigned int optiontype)
260 for (i = 0; i < cfgn; i++) {
261 if (image_cfg[i].type == optiontype)
262 return &image_cfg[i];
269 image_count_options(unsigned int optiontype)
272 unsigned int count = 0;
274 for (i = 0; i < cfgn; i++)
275 if (image_cfg[i].type == optiontype)
281 static int image_get_csk_index(void)
283 struct image_cfg_element *e;
285 e = image_find_option(IMAGE_CFG_CSK_INDEX);
292 static bool image_get_spezialized_img(void)
294 struct image_cfg_element *e;
296 e = image_find_option(IMAGE_CFG_SEC_SPECIALIZED_IMG);
300 return e->sec_specialized_img;
303 static int image_get_bootfrom(void)
305 struct image_cfg_element *e;
307 e = image_find_option(IMAGE_CFG_BOOT_FROM);
309 /* fallback to SPI if no BOOT_FROM is not provided */
310 return IBR_HDR_SPI_ID;
315 static int image_is_cpu_sheeva(void)
317 struct image_cfg_element *e;
319 e = image_find_option(IMAGE_CFG_CPU);
323 return e->cpu_sheeva;
327 * Compute a 8-bit checksum of a memory area. This algorithm follows
328 * the requirements of the Marvell SoC BootROM specifications.
330 static uint8_t image_checksum8(void *start, uint32_t len)
335 /* check len and return zero checksum if invalid */
348 * Verify checksum over a complete header that includes the checksum field.
349 * Return 1 when OK, otherwise 0.
351 static int main_hdr_checksum_ok(void *hdr)
353 /* Offsets of checksum in v0 and v1 headers are the same */
354 struct main_hdr_v0 *main_hdr = (struct main_hdr_v0 *)hdr;
357 checksum = image_checksum8(hdr, kwbheader_size_for_csum(hdr));
358 /* Calculated checksum includes the header checksum field. Compensate
361 checksum -= main_hdr->checksum;
363 return checksum == main_hdr->checksum;
366 static uint32_t image_checksum32(void *start, uint32_t len)
371 /* check len and return zero checksum if invalid */
375 if (len % sizeof(uint32_t)) {
376 fprintf(stderr, "Length %d is not in multiple of %zu\n",
377 len, sizeof(uint32_t));
384 len -= sizeof(uint32_t);
390 static unsigned int options_to_baudrate(uint8_t options)
392 switch (options & 0x7) {
393 case MAIN_HDR_V1_OPT_BAUD_2400:
395 case MAIN_HDR_V1_OPT_BAUD_4800:
397 case MAIN_HDR_V1_OPT_BAUD_9600:
399 case MAIN_HDR_V1_OPT_BAUD_19200:
401 case MAIN_HDR_V1_OPT_BAUD_38400:
403 case MAIN_HDR_V1_OPT_BAUD_57600:
405 case MAIN_HDR_V1_OPT_BAUD_115200:
407 case MAIN_HDR_V1_OPT_BAUD_DEFAULT:
413 static uint8_t baudrate_to_option(unsigned int baudrate)
417 return MAIN_HDR_V1_OPT_BAUD_2400;
419 return MAIN_HDR_V1_OPT_BAUD_4800;
421 return MAIN_HDR_V1_OPT_BAUD_9600;
423 return MAIN_HDR_V1_OPT_BAUD_19200;
425 return MAIN_HDR_V1_OPT_BAUD_38400;
427 return MAIN_HDR_V1_OPT_BAUD_57600;
429 return MAIN_HDR_V1_OPT_BAUD_115200;
431 return MAIN_HDR_V1_OPT_BAUD_DEFAULT;
435 static void kwb_msg(const char *fmt, ...)
441 vfprintf(stdout, fmt, ap);
446 static int openssl_err(const char *msg)
448 unsigned long ssl_err = ERR_get_error();
450 fprintf(stderr, "%s", msg);
451 fprintf(stderr, ": %s\n",
452 ERR_error_string(ssl_err, 0));
457 static int kwb_load_rsa_key(const char *keydir, const char *name, RSA **p_rsa)
466 snprintf(path, sizeof(path), "%s/%s.key", keydir, name);
467 f = fopen(path, "r");
469 fprintf(stderr, "Couldn't open RSA private key: '%s': %s\n",
470 path, strerror(errno));
474 rsa = PEM_read_RSAPrivateKey(f, 0, NULL, "");
476 openssl_err("Failure reading private key");
486 static int kwb_load_cfg_key(struct image_tool_params *params,
487 unsigned int cfg_option, const char *key_name,
490 struct image_cfg_element *e_key;
496 e_key = image_find_option(cfg_option);
498 fprintf(stderr, "%s not configured\n", key_name);
502 res = kwb_load_rsa_key(params->keydir, e_key->key_name, &key);
504 fprintf(stderr, "Failed to load %s\n", key_name);
513 static int kwb_load_kak(struct image_tool_params *params, RSA **p_kak)
515 return kwb_load_cfg_key(params, IMAGE_CFG_KAK, "KAK", p_kak);
518 static int kwb_load_csk(struct image_tool_params *params, RSA **p_csk)
520 return kwb_load_cfg_key(params, IMAGE_CFG_CSK, "CSK", p_csk);
523 static int kwb_compute_pubkey_hash(struct pubkey_der_v1 *pk,
524 struct hash_v1 *hash)
527 unsigned int key_size;
528 unsigned int hash_size;
531 if (!pk || !hash || pk->key[0] != 0x30 || pk->key[1] != 0x82)
534 key_size = (pk->key[2] << 8) + pk->key[3] + 4;
536 ctx = EVP_MD_CTX_create();
538 return openssl_err("EVP context creation failed");
540 EVP_MD_CTX_init(ctx);
541 if (!EVP_DigestInit(ctx, EVP_sha256())) {
542 ret = openssl_err("Digest setup failed");
546 if (!EVP_DigestUpdate(ctx, pk->key, key_size)) {
547 ret = openssl_err("Hashing data failed");
551 if (!EVP_DigestFinal(ctx, hash->hash, &hash_size)) {
552 ret = openssl_err("Could not obtain hash");
556 EVP_MD_CTX_cleanup(ctx);
559 EVP_MD_CTX_destroy(ctx);
563 static int kwb_import_pubkey(RSA **key, struct pubkey_der_v1 *src, char *keyname)
566 const unsigned char *ptr;
572 rsa = d2i_RSAPublicKey(key, &ptr, sizeof(src->key));
574 openssl_err("error decoding public key");
580 fprintf(stderr, "Failed to decode %s pubkey\n", keyname);
584 static int kwb_export_pubkey(RSA *key, struct pubkey_der_v1 *dst, FILE *hashf,
587 int size_exp, size_mod, size_seq;
588 const BIGNUM *key_e, *key_n;
590 char *errmsg = "Failed to encode %s\n";
592 RSA_get0_key(key, NULL, &key_e, NULL);
593 RSA_get0_key(key, &key_n, NULL, NULL);
595 if (!key || !key_e || !key_n || !dst) {
596 fprintf(stderr, "export pk failed: (%p, %p, %p, %p)",
597 key, key_e, key_n, dst);
598 fprintf(stderr, errmsg, keyname);
603 * According to the specs, the key should be PKCS#1 DER encoded.
604 * But unfortunately the really required encoding seems to be different;
605 * it violates DER...! (But it still conformes to BER.)
606 * (Length always in long form w/ 2 byte length code; no leading zero
607 * when MSB of first byte is set...)
608 * So we cannot use the encoding func provided by OpenSSL and have to
609 * do the encoding manually.
612 size_exp = BN_num_bytes(key_e);
613 size_mod = BN_num_bytes(key_n);
614 size_seq = 4 + size_mod + 4 + size_exp;
616 if (size_mod > 256) {
617 fprintf(stderr, "export pk failed: wrong mod size: %d\n",
619 fprintf(stderr, errmsg, keyname);
623 if (4 + size_seq > sizeof(dst->key)) {
624 fprintf(stderr, "export pk failed: seq too large (%d, %zu)\n",
625 4 + size_seq, sizeof(dst->key));
626 fprintf(stderr, errmsg, keyname);
632 /* PKCS#1 (RFC3447) RSAPublicKey structure */
633 *cur++ = 0x30; /* SEQUENCE */
635 *cur++ = (size_seq >> 8) & 0xFF;
636 *cur++ = size_seq & 0xFF;
638 *cur++ = 0x02; /* INTEGER */
640 *cur++ = (size_mod >> 8) & 0xFF;
641 *cur++ = size_mod & 0xFF;
642 BN_bn2bin(key_n, cur);
645 *cur++ = 0x02; /* INTEGER */
647 *cur++ = (size_exp >> 8) & 0xFF;
648 *cur++ = size_exp & 0xFF;
649 BN_bn2bin(key_e, cur);
652 struct hash_v1 pk_hash;
656 ret = kwb_compute_pubkey_hash(dst, &pk_hash);
658 fprintf(stderr, errmsg, keyname);
662 fprintf(hashf, "SHA256 = ");
663 for (i = 0 ; i < sizeof(pk_hash.hash); ++i)
664 fprintf(hashf, "%02X", pk_hash.hash[i]);
665 fprintf(hashf, "\n");
671 static int kwb_sign(RSA *key, void *data, int datasz, struct sig_v1 *sig,
676 unsigned int sig_size;
680 evp_key = EVP_PKEY_new();
682 return openssl_err("EVP_PKEY object creation failed");
684 if (!EVP_PKEY_set1_RSA(evp_key, key)) {
685 ret = openssl_err("EVP key setup failed");
689 size = EVP_PKEY_size(evp_key);
690 if (size > sizeof(sig->sig)) {
691 fprintf(stderr, "Buffer to small for signature (%d bytes)\n",
697 ctx = EVP_MD_CTX_create();
699 ret = openssl_err("EVP context creation failed");
702 EVP_MD_CTX_init(ctx);
703 if (!EVP_SignInit(ctx, EVP_sha256())) {
704 ret = openssl_err("Signer setup failed");
708 if (!EVP_SignUpdate(ctx, data, datasz)) {
709 ret = openssl_err("Signing data failed");
713 if (!EVP_SignFinal(ctx, sig->sig, &sig_size, evp_key)) {
714 ret = openssl_err("Could not obtain signature");
718 EVP_MD_CTX_cleanup(ctx);
719 EVP_MD_CTX_destroy(ctx);
720 EVP_PKEY_free(evp_key);
725 EVP_MD_CTX_destroy(ctx);
727 EVP_PKEY_free(evp_key);
728 fprintf(stderr, "Failed to create %s signature\n", signame);
732 static int kwb_verify(RSA *key, void *data, int datasz, struct sig_v1 *sig,
740 evp_key = EVP_PKEY_new();
742 return openssl_err("EVP_PKEY object creation failed");
744 if (!EVP_PKEY_set1_RSA(evp_key, key)) {
745 ret = openssl_err("EVP key setup failed");
749 size = EVP_PKEY_size(evp_key);
750 if (size > sizeof(sig->sig)) {
751 fprintf(stderr, "Invalid signature size (%d bytes)\n",
757 ctx = EVP_MD_CTX_create();
759 ret = openssl_err("EVP context creation failed");
762 EVP_MD_CTX_init(ctx);
763 if (!EVP_VerifyInit(ctx, EVP_sha256())) {
764 ret = openssl_err("Verifier setup failed");
768 if (!EVP_VerifyUpdate(ctx, data, datasz)) {
769 ret = openssl_err("Hashing data failed");
773 if (EVP_VerifyFinal(ctx, sig->sig, sizeof(sig->sig), evp_key) != 1) {
774 ret = openssl_err("Could not verify signature");
778 EVP_MD_CTX_cleanup(ctx);
779 EVP_MD_CTX_destroy(ctx);
780 EVP_PKEY_free(evp_key);
785 EVP_MD_CTX_destroy(ctx);
787 EVP_PKEY_free(evp_key);
788 fprintf(stderr, "Failed to verify %s signature\n", signame);
792 static int kwb_sign_and_verify(RSA *key, void *data, int datasz,
793 struct sig_v1 *sig, char *signame)
795 if (kwb_sign(key, data, datasz, sig, signame) < 0)
798 if (kwb_verify(key, data, datasz, sig, signame) < 0)
805 static int kwb_dump_fuse_cmds_38x(FILE *out, struct secure_hdr_v1 *sec_hdr)
807 struct hash_v1 kak_pub_hash;
808 struct image_cfg_element *e;
809 unsigned int fuse_line;
815 if (!out || !sec_hdr)
818 ret = kwb_compute_pubkey_hash(&sec_hdr->kak, &kak_pub_hash);
822 fprintf(out, "# burn KAK pub key hash\n");
823 ptr = kak_pub_hash.hash;
824 for (fuse_line = 26; fuse_line <= 30; ++fuse_line) {
825 fprintf(out, "fuse prog -y %u 0 ", fuse_line);
827 for (i = 4; i-- > 0;)
828 fprintf(out, "%02hx", (ushort)ptr[i]);
832 if (fuse_line < 30) {
833 for (i = 3; i-- > 0;)
834 fprintf(out, "%02hx", (ushort)ptr[i]);
837 fprintf(out, "000000");
840 fprintf(out, " 1\n");
843 fprintf(out, "# burn CSK selection\n");
845 idx = image_get_csk_index();
846 if (idx < 0 || idx > 15) {
851 for (fuse_line = 31; fuse_line < 31 + idx; ++fuse_line)
852 fprintf(out, "fuse prog -y %u 0 00000001 00000000 1\n",
855 fprintf(out, "# CSK index is 0; no mods needed\n");
858 e = image_find_option(IMAGE_CFG_BOX_ID);
860 fprintf(out, "# set box ID\n");
861 fprintf(out, "fuse prog -y 48 0 %08x 00000000 1\n", e->boxid);
864 e = image_find_option(IMAGE_CFG_FLASH_ID);
866 fprintf(out, "# set flash ID\n");
867 fprintf(out, "fuse prog -y 47 0 %08x 00000000 1\n", e->flashid);
870 fprintf(out, "# enable secure mode ");
871 fprintf(out, "(must be the last fuse line written)\n");
874 e = image_find_option(IMAGE_CFG_SEC_BOOT_DEV);
876 fprintf(stderr, "ERROR: secured mode boot device not given\n");
881 if (e->sec_boot_dev > 0xff) {
882 fprintf(stderr, "ERROR: secured mode boot device invalid\n");
887 val |= (e->sec_boot_dev << 8);
889 fprintf(out, "fuse prog -y 24 0 %08x 0103e0a9 1\n", val);
891 fprintf(out, "# lock (unused) fuse lines (0-23)s\n");
892 for (fuse_line = 0; fuse_line < 24; ++fuse_line)
893 fprintf(out, "fuse prog -y %u 2 1\n", fuse_line);
895 fprintf(out, "# OK, that's all :-)\n");
901 static int kwb_dump_fuse_cmds(struct secure_hdr_v1 *sec_hdr)
904 struct image_cfg_element *e;
906 e = image_find_option(IMAGE_CFG_SEC_FUSE_DUMP);
910 if (!strcmp(e->name, "a38x")) {
911 FILE *out = fopen("kwb_fuses_a38x.txt", "w+");
914 fprintf(stderr, "Couldn't open eFuse settings: '%s': %s\n",
915 "kwb_fuses_a38x.txt", strerror(errno));
919 kwb_dump_fuse_cmds_38x(out, sec_hdr);
930 static size_t image_headersz_align(size_t headersz, uint8_t blockid)
933 * Header needs to be 4-byte aligned, which is already ensured by code
934 * above. Moreover UART images must have header aligned to 128 bytes
935 * (xmodem block size), NAND images to 256 bytes (ECC calculation),
936 * and SATA and SDIO images to 512 bytes (storage block size).
937 * Note that SPI images do not have to have header size aligned
938 * to 256 bytes because it is possible to read from SPI storage from
939 * any offset (read offset does not have to be aligned to block size).
941 if (blockid == IBR_HDR_UART_ID)
942 return ALIGN(headersz, 128);
943 else if (blockid == IBR_HDR_NAND_ID)
944 return ALIGN(headersz, 256);
945 else if (blockid == IBR_HDR_SATA_ID || blockid == IBR_HDR_SDIO_ID)
946 return ALIGN(headersz, 512);
951 static size_t image_headersz_v0(int *hasext)
955 headersz = sizeof(struct main_hdr_v0);
956 if (image_count_options(IMAGE_CFG_DATA) > 0) {
957 headersz += sizeof(struct ext_hdr_v0);
962 return image_headersz_align(headersz, image_get_bootfrom());
965 static void *image_create_v0(size_t *imagesz, struct image_tool_params *params,
968 struct image_cfg_element *e;
970 struct main_hdr_v0 *main_hdr;
975 * Calculate the size of the header and the size of the
978 headersz = image_headersz_v0(&has_ext);
980 image = malloc(headersz);
982 fprintf(stderr, "Cannot allocate memory for image\n");
986 memset(image, 0, headersz);
988 main_hdr = (struct main_hdr_v0 *)image;
990 /* Fill in the main header */
991 main_hdr->blocksize =
992 cpu_to_le32(payloadsz);
993 main_hdr->srcaddr = cpu_to_le32(headersz);
994 main_hdr->ext = has_ext;
995 main_hdr->version = 0;
996 main_hdr->destaddr = cpu_to_le32(params->addr);
997 main_hdr->execaddr = cpu_to_le32(params->ep);
998 main_hdr->blockid = image_get_bootfrom();
1000 e = image_find_option(IMAGE_CFG_NAND_ECC_MODE);
1002 main_hdr->nandeccmode = e->nandeccmode;
1003 e = image_find_option(IMAGE_CFG_NAND_BLKSZ);
1005 main_hdr->nandblocksize = e->nandblksz / (64 * 1024);
1006 e = image_find_option(IMAGE_CFG_NAND_PAGESZ);
1008 main_hdr->nandpagesize = cpu_to_le16(e->nandpagesz);
1009 e = image_find_option(IMAGE_CFG_NAND_BADBLK_LOCATION);
1011 main_hdr->nandbadblklocation = e->nandbadblklocation;
1012 main_hdr->checksum = image_checksum8(image,
1013 sizeof(struct main_hdr_v0));
1016 * For SATA srcaddr is specified in number of sectors starting from
1017 * sector 0. The main header is stored at sector number 1.
1018 * This expects the sector size to be 512 bytes.
1019 * Header size is already aligned.
1021 if (main_hdr->blockid == IBR_HDR_SATA_ID)
1022 main_hdr->srcaddr = cpu_to_le32(headersz / 512 + 1);
1025 * For SDIO srcaddr is specified in number of sectors starting from
1026 * sector 0. The main header is stored at sector number 0.
1027 * This expects sector size to be 512 bytes.
1028 * Header size is already aligned.
1030 if (main_hdr->blockid == IBR_HDR_SDIO_ID)
1031 main_hdr->srcaddr = cpu_to_le32(headersz / 512);
1033 /* For PCIe srcaddr is not used and must be set to 0xFFFFFFFF. */
1034 if (main_hdr->blockid == IBR_HDR_PEX_ID)
1035 main_hdr->srcaddr = cpu_to_le32(0xFFFFFFFF);
1037 /* Generate the ext header */
1039 struct ext_hdr_v0 *ext_hdr;
1042 ext_hdr = (struct ext_hdr_v0 *)
1043 (image + sizeof(struct main_hdr_v0));
1044 ext_hdr->offset = cpu_to_le32(0x40);
1046 for (cfgi = 0, datai = 0; cfgi < cfgn; cfgi++) {
1047 e = &image_cfg[cfgi];
1048 if (e->type != IMAGE_CFG_DATA)
1051 ext_hdr->rcfg[datai].raddr =
1052 cpu_to_le32(e->regdata.raddr);
1053 ext_hdr->rcfg[datai].rdata =
1054 cpu_to_le32(e->regdata.rdata);
1058 ext_hdr->checksum = image_checksum8(ext_hdr,
1059 sizeof(struct ext_hdr_v0));
1062 *imagesz = headersz;
1066 static size_t image_headersz_v1(int *hasext)
1068 struct image_cfg_element *e;
1077 * Calculate the size of the header and the size of the
1080 headersz = sizeof(struct main_hdr_v1);
1082 if (image_get_csk_index() >= 0) {
1083 headersz += sizeof(struct secure_hdr_v1);
1088 cpu_sheeva = image_is_cpu_sheeva();
1091 for (cfgi = 0; cfgi < cfgn; cfgi++) {
1092 e = &image_cfg[cfgi];
1094 if (e->type == IMAGE_CFG_DATA)
1097 if (e->type == IMAGE_CFG_DATA_DELAY ||
1098 (e->type == IMAGE_CFG_BINARY && count > 0)) {
1099 headersz += sizeof(struct register_set_hdr_v1) + 8 * count + 4;
1103 if (e->type != IMAGE_CFG_BINARY)
1106 ret = stat(e->binary.file, &s);
1111 memset(cwd, 0, sizeof(cwd));
1112 if (!getcwd(cwd, sizeof(cwd))) {
1113 dir = "current working directory";
1114 perror("getcwd() failed");
1118 "Didn't find the file '%s' in '%s' which is mandatory to generate the image\n"
1119 "This file generally contains the DDR3 training code, and should be extracted from an existing bootable\n"
1120 "image for your board. Use 'dumpimage -T kwbimage -p 1' to extract it from an existing image.\n",
1121 e->binary.file, dir);
1125 headersz += sizeof(struct opt_hdr_v1) + sizeof(uint32_t) +
1126 (e->binary.nargs) * sizeof(uint32_t);
1128 if (e->binary.loadaddr) {
1130 * BootROM loads kwbimage header (in which the
1131 * executable code is also stored) to address
1132 * 0x40004000 or 0x40000000. Thus there is
1133 * restriction for the load address of the N-th
1136 unsigned int base_addr, low_addr, high_addr;
1138 base_addr = cpu_sheeva ? 0x40004000 : 0x40000000;
1139 low_addr = base_addr + headersz;
1140 high_addr = low_addr +
1141 (BINARY_MAX_ARGS - e->binary.nargs) * sizeof(uint32_t);
1143 if (cpu_sheeva && e->binary.loadaddr % 16) {
1145 "Invalid LOAD_ADDRESS 0x%08x for BINARY %s with %d args.\n"
1146 "Address for CPU SHEEVA must be 16-byte aligned.\n",
1147 e->binary.loadaddr, e->binary.file, e->binary.nargs);
1151 if (e->binary.loadaddr % 4 || e->binary.loadaddr < low_addr ||
1152 e->binary.loadaddr > high_addr) {
1154 "Invalid LOAD_ADDRESS 0x%08x for BINARY %s with %d args.\n"
1155 "Address must be 4-byte aligned and in range 0x%08x-0x%08x.\n",
1156 e->binary.loadaddr, e->binary.file,
1157 e->binary.nargs, low_addr, high_addr);
1160 headersz = e->binary.loadaddr - base_addr;
1161 } else if (cpu_sheeva) {
1162 headersz = ALIGN(headersz, 16);
1164 headersz = ALIGN(headersz, 4);
1167 headersz += ALIGN(s.st_size, 4) + sizeof(uint32_t);
1173 headersz += sizeof(struct register_set_hdr_v1) + 8 * count + 4;
1175 return image_headersz_align(headersz, image_get_bootfrom());
1178 static int add_binary_header_v1(uint8_t **cur, uint8_t **next_ext,
1179 struct image_cfg_element *binarye,
1180 struct main_hdr_v1 *main_hdr)
1182 struct opt_hdr_v1 *hdr = (struct opt_hdr_v1 *)*cur;
1194 hdr->headertype = OPT_HDR_V1_BINARY_TYPE;
1196 bin = fopen(binarye->binary.file, "r");
1198 fprintf(stderr, "Cannot open binary file %s\n",
1199 binarye->binary.file);
1203 if (fstat(fileno(bin), &s)) {
1204 fprintf(stderr, "Cannot stat binary file %s\n",
1205 binarye->binary.file);
1209 *cur += sizeof(struct opt_hdr_v1);
1211 args = (uint32_t *)*cur;
1212 *args = cpu_to_le32(binarye->binary.nargs);
1214 for (argi = 0; argi < binarye->binary.nargs; argi++)
1215 args[argi] = cpu_to_le32(binarye->binary.args[argi]);
1217 *cur += (binarye->binary.nargs + 1) * sizeof(uint32_t);
1220 * ARM executable code inside the BIN header on platforms with Sheeva
1221 * CPU (A370 and AXP) must always be aligned with the 128-bit boundary.
1222 * In the case when this code is not position independent (e.g. ARM
1223 * SPL), it must be placed at fixed load and execute address.
1224 * This requirement can be met by inserting dummy arguments into
1225 * BIN header, if needed.
1227 cpu_sheeva = image_is_cpu_sheeva();
1228 base_addr = cpu_sheeva ? 0x40004000 : 0x40000000;
1229 offset = *cur - (uint8_t *)main_hdr;
1230 if (binarye->binary.loadaddr)
1231 add_args = (binarye->binary.loadaddr - base_addr - offset) / sizeof(uint32_t);
1232 else if (cpu_sheeva)
1233 add_args = ((16 - offset % 16) % 16) / sizeof(uint32_t);
1237 *(args - 1) = cpu_to_le32(binarye->binary.nargs + add_args);
1238 *cur += add_args * sizeof(uint32_t);
1241 ret = fread(*cur, s.st_size, 1, bin);
1244 "Could not read binary image %s\n",
1245 binarye->binary.file);
1251 *cur += ALIGN(s.st_size, 4);
1253 *((uint32_t *)*cur) = 0x00000000;
1257 *cur += sizeof(uint32_t);
1259 binhdrsz = sizeof(struct opt_hdr_v1) +
1260 (binarye->binary.nargs + add_args + 2) * sizeof(uint32_t) +
1261 ALIGN(s.st_size, 4);
1262 hdr->headersz_lsb = cpu_to_le16(binhdrsz & 0xFFFF);
1263 hdr->headersz_msb = (binhdrsz & 0xFFFF0000) >> 16;
1273 static int export_pub_kak_hash(RSA *kak, struct secure_hdr_v1 *secure_hdr)
1278 hashf = fopen("pub_kak_hash.txt", "w");
1280 fprintf(stderr, "Couldn't open hash file: '%s': %s\n",
1281 "pub_kak_hash.txt", strerror(errno));
1285 res = kwb_export_pubkey(kak, &secure_hdr->kak, hashf, "KAK");
1289 return res < 0 ? 1 : 0;
1292 static int kwb_sign_csk_with_kak(struct image_tool_params *params,
1293 struct secure_hdr_v1 *secure_hdr, RSA *csk)
1296 RSA *kak_pub = NULL;
1297 int csk_idx = image_get_csk_index();
1298 struct sig_v1 tmp_sig;
1300 if (csk_idx < 0 || csk_idx > 15) {
1301 fprintf(stderr, "Invalid CSK index %d\n", csk_idx);
1305 if (kwb_load_kak(params, &kak) < 0)
1308 if (export_pub_kak_hash(kak, secure_hdr))
1311 if (kwb_import_pubkey(&kak_pub, &secure_hdr->kak, "KAK") < 0)
1314 if (kwb_export_pubkey(csk, &secure_hdr->csk[csk_idx], NULL, "CSK") < 0)
1317 if (kwb_sign_and_verify(kak, &secure_hdr->csk,
1318 sizeof(secure_hdr->csk) +
1319 sizeof(secure_hdr->csksig),
1320 &tmp_sig, "CSK") < 0)
1323 if (kwb_verify(kak_pub, &secure_hdr->csk,
1324 sizeof(secure_hdr->csk) +
1325 sizeof(secure_hdr->csksig),
1326 &tmp_sig, "CSK (2)") < 0)
1329 secure_hdr->csksig = tmp_sig;
1334 static int add_secure_header_v1(struct image_tool_params *params, uint8_t *ptr,
1335 int payloadsz, size_t headersz, uint8_t *image,
1336 struct secure_hdr_v1 *secure_hdr)
1338 struct image_cfg_element *e_jtagdelay;
1339 struct image_cfg_element *e_boxid;
1340 struct image_cfg_element *e_flashid;
1342 unsigned char *image_ptr;
1344 struct sig_v1 tmp_sig;
1345 bool specialized_img = image_get_spezialized_img();
1347 kwb_msg("Create secure header content\n");
1349 e_jtagdelay = image_find_option(IMAGE_CFG_JTAG_DELAY);
1350 e_boxid = image_find_option(IMAGE_CFG_BOX_ID);
1351 e_flashid = image_find_option(IMAGE_CFG_FLASH_ID);
1353 if (kwb_load_csk(params, &csk) < 0)
1356 secure_hdr->headertype = OPT_HDR_V1_SECURE_TYPE;
1357 secure_hdr->headersz_msb = 0;
1358 secure_hdr->headersz_lsb = cpu_to_le16(sizeof(struct secure_hdr_v1));
1360 secure_hdr->jtag_delay = e_jtagdelay->jtag_delay;
1361 if (e_boxid && specialized_img)
1362 secure_hdr->boxid = cpu_to_le32(e_boxid->boxid);
1363 if (e_flashid && specialized_img)
1364 secure_hdr->flashid = cpu_to_le32(e_flashid->flashid);
1366 if (kwb_sign_csk_with_kak(params, secure_hdr, csk))
1369 image_ptr = ptr + headersz;
1370 image_size = payloadsz - headersz;
1372 if (kwb_sign_and_verify(csk, image_ptr, image_size,
1373 &secure_hdr->imgsig, "image") < 0)
1376 if (kwb_sign_and_verify(csk, image, headersz, &tmp_sig, "header") < 0)
1379 secure_hdr->hdrsig = tmp_sig;
1381 kwb_dump_fuse_cmds(secure_hdr);
1386 static void finish_register_set_header_v1(uint8_t **cur, uint8_t **next_ext,
1387 struct register_set_hdr_v1 *register_set_hdr,
1388 int *datai, uint8_t delay)
1390 int size = sizeof(struct register_set_hdr_v1) + 8 * (*datai) + 4;
1392 register_set_hdr->headertype = OPT_HDR_V1_REGISTER_TYPE;
1393 register_set_hdr->headersz_lsb = cpu_to_le16(size & 0xFFFF);
1394 register_set_hdr->headersz_msb = size >> 16;
1395 register_set_hdr->data[*datai].last_entry.delay = delay;
1398 *next_ext = ®ister_set_hdr->data[*datai].last_entry.next;
1402 static void *image_create_v1(size_t *imagesz, struct image_tool_params *params,
1403 uint8_t *ptr, int payloadsz)
1405 struct image_cfg_element *e;
1406 struct main_hdr_v1 *main_hdr;
1407 struct opt_hdr_v1 *ohdr;
1408 struct register_set_hdr_v1 *register_set_hdr;
1409 struct secure_hdr_v1 *secure_hdr = NULL;
1411 uint8_t *image, *cur;
1413 uint8_t *next_ext = NULL;
1418 * Calculate the size of the header and the size of the
1421 headersz = image_headersz_v1(&hasext);
1425 image = malloc(headersz);
1427 fprintf(stderr, "Cannot allocate memory for image\n");
1431 memset(image, 0, headersz);
1433 main_hdr = (struct main_hdr_v1 *)image;
1435 cur += sizeof(struct main_hdr_v1);
1436 next_ext = &main_hdr->ext;
1438 /* Fill the main header */
1439 main_hdr->blocksize =
1440 cpu_to_le32(payloadsz);
1441 main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
1442 main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
1443 main_hdr->destaddr = cpu_to_le32(params->addr);
1444 main_hdr->execaddr = cpu_to_le32(params->ep);
1445 main_hdr->srcaddr = cpu_to_le32(headersz);
1446 main_hdr->ext = hasext;
1447 main_hdr->version = 1;
1448 main_hdr->blockid = image_get_bootfrom();
1450 e = image_find_option(IMAGE_CFG_NAND_BLKSZ);
1452 main_hdr->nandblocksize = e->nandblksz / (64 * 1024);
1453 e = image_find_option(IMAGE_CFG_NAND_PAGESZ);
1455 main_hdr->nandpagesize = cpu_to_le16(e->nandpagesz);
1456 e = image_find_option(IMAGE_CFG_NAND_BADBLK_LOCATION);
1458 main_hdr->nandbadblklocation = e->nandbadblklocation;
1459 e = image_find_option(IMAGE_CFG_BAUDRATE);
1461 main_hdr->options |= baudrate_to_option(e->baudrate);
1462 e = image_find_option(IMAGE_CFG_UART_PORT);
1464 main_hdr->options |= (e->uart_port & 3) << 3;
1465 e = image_find_option(IMAGE_CFG_UART_MPP);
1467 main_hdr->options |= (e->uart_mpp & 7) << 5;
1468 e = image_find_option(IMAGE_CFG_DEBUG);
1470 main_hdr->flags = e->debug ? 0x1 : 0;
1473 * For SATA srcaddr is specified in number of sectors starting from
1474 * sector 0. The main header is stored at sector number 1.
1475 * This expects the sector size to be 512 bytes.
1476 * Header size is already aligned.
1478 if (main_hdr->blockid == IBR_HDR_SATA_ID)
1479 main_hdr->srcaddr = cpu_to_le32(headersz / 512 + 1);
1482 * For SDIO srcaddr is specified in number of sectors starting from
1483 * sector 0. The main header is stored at sector number 0.
1484 * This expects sector size to be 512 bytes.
1485 * Header size is already aligned.
1487 if (main_hdr->blockid == IBR_HDR_SDIO_ID)
1488 main_hdr->srcaddr = cpu_to_le32(headersz / 512);
1490 /* For PCIe srcaddr is not used and must be set to 0xFFFFFFFF. */
1491 if (main_hdr->blockid == IBR_HDR_PEX_ID)
1492 main_hdr->srcaddr = cpu_to_le32(0xFFFFFFFF);
1494 if (image_get_csk_index() >= 0) {
1496 * only reserve the space here; we fill the header later since
1497 * we need the header to be complete to compute the signatures
1499 secure_hdr = (struct secure_hdr_v1 *)cur;
1500 cur += sizeof(struct secure_hdr_v1);
1502 next_ext = &secure_hdr->next;
1506 for (cfgi = 0; cfgi < cfgn; cfgi++) {
1507 e = &image_cfg[cfgi];
1508 if (e->type != IMAGE_CFG_DATA &&
1509 e->type != IMAGE_CFG_DATA_DELAY &&
1510 e->type != IMAGE_CFG_BINARY)
1514 register_set_hdr = (struct register_set_hdr_v1 *)cur;
1516 /* If delay is not specified, use the smallest possible value. */
1517 if (e->type == IMAGE_CFG_DATA_DELAY)
1518 delay = e->regdata_delay;
1520 delay = REGISTER_SET_HDR_OPT_DELAY_MS(0);
1523 * DATA_DELAY command is the last entry in the register set
1524 * header and BINARY command inserts new binary header.
1525 * Therefore BINARY command requires to finish register set
1526 * header if some DATA command was specified. And DATA_DELAY
1527 * command automatically finish register set header even when
1528 * there was no DATA command.
1530 if (e->type == IMAGE_CFG_DATA_DELAY ||
1531 (e->type == IMAGE_CFG_BINARY && datai != 0))
1532 finish_register_set_header_v1(&cur, &next_ext, register_set_hdr,
1535 if (e->type == IMAGE_CFG_DATA) {
1536 register_set_hdr->data[datai].entry.address =
1537 cpu_to_le32(e->regdata.raddr);
1538 register_set_hdr->data[datai].entry.value =
1539 cpu_to_le32(e->regdata.rdata);
1543 if (e->type == IMAGE_CFG_BINARY) {
1544 if (add_binary_header_v1(&cur, &next_ext, e, main_hdr))
1549 /* Set delay to the smallest possible value. */
1550 delay = REGISTER_SET_HDR_OPT_DELAY_MS(0);
1551 finish_register_set_header_v1(&cur, &next_ext, register_set_hdr,
1555 if (secure_hdr && add_secure_header_v1(params, ptr, payloadsz + headersz,
1556 headersz, image, secure_hdr))
1559 *imagesz = headersz;
1561 /* Fill the real header size without padding into the main header */
1562 headersz = sizeof(*main_hdr);
1563 for_each_opt_hdr_v1 (ohdr, main_hdr)
1564 headersz += opt_hdr_v1_size(ohdr);
1565 main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
1566 main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
1568 /* Calculate and set the header checksum */
1569 main_hdr->checksum = image_checksum8(main_hdr, headersz);
1574 static int recognize_keyword(char *keyword)
1578 for (kw_id = 1; kw_id < IMAGE_CFG_COUNT; ++kw_id)
1579 if (!strcmp(keyword, id_strs[kw_id]))
1585 static int image_create_config_parse_oneline(char *line,
1586 struct image_cfg_element *el)
1588 char *keyword, *saveptr, *value1, *value2;
1589 char delimiters[] = " \t";
1590 int keyword_id, ret, argi;
1591 char *unknown_msg = "Ignoring unknown line '%s'\n";
1593 keyword = strtok_r(line, delimiters, &saveptr);
1594 keyword_id = recognize_keyword(keyword);
1597 fprintf(stderr, unknown_msg, line);
1601 el->type = keyword_id;
1603 value1 = strtok_r(NULL, delimiters, &saveptr);
1606 fprintf(stderr, "Parameter missing in line '%s'\n", line);
1610 switch (keyword_id) {
1611 case IMAGE_CFG_VERSION:
1612 el->version = atoi(value1);
1615 if (strcmp(value1, "FEROCEON") == 0)
1617 else if (strcmp(value1, "SHEEVA") == 0)
1619 else if (strcmp(value1, "A9") == 0)
1622 fprintf(stderr, "Invalid CPU %s\n", value1);
1626 case IMAGE_CFG_BOOT_FROM:
1627 ret = image_boot_mode_id(value1);
1630 fprintf(stderr, "Invalid boot media '%s'\n", value1);
1635 case IMAGE_CFG_NAND_BLKSZ:
1636 el->nandblksz = strtoul(value1, NULL, 16);
1638 case IMAGE_CFG_NAND_BADBLK_LOCATION:
1639 el->nandbadblklocation = strtoul(value1, NULL, 16);
1641 case IMAGE_CFG_NAND_ECC_MODE:
1642 ret = image_nand_ecc_mode_id(value1);
1645 fprintf(stderr, "Invalid NAND ECC mode '%s'\n", value1);
1648 el->nandeccmode = ret;
1650 case IMAGE_CFG_NAND_PAGESZ:
1651 el->nandpagesz = strtoul(value1, NULL, 16);
1653 case IMAGE_CFG_BINARY:
1656 el->binary.file = strdup(value1);
1658 char *value = strtok_r(NULL, delimiters, &saveptr);
1664 if (!strcmp(value, "LOAD_ADDRESS")) {
1665 value = strtok_r(NULL, delimiters, &saveptr);
1668 "Missing address argument for BINARY LOAD_ADDRESS\n");
1671 el->binary.loadaddr = strtoul(value, &endptr, 16);
1674 "Invalid argument '%s' for BINARY LOAD_ADDRESS\n",
1678 value = strtok_r(NULL, delimiters, &saveptr);
1681 "Unexpected argument '%s' after BINARY LOAD_ADDRESS\n",
1688 el->binary.args[argi] = strtoul(value, &endptr, 16);
1690 fprintf(stderr, "Invalid argument '%s' for BINARY\n", value);
1694 if (argi >= BINARY_MAX_ARGS) {
1696 "Too many arguments for BINARY\n");
1700 el->binary.nargs = argi;
1702 case IMAGE_CFG_DATA:
1703 value2 = strtok_r(NULL, delimiters, &saveptr);
1705 if (!value1 || !value2) {
1707 "Invalid number of arguments for DATA\n");
1711 el->regdata.raddr = strtoul(value1, NULL, 16);
1712 el->regdata.rdata = strtoul(value2, NULL, 16);
1714 case IMAGE_CFG_DATA_DELAY:
1715 if (!strcmp(value1, "SDRAM_SETUP"))
1716 el->regdata_delay = REGISTER_SET_HDR_OPT_DELAY_SDRAM_SETUP;
1718 el->regdata_delay = REGISTER_SET_HDR_OPT_DELAY_MS(strtoul(value1, NULL, 10));
1719 if (el->regdata_delay > 255) {
1720 fprintf(stderr, "Maximal DATA_DELAY is 255\n");
1724 case IMAGE_CFG_BAUDRATE:
1725 el->baudrate = strtoul(value1, NULL, 10);
1727 case IMAGE_CFG_UART_PORT:
1728 el->uart_port = strtoul(value1, NULL, 16);
1730 case IMAGE_CFG_UART_MPP:
1731 el->uart_mpp = strtoul(value1, NULL, 16);
1733 case IMAGE_CFG_DEBUG:
1734 el->debug = strtoul(value1, NULL, 10);
1737 el->key_name = strdup(value1);
1740 el->key_name = strdup(value1);
1742 case IMAGE_CFG_CSK_INDEX:
1743 el->csk_idx = strtol(value1, NULL, 0);
1745 case IMAGE_CFG_JTAG_DELAY:
1746 el->jtag_delay = strtoul(value1, NULL, 0);
1748 case IMAGE_CFG_BOX_ID:
1749 el->boxid = strtoul(value1, NULL, 0);
1751 case IMAGE_CFG_FLASH_ID:
1752 el->flashid = strtoul(value1, NULL, 0);
1754 case IMAGE_CFG_SEC_SPECIALIZED_IMG:
1755 el->sec_specialized_img = true;
1757 case IMAGE_CFG_SEC_COMMON_IMG:
1758 el->sec_specialized_img = false;
1760 case IMAGE_CFG_SEC_BOOT_DEV:
1761 el->sec_boot_dev = strtoul(value1, NULL, 0);
1763 case IMAGE_CFG_SEC_FUSE_DUMP:
1764 el->name = strdup(value1);
1767 fprintf(stderr, unknown_msg, line);
1774 * Parse the configuration file 'fcfg' into the array of configuration
1775 * elements 'image_cfg', and return the number of configuration
1776 * elements in 'cfgn'.
1778 static int image_create_config_parse(FILE *fcfg)
1783 /* Parse the configuration file */
1784 while (!feof(fcfg)) {
1788 /* Read the current line */
1789 memset(buf, 0, sizeof(buf));
1790 line = fgets(buf, sizeof(buf), fcfg);
1794 /* Ignore useless lines */
1795 if (line[0] == '\n' || line[0] == '#')
1798 /* Strip final newline */
1799 if (line[strlen(line) - 1] == '\n')
1800 line[strlen(line) - 1] = 0;
1802 /* Parse the current line */
1803 ret = image_create_config_parse_oneline(line,
1810 if (cfgi >= IMAGE_CFG_ELEMENT_MAX) {
1812 "Too many configuration elements in .cfg file\n");
1821 static int image_get_version(void)
1823 struct image_cfg_element *e;
1825 e = image_find_option(IMAGE_CFG_VERSION);
1832 static void kwbimage_set_header(void *ptr, struct stat *sbuf, int ifd,
1833 struct image_tool_params *params)
1838 size_t headersz = 0;
1845 * Do not use sbuf->st_size as it contains size with padding.
1846 * We need original image data size, so stat original file.
1848 if (stat(params->datafile, &s)) {
1849 fprintf(stderr, "Could not stat data file %s: %s\n",
1850 params->datafile, strerror(errno));
1853 datasz = ALIGN(s.st_size, 4);
1855 fcfg = fopen(params->imagename, "r");
1857 fprintf(stderr, "Could not open input file %s\n",
1862 image_cfg = malloc(IMAGE_CFG_ELEMENT_MAX *
1863 sizeof(struct image_cfg_element));
1865 fprintf(stderr, "Cannot allocate memory\n");
1870 memset(image_cfg, 0,
1871 IMAGE_CFG_ELEMENT_MAX * sizeof(struct image_cfg_element));
1874 ret = image_create_config_parse(fcfg);
1881 version = image_get_version();
1884 * Fallback to version 0 if no version is provided in the
1889 image = image_create_v0(&headersz, params, datasz + 4);
1893 image = image_create_v1(&headersz, params, ptr, datasz + 4);
1897 fprintf(stderr, "Unsupported version %d\n", version);
1903 fprintf(stderr, "Could not create image\n");
1910 /* Build and add image data checksum */
1911 checksum = cpu_to_le32(image_checksum32((uint8_t *)ptr + headersz,
1913 memcpy((uint8_t *)ptr + headersz + datasz, &checksum, sizeof(uint32_t));
1915 /* Finally copy the header into the image area */
1916 memcpy(ptr, image, headersz);
1921 static void kwbimage_print_header(const void *ptr)
1923 struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr;
1924 struct bin_hdr_v0 *bhdr;
1925 struct opt_hdr_v1 *ohdr;
1927 printf("Image Type: MVEBU Boot from %s Image\n",
1928 image_boot_mode_name(mhdr->blockid));
1929 printf("Image version:%d\n", kwbimage_version(ptr));
1931 for_each_opt_hdr_v1 (ohdr, mhdr) {
1932 if (ohdr->headertype == OPT_HDR_V1_BINARY_TYPE) {
1933 printf("BIN Img Size: ");
1934 genimg_print_size(opt_hdr_v1_size(ohdr) - 12 -
1936 printf("BIN Img Offs: %08x\n",
1937 (unsigned)((uint8_t *)ohdr - (uint8_t *)mhdr) +
1938 8 + 4 * ohdr->data[0]);
1942 for_each_bin_hdr_v0(bhdr, mhdr) {
1943 printf("BIN Img Size: ");
1944 genimg_print_size(le32_to_cpu(bhdr->size));
1945 printf("BIN Img Addr: %08x\n", le32_to_cpu(bhdr->destaddr));
1946 printf("BIN Img Entr: %08x\n", le32_to_cpu(bhdr->execaddr));
1949 printf("Data Size: ");
1950 genimg_print_size(mhdr->blocksize - sizeof(uint32_t));
1951 printf("Load Address: %08x\n", mhdr->destaddr);
1952 printf("Entry Point: %08x\n", mhdr->execaddr);
1955 static int kwbimage_check_image_types(uint8_t type)
1957 if (type == IH_TYPE_KWBIMAGE)
1958 return EXIT_SUCCESS;
1960 return EXIT_FAILURE;
1963 static int kwbimage_verify_header(unsigned char *ptr, int image_size,
1964 struct image_tool_params *params)
1966 size_t header_size = kwbheader_size(ptr);
1972 if (header_size > 192*1024)
1973 return -FDT_ERR_BADSTRUCTURE;
1975 if (header_size > image_size)
1976 return -FDT_ERR_BADSTRUCTURE;
1978 if (!main_hdr_checksum_ok(ptr))
1979 return -FDT_ERR_BADSTRUCTURE;
1981 /* Only version 0 extended header has checksum */
1982 if (kwbimage_version(ptr) == 0) {
1983 struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr;
1984 struct ext_hdr_v0 *ext_hdr;
1985 struct bin_hdr_v0 *bhdr;
1987 for_each_ext_hdr_v0(ext_hdr, ptr) {
1988 csum = image_checksum8(ext_hdr, sizeof(*ext_hdr) - 1);
1989 if (csum != ext_hdr->checksum)
1990 return -FDT_ERR_BADSTRUCTURE;
1993 for_each_bin_hdr_v0(bhdr, ptr) {
1994 csum = image_checksum8(bhdr, (uint8_t *)&bhdr->checksum - (uint8_t *)bhdr - 1);
1995 if (csum != bhdr->checksum)
1996 return -FDT_ERR_BADSTRUCTURE;
1998 if (bhdr->offset > sizeof(*bhdr) || bhdr->offset % 4 != 0)
1999 return -FDT_ERR_BADSTRUCTURE;
2001 if (bhdr->offset + bhdr->size + 4 > sizeof(*bhdr) || bhdr->size % 4 != 0)
2002 return -FDT_ERR_BADSTRUCTURE;
2004 if (image_checksum32((uint8_t *)bhdr + bhdr->offset, bhdr->size) !=
2005 *(uint32_t *)((uint8_t *)bhdr + bhdr->offset + bhdr->size))
2006 return -FDT_ERR_BADSTRUCTURE;
2009 blockid = mhdr->blockid;
2010 offset = le32_to_cpu(mhdr->srcaddr);
2011 size = le32_to_cpu(mhdr->blocksize);
2012 } else if (kwbimage_version(ptr) == 1) {
2013 struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
2014 const uint8_t *mhdr_end;
2015 struct opt_hdr_v1 *ohdr;
2017 mhdr_end = (uint8_t *)mhdr + header_size;
2018 for_each_opt_hdr_v1 (ohdr, ptr)
2019 if (!opt_hdr_v1_valid_size(ohdr, mhdr_end))
2020 return -FDT_ERR_BADSTRUCTURE;
2022 blockid = mhdr->blockid;
2023 offset = le32_to_cpu(mhdr->srcaddr);
2024 size = le32_to_cpu(mhdr->blocksize);
2026 return -FDT_ERR_BADSTRUCTURE;
2030 * For SATA srcaddr is specified in number of sectors.
2031 * The main header is must be stored at sector number 1.
2032 * This expects that sector size is 512 bytes and recalculates
2033 * data offset to bytes relative to the main header.
2035 if (blockid == IBR_HDR_SATA_ID) {
2037 return -FDT_ERR_BADSTRUCTURE;
2043 * For SDIO srcaddr is specified in number of sectors.
2044 * This expects that sector size is 512 bytes and recalculates
2045 * data offset to bytes.
2047 if (blockid == IBR_HDR_SDIO_ID)
2051 * For PCIe srcaddr is always set to 0xFFFFFFFF.
2052 * This expects that data starts after all headers.
2054 if (blockid == IBR_HDR_PEX_ID && offset == 0xFFFFFFFF)
2055 offset = header_size;
2057 if (offset > image_size || offset % 4 != 0)
2058 return -FDT_ERR_BADSTRUCTURE;
2060 if (size < 4 || offset + size > image_size || size % 4 != 0)
2061 return -FDT_ERR_BADSTRUCTURE;
2063 if (image_checksum32(ptr + offset, size - 4) !=
2064 *(uint32_t *)(ptr + offset + size - 4))
2065 return -FDT_ERR_BADSTRUCTURE;
2070 static int kwbimage_generate(struct image_tool_params *params,
2071 struct image_type_params *tparams)
2081 fcfg = fopen(params->imagename, "r");
2083 fprintf(stderr, "Could not open input file %s\n",
2088 if (stat(params->datafile, &s)) {
2089 fprintf(stderr, "Could not stat data file %s: %s\n",
2090 params->datafile, strerror(errno));
2094 image_cfg = malloc(IMAGE_CFG_ELEMENT_MAX *
2095 sizeof(struct image_cfg_element));
2097 fprintf(stderr, "Cannot allocate memory\n");
2102 memset(image_cfg, 0,
2103 IMAGE_CFG_ELEMENT_MAX * sizeof(struct image_cfg_element));
2106 ret = image_create_config_parse(fcfg);
2113 bootfrom = image_get_bootfrom();
2114 version = image_get_version();
2117 * Fallback to version 0 if no version is provided in the
2122 alloc_len = image_headersz_v0(NULL);
2126 alloc_len = image_headersz_v1(NULL);
2131 if (alloc_len > 192*1024) {
2132 fprintf(stderr, "Header is too big (%u bytes), maximal kwbimage header size is %u bytes\n", alloc_len, 192*1024);
2139 fprintf(stderr, "Unsupported version %d\n", version);
2146 hdr = malloc(alloc_len);
2148 fprintf(stderr, "%s: malloc return failure: %s\n",
2149 params->cmdname, strerror(errno));
2153 memset(hdr, 0, alloc_len);
2154 tparams->header_size = alloc_len;
2158 * The resulting image needs to be 4-byte aligned. At least
2159 * the Marvell hdrparser tool complains if its unaligned.
2160 * After the image data is stored 4-byte checksum.
2161 * Final UART image must be aligned to 128 bytes.
2162 * Final SPI and NAND images must be aligned to 256 bytes.
2163 * Final SATA and SDIO images must be aligned to 512 bytes.
2165 if (bootfrom == IBR_HDR_SPI_ID || bootfrom == IBR_HDR_NAND_ID)
2166 return 4 + (256 - (alloc_len + s.st_size + 4) % 256) % 256;
2167 else if (bootfrom == IBR_HDR_SATA_ID || bootfrom == IBR_HDR_SDIO_ID)
2168 return 4 + (512 - (alloc_len + s.st_size + 4) % 512) % 512;
2169 else if (bootfrom == IBR_HDR_UART_ID)
2170 return 4 + (128 - (alloc_len + s.st_size + 4) % 128) % 128;
2172 return 4 + (4 - s.st_size % 4) % 4;
2175 static int kwbimage_generate_config(void *ptr, struct image_tool_params *params)
2177 struct main_hdr_v0 *mhdr0 = (struct main_hdr_v0 *)ptr;
2178 struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
2179 size_t header_size = kwbheader_size(ptr);
2180 struct register_set_hdr_v1 *regset_hdr;
2181 struct ext_hdr_v0_reg *regdata;
2182 struct ext_hdr_v0 *ehdr0;
2183 struct bin_hdr_v0 *bhdr0;
2184 struct opt_hdr_v1 *ohdr;
2193 f = fopen(params->outfile, "w");
2195 fprintf(stderr, "Can't open \"%s\": %s\n", params->outfile, strerror(errno));
2199 version = kwbimage_version(ptr);
2203 if (mhdr0->ext > 1 || mhdr0->bin ||
2204 ((ehdr0 = ext_hdr_v0_first(ptr)) &&
2205 (ehdr0->match_addr || ehdr0->match_mask || ehdr0->match_value)))
2210 fprintf(f, "VERSION %d\n", version);
2212 fprintf(f, "BOOT_FROM %s\n", image_boot_mode_name(mhdr->blockid) ?: "<unknown>");
2214 if (version == 0 && mhdr->blockid == IBR_HDR_NAND_ID)
2215 fprintf(f, "NAND_ECC_MODE %s\n", image_nand_ecc_mode_name(mhdr0->nandeccmode));
2217 if (mhdr->blockid == IBR_HDR_NAND_ID)
2218 fprintf(f, "NAND_PAGE_SIZE 0x%x\n", (unsigned)mhdr->nandpagesize);
2220 if (version != 0 && mhdr->blockid == IBR_HDR_NAND_ID)
2221 fprintf(f, "NAND_BLKSZ 0x%x\n", (unsigned)mhdr->nandblocksize);
2223 if (mhdr->blockid == IBR_HDR_NAND_ID && (mhdr->nandbadblklocation != 0 || is_v0_ext))
2224 fprintf(f, "NAND_BADBLK_LOCATION 0x%x\n", (unsigned)mhdr->nandbadblklocation);
2226 if (version == 0 && mhdr->blockid == IBR_HDR_SATA_ID)
2227 fprintf(f, "SATA_PIO_MODE %u\n", (unsigned)mhdr0->satapiomode);
2230 * Addresses and sizes which are specified by mkimage command line
2231 * arguments and not in kwbimage config file
2235 fprintf(f, "#HEADER_SIZE 0x%x\n",
2236 ((unsigned)mhdr->headersz_msb << 8) | le16_to_cpu(mhdr->headersz_lsb));
2238 fprintf(f, "#SRC_ADDRESS 0x%x\n", le32_to_cpu(mhdr->srcaddr));
2239 fprintf(f, "#BLOCK_SIZE 0x%x\n", le32_to_cpu(mhdr->blocksize));
2240 fprintf(f, "#DEST_ADDRESS 0x%08x\n", le32_to_cpu(mhdr->destaddr));
2241 fprintf(f, "#EXEC_ADDRESS 0x%08x\n", le32_to_cpu(mhdr->execaddr));
2244 if (options_to_baudrate(mhdr->options))
2245 fprintf(f, "BAUDRATE %u\n", options_to_baudrate(mhdr->options));
2246 if (options_to_baudrate(mhdr->options) ||
2247 ((mhdr->options >> 3) & 0x3) || ((mhdr->options >> 5) & 0x7)) {
2248 fprintf(f, "UART_PORT %u\n", (unsigned)((mhdr->options >> 3) & 0x3));
2249 fprintf(f, "UART_MPP 0x%x\n", (unsigned)((mhdr->options >> 5) & 0x7));
2251 if (mhdr->flags & 0x1)
2252 fprintf(f, "DEBUG 1\n");
2256 for_each_opt_hdr_v1(ohdr, ptr) {
2257 if (ohdr->headertype == OPT_HDR_V1_SECURE_TYPE) {
2258 fprintf(f, "#SECURE_HEADER\n");
2259 } else if (ohdr->headertype == OPT_HDR_V1_BINARY_TYPE) {
2260 fprintf(f, "BINARY binary%d.bin", cur_idx);
2261 for (i = 0; i < ohdr->data[0]; i++)
2262 fprintf(f, " 0x%x", le32_to_cpu(((uint32_t *)ohdr->data)[i + 1]));
2263 offset = (unsigned)((uint8_t *)ohdr - (uint8_t *)mhdr) + 8 + 4 * ohdr->data[0];
2264 fprintf(f, " LOAD_ADDRESS 0x%08x\n", 0x40000000 + offset);
2265 fprintf(f, " # for CPU SHEEVA: LOAD_ADDRESS 0x%08x\n", 0x40004000 + offset);
2267 } else if (ohdr->headertype == OPT_HDR_V1_REGISTER_TYPE) {
2268 regset_hdr = (struct register_set_hdr_v1 *)ohdr;
2270 i < opt_hdr_v1_size(ohdr) - sizeof(struct opt_hdr_v1) -
2271 sizeof(regset_hdr->data[0].last_entry);
2273 fprintf(f, "DATA 0x%08x 0x%08x\n",
2274 le32_to_cpu(regset_hdr->data[i].entry.address),
2275 le32_to_cpu(regset_hdr->data[i].entry.value));
2276 if (opt_hdr_v1_size(ohdr) - sizeof(struct opt_hdr_v1) >=
2277 sizeof(regset_hdr->data[0].last_entry)) {
2278 if (regset_hdr->data[0].last_entry.delay)
2279 fprintf(f, "DATA_DELAY %u\n",
2280 (unsigned)regset_hdr->data[0].last_entry.delay);
2282 fprintf(f, "DATA_DELAY SDRAM_SETUP\n");
2287 if (version == 0 && !is_v0_ext && le16_to_cpu(mhdr0->ddrinitdelay))
2288 fprintf(f, "DDR_INIT_DELAY %u\n", (unsigned)le16_to_cpu(mhdr0->ddrinitdelay));
2290 for_each_ext_hdr_v0(ehdr0, ptr) {
2292 fprintf(f, "\nMATCH ADDRESS 0x%08x MASK 0x%08x VALUE 0x%08x\n",
2293 le32_to_cpu(ehdr0->match_addr),
2294 le32_to_cpu(ehdr0->match_mask),
2295 le32_to_cpu(ehdr0->match_value));
2296 if (ehdr0->rsvd1[0] || ehdr0->rsvd1[1] || ehdr0->rsvd1[2] ||
2297 ehdr0->rsvd1[3] || ehdr0->rsvd1[4] || ehdr0->rsvd1[5] ||
2298 ehdr0->rsvd1[6] || ehdr0->rsvd1[7])
2299 fprintf(f, "#DDR_RSVD1 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
2300 ehdr0->rsvd1[0], ehdr0->rsvd1[1], ehdr0->rsvd1[2],
2301 ehdr0->rsvd1[3], ehdr0->rsvd1[4], ehdr0->rsvd1[5],
2302 ehdr0->rsvd1[6], ehdr0->rsvd1[7]);
2303 if (ehdr0->rsvd2[0] || ehdr0->rsvd2[1] || ehdr0->rsvd2[2] ||
2304 ehdr0->rsvd2[3] || ehdr0->rsvd2[4] || ehdr0->rsvd2[5] ||
2306 fprintf(f, "#DDR_RSVD2 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
2307 ehdr0->rsvd2[0], ehdr0->rsvd2[1], ehdr0->rsvd2[2],
2308 ehdr0->rsvd2[3], ehdr0->rsvd2[4], ehdr0->rsvd2[5],
2310 if (ehdr0->ddrwritetype)
2311 fprintf(f, "DDR_WRITE_TYPE %u\n", (unsigned)ehdr0->ddrwritetype);
2312 if (ehdr0->ddrresetmpp)
2313 fprintf(f, "DDR_RESET_MPP 0x%x\n", (unsigned)ehdr0->ddrresetmpp);
2314 if (ehdr0->ddrclkenmpp)
2315 fprintf(f, "DDR_CLKEN_MPP 0x%x\n", (unsigned)ehdr0->ddrclkenmpp);
2316 if (ehdr0->ddrinitdelay)
2317 fprintf(f, "DDR_INIT_DELAY %u\n", (unsigned)ehdr0->ddrinitdelay);
2320 if (ehdr0->offset) {
2321 for (regdata = (struct ext_hdr_v0_reg *)((uint8_t *)ptr + ehdr0->offset);
2322 (uint8_t *)regdata < (uint8_t *)ptr + header_size &&
2323 (regdata->raddr || regdata->rdata);
2325 fprintf(f, "DATA 0x%08x 0x%08x\n", le32_to_cpu(regdata->raddr),
2326 le32_to_cpu(regdata->rdata));
2327 if ((uint8_t *)regdata != (uint8_t *)ptr + ehdr0->offset)
2328 fprintf(f, "DATA 0x0 0x0\n");
2331 if (le32_to_cpu(ehdr0->enddelay))
2332 fprintf(f, "DATA_DELAY %u\n", le32_to_cpu(ehdr0->enddelay));
2334 fprintf(f, "DATA_DELAY SDRAM_SETUP\n");
2338 for_each_bin_hdr_v0(bhdr0, ptr) {
2339 fprintf(f, "\nMATCH ADDRESS 0x%08x MASK 0x%08x VALUE 0x%08x\n",
2340 le32_to_cpu(bhdr0->match_addr),
2341 le32_to_cpu(bhdr0->match_mask),
2342 le32_to_cpu(bhdr0->match_value));
2344 fprintf(f, "BINARY binary%d.bin", cur_idx);
2345 params_count = fls4(bhdr0->params_flags & 0xF);
2346 for (i = 0; i < params_count; i++)
2347 fprintf(f, " 0x%x", (bhdr0->params[i] & (1 << i)) ? bhdr0->params[i] : 0);
2348 fprintf(f, " LOAD_ADDRESS 0x%08x", le32_to_cpu(bhdr0->destaddr));
2349 fprintf(f, " EXEC_ADDRESS 0x%08x", le32_to_cpu(bhdr0->execaddr));
2352 fprintf(f, "#BINARY_OFFSET 0x%x\n", le32_to_cpu(bhdr0->offset));
2353 fprintf(f, "#BINARY_SIZE 0x%x\n", le32_to_cpu(bhdr0->size));
2356 fprintf(f, "#BINARY_RSVD1 0x%x\n", (unsigned)bhdr0->rsvd1);
2358 fprintf(f, "#BINARY_RSVD2 0x%x\n", (unsigned)bhdr0->rsvd2);
2363 /* Undocumented reserved fields */
2365 if (version == 0 && (mhdr0->rsvd1[0] || mhdr0->rsvd1[1] || mhdr0->rsvd1[2]))
2366 fprintf(f, "#RSVD1 0x%x 0x%x 0x%x\n", (unsigned)mhdr0->rsvd1[0],
2367 (unsigned)mhdr0->rsvd1[1], (unsigned)mhdr0->rsvd1[2]);
2369 if (version == 0 && le16_to_cpu(mhdr0->rsvd2))
2370 fprintf(f, "#RSVD2 0x%x\n", (unsigned)le16_to_cpu(mhdr0->rsvd2));
2372 if (version != 0 && mhdr->reserved4)
2373 fprintf(f, "#RESERVED4 0x%x\n", (unsigned)mhdr->reserved4);
2375 if (version != 0 && mhdr->reserved5)
2376 fprintf(f, "#RESERVED5 0x%x\n", (unsigned)le16_to_cpu(mhdr->reserved5));
2383 static int kwbimage_extract_subimage(void *ptr, struct image_tool_params *params)
2385 struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
2386 size_t header_size = kwbheader_size(ptr);
2387 struct bin_hdr_v0 *bhdr;
2388 struct opt_hdr_v1 *ohdr;
2389 int idx = params->pflag;
2395 /* Generate kwbimage config file when '-p -1' is specified */
2397 return kwbimage_generate_config(ptr, params);
2403 /* Extract data image when -p is not specified or when '-p 0' is specified */
2404 offset = le32_to_cpu(mhdr->srcaddr);
2406 if (mhdr->blockid == IBR_HDR_SATA_ID) {
2411 if (mhdr->blockid == IBR_HDR_SDIO_ID)
2414 if (mhdr->blockid == IBR_HDR_PEX_ID && offset == 0xFFFFFFFF)
2415 offset = header_size;
2417 image = (ulong)((uint8_t *)ptr + offset);
2418 size = le32_to_cpu(mhdr->blocksize) - 4;
2420 /* Extract N-th binary header executabe image when other '-p N' is specified */
2422 for_each_opt_hdr_v1(ohdr, ptr) {
2423 if (ohdr->headertype != OPT_HDR_V1_BINARY_TYPE)
2426 if (idx == cur_idx) {
2427 image = (ulong)&ohdr->data[4 + 4 * ohdr->data[0]];
2428 size = opt_hdr_v1_size(ohdr) - 12 - 4 * ohdr->data[0];
2434 for_each_bin_hdr_v0(bhdr, ptr) {
2435 if (idx == cur_idx) {
2436 image = (ulong)bhdr + bhdr->offset;
2444 fprintf(stderr, "Argument -p %d is invalid\n", idx);
2445 fprintf(stderr, "Available subimages:\n");
2446 fprintf(stderr, " -p -1 - kwbimage config file\n");
2447 fprintf(stderr, " -p 0 - data image\n");
2448 if (cur_idx - 1 > 0)
2449 fprintf(stderr, " -p N - Nth binary header image (totally: %d)\n",
2455 return imagetool_save_subimage(params->outfile, image, size);
2459 * Report Error if xflag is set in addition to default
2461 static int kwbimage_check_params(struct image_tool_params *params)
2463 if (!params->lflag && !params->iflag && !params->pflag &&
2464 (!params->imagename || !strlen(params->imagename))) {
2465 char *msg = "Configuration file for kwbimage creation omitted";
2467 fprintf(stderr, "Error:%s - %s\n", params->cmdname, msg);
2471 return (params->dflag && (params->fflag || params->lflag)) ||
2472 (params->fflag && (params->dflag || params->lflag)) ||
2473 (params->lflag && (params->dflag || params->fflag)) ||
2478 * kwbimage type parameters definition
2482 "Marvell MVEBU Boot Image support",
2485 kwbimage_check_params,
2486 kwbimage_verify_header,
2487 kwbimage_print_header,
2488 kwbimage_set_header,
2489 kwbimage_extract_subimage,
2490 kwbimage_check_image_types,