3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 */
28 #define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
29 #define APP_CODE_BARKER 0xB1
30 #define DCD_BARKER 0xB17219E9
32 #define HEADER_OFFSET 0x400
35 * NOTE: This file must be kept in sync with arch/arm/include/asm/\
36 * imx-common/imximage.cfg because tools/imximage.c can not
37 * cross-include headers from arch/arm/ and vice-versa.
39 #define CMD_DATA_STR "DATA"
40 #define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
41 #define FLASH_OFFSET_STANDARD 0x400
42 #define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
43 #define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD
44 #define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD
45 #define FLASH_OFFSET_ONENAND 0x100
46 #define FLASH_OFFSET_NOR 0x1000
47 #define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
49 #define IVT_HEADER_TAG 0xD1
50 #define IVT_VERSION 0x40
51 #define DCD_HEADER_TAG 0xD2
52 #define DCD_COMMAND_TAG 0xCC
53 #define DCD_VERSION 0x40
54 #define DCD_COMMAND_PARAM 0x4
64 enum imximage_fld_types {
72 enum imximage_version {
73 IMXIMAGE_VER_INVALID = -1,
79 uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */
80 uint32_t addr; /* Address to write to */
81 uint32_t value; /* Data to write */
82 } dcd_type_addr_data_t;
85 uint32_t barker; /* Barker for sanity check */
86 uint32_t length; /* Device configuration length (without preamble) */
90 dcd_preamble_t preamble;
91 dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1];
95 uint32_t app_code_jump_vector;
96 uint32_t app_code_barker;
97 uint32_t app_code_csf;
99 uint32_t super_root_key;
101 uint32_t app_dest_ptr;
105 uint32_t length; /* Length of data to be read from flash */
109 flash_header_v1_t fhdr;
111 flash_cfg_parms_t ext_header;
123 } __attribute__((packed)) ivt_header_t;
129 } __attribute__((packed)) write_dcd_command_t;
133 write_dcd_command_t write_dcd_command;
134 dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
148 uint32_t boot_data_ptr;
155 flash_header_v2_t fhdr;
156 boot_data_t boot_data;
160 /* The header must be aligned to 4k on MX53 for NAND boot */
163 imx_header_v1_t hdr_v1;
164 imx_header_v2_t hdr_v2;
166 uint32_t flash_offset;
167 } __attribute__((aligned(4096)));
169 typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
170 char *name, int lineno,
171 int fld, uint32_t value,
174 typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
176 char *name, int lineno);
178 typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
179 uint32_t entry_point, uint32_t flash_offset);
181 #endif /* _IMXIMAGE_H_ */